TW201611141A - 用以製造基材配接器的方法、基材配接器及用於提供與半導體元件接觸的目的之方法 - Google Patents
用以製造基材配接器的方法、基材配接器及用於提供與半導體元件接觸的目的之方法 Download PDFInfo
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- TW201611141A TW201611141A TW104121712A TW104121712A TW201611141A TW 201611141 A TW201611141 A TW 201611141A TW 104121712 A TW104121712 A TW 104121712A TW 104121712 A TW104121712 A TW 104121712A TW 201611141 A TW201611141 A TW 201611141A
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- 238000000034 method Methods 0.000 title claims abstract description 99
- 239000000758 substrate Substances 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 186
- 239000002184 metal Substances 0.000 claims abstract description 185
- 239000000463 material Substances 0.000 claims abstract description 127
- 239000011248 coating agent Substances 0.000 claims description 46
- 238000000576 coating method Methods 0.000 claims description 46
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 238000004049 embossing Methods 0.000 claims description 7
- 239000004820 Pressure-sensitive adhesive Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000011889 copper foil Substances 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 239000002313 adhesive film Substances 0.000 claims description 4
- 238000005246 galvanizing Methods 0.000 claims description 4
- 238000003698 laser cutting Methods 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000011888 foil Substances 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 229940100890 silver compound Drugs 0.000 claims description 3
- 150000003379 silver compounds Chemical class 0.000 claims description 3
- 239000007921 spray Substances 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 238000005304 joining Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 238000003825 pressing Methods 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 229910001316 Ag alloy Inorganic materials 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 239000000543 intermediate Substances 0.000 description 2
- 239000013067 intermediate product Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000637 aluminium metallisation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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Abstract
本發明有關於用以製造基材配接器之方法,它特別用來提供與半導體元件的接觸,其係包含下列步驟:- 施加一接觸材料於一支撐介質的一面上,- 使一導電金屬元件結構化,- 安置該結構化金屬元件於該支撐介質上,使得該金屬元件的第一面與該支撐介質中設有該接觸材料的面係面對面地配置,- 接合該結構化金屬元件與設有接觸材料的該支撐介質,- 施加一轉印元件於該結構化金屬元件的第二面上,- 劃分該轉印元件及/或與接觸材料接合的該結構化金屬元件,以供進一步加工處理的目的用。
Description
本發明涉及用以製造特別用來提供與數個半導體元件接觸之基材配接器的方法。此外,本發明涉及用此方法製成的基材配接器,以及用於提供與半導體元件接觸的目的之方法,特別是,有該基材配接器部署於其中的功率組件。
功率電子模組的遞增要求,例如,在導電率及使用壽命方面,需要部署銅製焊線用於功率半導體之互相接觸的目的,或用於功率電子模組內的其他連接。以目前的晶片金屬化而言,主要是專門裝設的鋁塗層或鋁金屬化,其中這在提供接觸的過程中以及以後的應用會產生問題。例如,此類金屬化可能在以後的運行導致失效。
存在各種解決方案用以增加系統的使用壽命,例如,利用所謂的可撓電路板。不過,此類可撓電路板也與一種缺點有關,因為使用習知焊線製程無法做成接觸,以
及導致現有生產措施不能再用。
本發明之一目標是要提供改良方案,特別是關於製成半導體元件(特別是,功率半導體元件)的可靠性。
根據本發明,此目標與以下有關:用具有請求項1或2所述之特徵的方法實現一種方法用以製造特別用來提供與數個半導體元件之接觸的基材配接器;用具有請求項19之主旨實現該基材配接器;以及用具有請求項20或21所述之特徵的方法以本發明基材配接器實現與半導體元件接觸的方法,特別是功率組件。
附屬項具體說明用以製造基材配接器之本發明方法的有利及可取組態,亦即,用本發明基材配接器來提供與半導體元件(特別是,功率組件)接觸的目的之本發明方法。
用以製造特別用來提供與數個半導體元件之接觸的基材配接器的本發明方法包含以下步驟:- 施加一接觸材料於一支撐介質的一面上,- 使一導電金屬元件結構化,- 安置該結構化金屬元件於該支撐介質上,使得該金屬元件的第一面與該支撐介質中設有該接觸材料的面係面對面地配置,- 接合該結構化金屬元件與設有接觸材料的該支撐介質,- 施加一轉印元件於該結構化金屬元件的第二面上,
- 劃分該轉印元件及/或與接觸材料接合的該結構化金屬元件,以供進一步加工處理的目的用。
在另一方面中,用以製造特別用來提供與數個半導體元件之接觸的基材配接器的本發明方法包含下列步驟:- 施加一接觸材料於一支撐介質的一面上,- 使一導電金屬元件結構化,- 安置該結構化金屬元件於該支撐介質上,使得該金屬元件的第一面與該支撐介質中設有該接觸材料的面係面對面地配置,- 接合該結構化金屬元件與設有接觸材料的該支撐介質,- 劃分與接觸材料接合的該結構化金屬元件,以供進一步加工處理的目的用。
因此,本發明方法視需要可包含以下步驟:一轉印元件施加於該結構化金屬元件的第二面上。
該接觸材料的施加也可被指定為轉印處理(transference)。此外,該接觸材料有可能作為接觸層施加或轉印於該支撐介質的一面上。
導電金屬元件的結構化涉及在導電金屬元件中加入數個結構,其中該等結構可加入導電金屬元件的一面或多面上。進行導電金屬元件的結構化最好與待實現基材配接器的形狀有關,或與待實現接觸構件的形狀有關。例如,類似或匹配的形狀有可能以彼此有間隔地加入導電金
屬元件。
設有接觸材料的支撐介質以及該結構化導電金屬元件在下文的第一個實例中採用的形式是彼此被分開的兩個元件將會被加工或可能被加工,隨後相鄰地安置。進行該結構化金屬元件在該支撐介質上的安置藉此面對面地配置該金屬元件的第一面與該支撐介質中設有該接觸材料的該面。換言之,該金屬元件的該第一面與該支撐介質中設有該接觸材料的該面,亦即,該接觸材料與該金屬元件的第一面,面對面。在最好對於該支撐介質確切地安置該結構化金屬元件之後,該結構化金屬元件接合至設有接觸材料的該支撐介質。換言之,該支撐介質與該結構化金屬元件接合,其中該接觸材料在接合製程期間及之後與該結構化金屬元件的第一面接觸。
在形成第一中間元件之後,亦即,與該支撐介質接合的該結構化金屬元件,一轉印元件可施加於該結構化金屬元件中最好沒有提供接觸材料於其上的該第二面上。換言之,該接觸材料與該支撐介質位於該結構化金屬元件的一面上。該轉印元件位在另一面上,亦即,在與該結構化金屬元件相反的面上。
為了進一步加工,該轉印元件及/或與該接觸材料接合之該結構化金屬元件的劃分涉及個別基材配接器的描繪,亦即,提供。因此,基材配接器理論上有可能視需要包含轉印元件或沒有。
關於這點,應注意,基材配接器應瞭解為配置於
一支撐介質的個別基材配接器和多個基材配接器。因此,本發明方法涉及用以製造一個基材配接器的方法與用以製造配置於一支撐介質上之多個基材配接器的方法。
藉助於轉印元件及/或與接觸材料接合之結構化金屬元件的劃分,可製成基材配接器的形狀,或相鄰地配置於支撐介質上之基材配接器的形狀。例如,轉印元件,及/或藉由劃分一轉印元件製成的轉印元件區段,以及與接觸材料接合和視需要劃分的結構化金屬元件,形成一基材配接器,或配置於最好不會被劃分之支撐介質上的多個基材配接器。此外,可想而知,只有與接觸材料接合、被劃分及視需要有塗層的金屬元件形成一基材配接器,或配置於最好不會被劃分之支撐介質上的多個基材配接器。該支撐介質,以及位於其上的基材配接器或數個基材配接器形成一中間產物,例如,為了提供與半導體元件的接觸,這是必需的。可獨立操縱該中間產物,亦即,位於該支撐介質上的基材配接器,以及在時間及/或空間上分離的製程中可進一步加工,或在用於提供與半導體元件接觸的目的之方法中可使用它。
視需要可提供,結構化金屬元件的第一面塗有第一塗層系統,及/或結構化金屬元件的第二面塗有第二塗層系統,其中結構化金屬元件之第一面及/或第二面的塗層最好在安置該結構化金屬元件於該支撐介質上之前進行。
因此,在下文中,結構化金屬元件的名稱永遠包含以下選項:可塗層該結構化金屬元件的一或兩面,亦即,
第一面及/或第二面。
在本發明的一具體實施例形式中,該支撐介質可為薄膜,特別是有可調整黏著力的薄膜,其中該薄膜夾在一框體中,特別是一薄膜框體。此外,該薄膜有可能連續地纏繞於一線圈成形器(coil former)上。例如,在此情形下,支撐薄膜的形式可為UV薄膜。
薄膜(亦即,支撐薄膜)在支撐介質、接觸材料之間的黏著力(特別是,可調整黏著力)可小於接觸材料與結構化金屬元件之間的黏著力。如果該結構化金屬元件從該支撐介質拆下,該接觸材料仍然黏著至該經結構化及視需要有塗層的金屬元件。換言之,支撐介質與接觸材料之間的黏著最好小於接觸材料與經結構化及視需要有塗層的金屬元件之間的黏著,使得如果該經結構化及視需要有塗層的金屬元件從該支撐介質拆下,該接觸材料仍然黏著至該經結構化及視需要有塗層的金屬元件。
施加於接觸材料之一面上的支撐介質例如可採用可燒結的材料形式,或燒結材料。該接觸材料可為燒結膏及/或燒結薄膜,其中燒結材料及/或燒結膏及/或燒結薄膜,例如,可包含銀及/或銀化合物。
在本發明的另一具體實施例形式中,該接觸材料可為焊料及/或傳導黏著劑。
該接觸材料在該支撐介質之一面上的施加可用壓印法(imprinting),特別是網印法及/或模版印刷法,及/或有刮刀,及/或用噴塗法及/或噴射法執行或進行。
該接觸材料在該支撐介質之一面上的施加可在一預定結構下執行為較佳,其中該預定結構特別與金屬元件(特別是,結構化金屬元件)的結構完全匹配。該接觸材料最好在一形狀或結構下施加於該支撐介質之一面上使得它對應至該結構化金屬元件之金屬元件的形狀或結構,使得在該結構化金屬元件接合至設有接觸材料的支撐介質時,該結構化接觸材料可完全匹配地施加於該金屬元件的結構上。
該金屬元件可為一金屬箔,特別是一銅箔。
該金屬元件之第一及/或第二面以第一及/或第二塗層系統的視需要塗層,例如,可用鍍鋅法(galvanising process)執行。該塗層,亦即,第一及/或第二塗層系統,例如,可在鍍鋅框體中施加於該金屬元件的第一面及/或第二面上。
該第一塗層系統與該第二塗層系統最好為不同的金屬,特別是鎳、銀及/或金。
在本發明的另一具體實施例形式中,對於施加於支撐介質上的接觸材料,特別是,外加燒結膏及/或燒結薄膜及/或外加焊料,可提供預熱。施加於支撐介質上之接觸材料的預熱最好在安置該經結構化及視需要有塗層之金屬元件於支撐介質上之前執行。換言之,施加於支撐介質上之接觸材料在該經結構化及視需要有塗層之金屬元件與該接觸材料接合期間已經被預熱。
該經結構化及視需要有塗層之金屬元件,特別是
該金屬元件的第二面,在該接合製程期間,特別是在用加熱壓印器(heated stamp)壓合該金屬元件與該支撐介質期間,可加熱到60℃至100℃的溫度,特別是70℃至90℃,特別是80℃。
在該壓合製程期間,對立支撐物及/或對立壓印器可在該支撐介質中沒有施加接觸材料的面上操作。
施加於該經結構化及視需要有塗層之金屬元件之第二面上的上述轉印元件可採用轉印薄膜的形式,特別是有黏著劑塗層的自黏薄膜,PSA(壓敏黏著劑)黏著劑塗層為較佳。該轉印元件最好為轉印薄膜,或該轉印元件具有轉印薄膜。
在本發明方法的上下文中,該金屬元件,其係與支撐介質及/或接觸材料接合,經結構化,視需要有塗層,且視需要設有轉印元件,有可能用鋸切法及/或雷射切割法及/或壓印法及/或蝕刻法及/或水刀切割法劃分為較佳。由於該轉印元件及/或該金屬元件的劃分,可製造及提供多個基材配接器在一支撐介質上的配置。
例如,有可能只有該轉印元件被劃分。此外,可想而知,轉印元件以及與接觸材料接合的金屬元件兩者可能被劃分。
此外,有可能只劃分與接觸材料接合的金屬元件。也可能劃分支撐介質的子區域。用劃分建立相鄰堆疊之間的間隙為較佳,其中該等堆疊由一金屬元件區段與一接觸材料區段組成,且視需要包含一轉印元件區段。相鄰地配
置的個別堆疊可附著於(亦即,位於)支撐介質上,亦即,於共用支撐介質上。
在一獨立方面中,本發明涉及一種基材配接器,它用一種方法製成,亦即,使用本發明方法。該基材配接器包含至少一金屬元件區段與至少一接觸材料區段。此外,該基材配接器也有可能包含至少一轉印元件區段。這些區段視需要可位於一支撐介質上。
在另一獨立方面中,本發明涉及多個基材配接器在支撐介質上的配置,其中多個基材配接器的配置是用本發明方法製成。
本發明的另一獨立方面涉及一種用本發明基材配接器來提供與半導體元件接觸的目的之方法,特別是功率組件。本發明接觸方法包含以下步驟:- 從該支撐介質拆下一經劃分之基材配接器,其係包含與接觸材料接合的該視需要有塗層的金屬元件以及該轉印元件,- 安置該基材配接器於一半導體元件上使得該接觸材料與該半導體元件處於彼此相對的位置,亦即,面對面,- 用熱及/或施加壓力使該基材配接器附著於該半導體元件上,- 移除該轉印元件以及暴露該視需要有塗層之金屬元件的第二面,- 使用一接觸元件提供與該視需要有塗層之金屬元件的第二面接觸,特別是,焊線,特別是銅製焊線,及/或
金屬帶(bonding ribbon),及/或銅夾(copper clip)。
本發明的另一獨立方面涉及一種用本發明基材配接器來提供與半導體元件接觸的目的之方法,特別是功率組件。本發明接觸方法包含以下步驟:- 從該支撐介質拆下一經劃分之基材配接器,其係包含與接觸材料接合的該視需要有塗層之金屬元件,- 安置該基材配接器於一半導體元件上使得該接觸材料與該半導體元件面對面,- 用熱及/或施加壓力使該基材配接器附著於該半導體元件上,- 用一接觸元件提供與該視需要有塗層之金屬元件的第二面接觸,特別是,焊線,特別是銅製焊線,及/或金屬帶,及/或銅夾。
此外,本發明接觸方法可包含以下方法步驟:該基材配接器燒結及/或焊接及/或黏著至該半導體元件,及/或包含該半導體元件的一基材。
藉助於用以製造基材的本發明方法,提供經婌成含有該接觸材料的基材配接器給客戶及/或以進一步加工或至機械加工生產線。可在薄膜框體上提供該基材配接器或多個基材配接器的配置。在此一輸送形式中,它可在下一個製程或方法步驟中由薄膜框體取出以及燒結於半導體元件上,特別是於功率組件上。這對應至所謂的拾放技術。亦即,基材配接器,藉助於機器人系統,或抓取裝置,或噴嘴,亦即,抽吸設備,可由該支撐介質(例如,薄膜框體)
卸下,以及運送到適當的半導體元件。
10‧‧‧支撐介質
11‧‧‧薄膜框體
12‧‧‧支撐介質的第一面
13‧‧‧接觸材料
14‧‧‧接觸材料的結構
15‧‧‧金屬元件
16‧‧‧金屬元件的結構
17‧‧‧金屬元件的第一面
18‧‧‧支撐介質的第二面
19‧‧‧對立支撐物
20‧‧‧金屬元件的第二面
21‧‧‧壓印器
22‧‧‧轉印元件
23‧‧‧凹部
24‧‧‧分離點
25‧‧‧第一塗層系統
26‧‧‧第二塗層系統
27‧‧‧堆疊,基材配接器
28‧‧‧轉印元件區段
29‧‧‧金屬元件區段
30‧‧‧接觸材料區段
31、31'‧‧‧噴嘴
32‧‧‧半導體元件
33‧‧‧銅製焊線
d‧‧‧金屬元件的厚度
以下用具體實施例的例子且參考有其他細節的附圖進一步詳細解釋本發明。
在此圖1至圖6的個別階段及步驟圖示製造用於功率半導體模組之特別基材配接器的方法,其中該基材配接器經設計成可保護功率半導體模組免受害於機械應力,以及使得能用銅製焊線接合;圖7至圖11的個別階段或步驟圖示用以製造基材配接器之方法的另一示範具體實施例;圖12至圖14的個別階段或步驟圖示用基材配接器來提供與半導體元件接觸的目的之本發明方法;圖15圖示已裝設接觸於其中的半導體元件;以及圖16至圖21的個別階段或步驟圖示用以製造基材配接器之方法的另一示範具體實施例,以及用基材配接器來提供與半導體元件接觸的目的之方法。
以下類似的部件和操作方式類似的部件用相同的元件符號表示。
圖1至圖6的平面圖及橫截面圖圖示個別方法步驟及中間產物。
圖1圖示夾在所謂薄膜框體11上的支撐介質10。支撐介質10的形式圖示成為有可調整黏著力的薄膜。當薄
膜10夾進薄膜框體11時,必須注意薄膜,亦即,支撐介質10,有充分的機械強健性,使得在可能後續乾燥製程的情形下,位於支撐介質上的元件,例如位於其上的接觸材料13,不會變形。
接觸材料13施加於圖2之支撐介質10的一面12上。在如附圖所示的實施例中,接觸材料13的形式為燒結膏。該燒結膏最好含有銀及/或銀化合物。接觸材料13以帶有結構的方式(亦即,有結構14)施加於支撐介質10的面12上。換言之,接觸材料13施加於4個個別區段中,其中該等個別區段的形成大致為L形。最好用壓印法進行接觸材料13於支撐介質10之面12上的施加,特別是網印法及/或模版印刷法。接著,預乾燥壓印於支撐介質10之面12上的接觸材料13,亦即燒結膏。例如,以大約100℃乾燥使用銀為較佳的燒結膏約10分鐘。
圖3的平面圖圖示金屬元件15的第一面。金屬元件15的形式最好為金屬箔,特別是銅箔。導電金屬元件15經結構化。例如,可用蝕刻法及/或壓印法及/或雷射進行該結構化。換言之,在導電金屬元件15中引進一結構或多個結構16。結構16或形狀最好對應至接觸元件13的結構14。金屬元件15的結構16最好對應至隨後將會使用之基材配接器的形狀。
接觸材料13於支撐介質10之面12上的施加在預定結構14下進行,其中結構14經執行與金屬元件15的結構16完全匹配。因此,導電金屬元件15的結構16同樣
經執行成為L形,它們與接觸材料13的L形或個別結構14一樣彼此有相同的間隔。
圖4圖示用以製造基材配接器之本發明方法的另一步驟。這涉及結構化金屬元件15在支撐介質10上的安置,其中進行該安置,使得金屬元件15的第一面17,以及支撐介質10中設有接觸材料13的面12面對面地配置。在此,導電及結構化金屬元件15完全匹配地平放於塗有燒結膏的支撐薄膜上。為了不扭曲支撐介質10,亦即,支撐薄膜,對立支撐物19在沒有接觸材料13的底面(亦即,支撐介質10的第二面18)上運作。
由圖5可見,接著是結構化金屬元件15與設有接觸材料13之支撐介質10的接合。在該接合製程期間,亦即,在用加熱壓印器21施加壓力期間,加熱金屬元件15,特別是金屬元件15之第二面20,達60℃至100℃的溫度,特別是70℃至90℃,特別是80℃。用熱及/或施加壓力,將金屬元件15與支撐介質10壓合在一起,亦即,在接觸材料13位於支撐介質10上的情形下。對立支撐物19在施加壓力期間繼續在支撐介質10的第二面18上運作。
在施加壓力後,亦即,在接合結構化金屬元件15與設有接觸材料13的支撐介質10後,轉印元件22施加於結構化金屬元件15之第二面20上。轉印元件22的形式最好為轉印薄膜。特別是,轉印薄膜的形式可為有黏著劑塗層的自黏薄膜。PSA(壓敏黏著劑)黏著劑塗層為較佳。
如上述,支撐介質10也可為薄膜,亦即,支撐
薄膜。特別是,支撐介質10為有可調整黏著力的薄膜。最好調整該薄膜(亦即,支撐薄膜10)的黏著力使得支撐介質10(亦即,支撐介質10之第一面12)與接觸材料13之間的黏著力小於接觸材料13與結構化金屬元件15(亦即,結構化金屬元件15之第一面17)之間的黏著力。黏著力有此調整使得,如果結構化金屬元件15從支撐介質10拆下以及接觸材料13位於後者時,接觸材料13能夠仍然黏著結構化金屬元件15。換言之,如果拆下結構化金屬元件15,則位於金屬元件15上的接觸材料13也與它一起拆下,因為接觸材料13由於與支撐介質10有較低的黏著力而可從支撐介質10拆下,亦即,從與支撐介質10的第一面12。
圖6圖示轉印元件22的劃分,以及與接觸材料13接合的結構化金屬元件15,用於進一步加工的目的。因此,經結構化、視需要有塗層且設有轉印元件22、而且與支撐介質10及/或接觸材料13接合的金屬元件15最好用鋸切法及/或雷射切割法及/或壓印法及/或蝕刻法及/或水刀切割法劃分。由於劃分,例如,順著接觸材料13的結構14,以及金屬元件15的結構16,可由後者加工(亦即,製造)成個別的基材配接器。在劃分製程期間,支撐介質10不被劃分為較佳,或只在某些區段。因此,被劃分的基材配接器仍可黏著至支撐介質10。換言之,該劃分製程只涉及轉印元件22,以及與接觸材料13接合的金屬元件15。藉助於薄膜框體11及支撐介質10,可簡單的方式運送已被如此劃分的基材配接器。
以下的圖7至圖11涉及用以製造基材配接器的本發明方法具體實施例之另一形式。
圖7圖示首先被結構化的金屬元件15,亦即,銅箔。為此目的,金屬元件15的第一面17加入凹部23。由於有加入的凹部23,以及使金屬元件15在整體厚度d上分離的分離點24,結構16因而在金屬元件15的第一面17上產生。
根據圖8,用第一面17上的第一塗層系統25與第二面20上的第二塗層系統26進行金屬元件15之第一面17以及金屬元件15之第二面20兩者的塗層。因此,最好在金屬元件15的結構化之後進行結構化金屬元件15的視需要塗層。金屬元件15之第一面17及第二面20的塗層用鍍鋅法執行為較佳。
第一塗層系統25與第二塗層系統26最好為不同的金屬,鎳、銀及/或金為較佳。
圖9圖示接觸材料13已施加於其上的支撐介質10。接觸材料13,例如,為含有銀或銀合金的燒結膏。接觸材料13具有結構14,其中結構14類似金屬元件15的結構16。安置帶有塗層的金屬元件15於支撐介質10上,特別是於接觸材料13上。金屬元件15之第一面17,以及位於後者上的第一塗層系統25,最好配置於接觸材料13上。接著是,結構化金屬元件15與接觸材料13的接合。例如,進行該接合製程可藉助施加壓力,如在說明圖5時所述。
根據圖10,可施加轉印元件22。轉印元件22,
例如,為轉印薄膜,其中這是施加於金屬元件15之第二面20上,特別是於第二塗層系統26上。轉印元件22最好完全覆蓋帶有塗層及結構的金屬元件15。
圖11接著圖示轉印元件22的劃分以及與接觸材料13接合帶有結構及塗層的金屬元件15。如上述,進行該劃分可藉助鋸切法及/或雷射切割法及/或壓印法及/或蝕刻法及/或水刀切割法。由於該劃分製程,個別堆疊27,在各種情形下,因而是由轉印元件區段28、塗層金屬元件區段29及接觸材料區段30組成。在目前情形下,圖示支撐介質10不被分離。此外,可見,中央堆疊27,例如,是由併在一起的兩個堆疊形成;然而,這些只是經由轉印元件區段28連接。個別堆疊27為待施加於半導體元件上的基材配接器。個別堆疊27,亦即,基材配接器,可在支撐介質10上運送。
圖12圖示在基於客戶的後期製程中,中央堆疊27,亦即,基材配接器,用藉助於夾具或抽吸設備(例如,噴嘴31)的拾放技術,如何可從支撐介質10釋出。該堆疊,亦即,基材配接器27,安置於半導體元件32上,其中接觸材料13與半導體元件32面對面(參考圖13)。用熱及/或施加壓力進行基材配接器(亦即,堆疊27)於半導體元件32上的附著。
在以下步驟(參考圖14)中,移除轉印元件22,亦即,轉印元件區段28,以及暴露金屬元件15的第二面20,或第二塗層系統26。
如圖15所示,用接觸元件(亦即,銅製焊線33)提供與視需要有塗層之金屬元件15之第二面20的接觸。接著是燒結製程及/或提供常見建立及連接製程用於製造有該接觸之半導體元件32(例如,功率組件)的目的。
如下文章節所述,圖16至圖21涉及用以製造基材配接器之本發明方法具體實施例的另一形式,以及用基材配接器提供來與半導體元件接觸的目的之方法。
圖16圖示首先被結構化的金屬元件15,亦即,銅箔。為此目的,金屬元件15的第一面17加入凹部23。由於有加入的凹部23,以及使金屬元件15在整體厚度d上分離的分離點24,結構16因而在金屬元件15的第一面17上產生。
根據圖17,用第一面17上的第一塗層系統25與第二面20上的第二塗層系統26進行金屬元件15之第一面17以及金屬元件15之第二面20兩者的塗層。最好在金屬元件15的結構化之後進行結構化金屬元件15的視需要塗層。金屬元件15之第一面17及第二面20的塗層用鍍鋅法執行為較佳。
第一塗層系統25與第二塗層系統26最好為不同的金屬,鎳、銀及/或金為較佳。
圖18接觸材料13已施加於其上的支撐介質10。接觸材料13,例如,為含有銀或銀合金的燒結膏。接觸材料13具有結構14,其中結構14類似金屬元件15的結構16。安置帶有塗層的金屬元件15於支撐介質10上,特別
是於接觸材料13上。金屬元件15之第一面17,以及位於後者上的第一塗層系統25,最好配置於接觸材料13上。接著是,結構化金屬元件15與接觸材料13的接合。例如,進行該接合製程可藉助施加壓力,如在說明圖5時所述。
圖19接著圖示與接觸材料13接合帶有結構及塗層的金屬元件15的劃分。進行該劃分可藉助鋸切法及/或雷射切割法及/或壓印法及/或蝕刻法及/或水刀切割法。由於該劃分製程,個別堆疊27',在各種情形下,因而是由轉印元件區段28、塗層金屬元件區段29及接觸材料區段30組成。在目前情形下,圖示支撐介質10不被分離。個別堆疊27'為待施加於半導體元件上的基材配接器。個別堆疊27',亦即,基材配接器,可在支撐介質10上運送,例如,支撐介質10可夾在薄膜框體中。
圖20圖示在基於客戶的後期製程中,中央堆疊27',亦即,基材配接器,用藉助於夾具或抽吸設備(例如,噴嘴31)的拾放技術如何可從支撐介質10釋出。在目前情形下,該堆疊,亦即,基材配接器27',為安置於半導體元件32上的射極,其中接觸材料13與半導體元件32面對面(參考圖21)。用熱及/或施加壓力進行基材配接器(亦即,堆疊27')於半導體元件32上的附著。位於支撐介質10上為閘極的額外堆疊,亦即,基材配接器27',可個別施加於半導體元件32上。如圖21所示,這可用另一個附加抽吸設備(例如,噴嘴31')進行。在圖示於圖13的方法步驟中,可在一個步驟中進行射極及閘極的安置,因為這兩個堆疊27
經由轉印元件區段28互相連接。
提供與金屬元件15之第二面20(亦即,第二塗層系統26)的接觸可在未圖示的後續方法步驟中完成為較佳,例如,利用銅製焊線。接著是燒結製程及/或提供常見建立及連接製程用於製造有該接觸之半導體元件32(例如,功率組件)的目的。
在此時,應注意,個別或者是以任何組合方式與圖1至圖21之具體實施例形式有關的上述所有方法步驟及元件,特別是圖示於附圖的細節,都被主張對本發明而言是至關重要的。
15‧‧‧金屬元件
20‧‧‧金屬元件的第二面
27‧‧‧堆疊,基材配接器
32‧‧‧半導體元件
33‧‧‧銅製焊線
Claims (22)
- 一種用以製造基材配接器之方法,該基材配接器係特別用來提供與數個半導體元件之接觸,該方法包含下列步驟:施加一接觸材料於一支撐介質的一面上,使一導電金屬元件結構化,安置該結構化金屬元件於該支撐介質上,使得該金屬元件的一第一面與該支撐介質中設有該接觸材料的面係面對面地配置,接合該結構化金屬元件與設有接觸材料的該支撐介質,施加一轉印元件於該結構化金屬元件之該第二面上,劃分該轉印元件及/或與接觸材料接合的該結構化金屬元件,以供進一步加工處理的目的用。
- 一種用以製造基材配接器之方法,該基材配接器係特別用來提供與數個半導體元件之接觸,該方法包含下列步驟:施加一接觸材料於一支撐介質的一面上,使一導電金屬元件結構化,安置該結構化金屬元件於該支撐介質上,使得該金屬元件的一第一面與該支撐介質中設有該接觸材料的面係面對面地配置, 接合該結構化金屬元件與設有接觸材料的該支撐介質,劃分與接觸材料接合的該結構化金屬元件,以供進一步加工處理的目的用。
- 如請求項1或2所述之方法,其特徵在於,特別可在安置該結構化金屬元件於該支撐介質上的步驟之前,用一第一塗層系統塗敷該結構化金屬元件之該第一面,及/或用一第二塗層系統塗敷該結構化金屬元件之一第二面。
- 如請求項1至3中之任一項所述的方法,其特徵在於,該支撐介質為一薄膜,特別可為有可調整黏著力的薄膜,該薄膜係夾緊於一框體中或連續地纏繞於一線圈成形器上,該框體特別可為一薄膜框體,。
- 如請求項4項所述之方法,其特徵在於,該支撐介質與該接觸材料之間的黏著力係小於該接觸材料與該結構化金屬元件之間的黏著力,使得在該結構化金屬元件從該支撐介質拆下的情況下,該接觸材料仍然黏著至該結構化金屬元件。
- 如請求項1至5中之任一所述的方法,其特徵在於,該接觸材料為一燒結材料。
- 如請求項6所述之方法,其特徵在於,該接觸材料為一燒結膏及/或一燒結薄膜,且較佳地含有銀及/或銀化合物。
- 如以上所有請求項中之任一項所述的方法,其特徵在於,該接觸材料為一焊料及/或一傳導黏著劑。
- 如以上所有請求項中之任一項所述的方法,其特徵在於,施加該接觸材料於該支撐介質之一面上的步驟是用壓印法執行,可特別是網印法及/或模版印刷法,及/或有一刮刀及/或用噴塗法及/或噴射法。
- 如以上所有請求項中之任一項所述的方法,其特徵在於,施加該接觸材料於該支撐介質之一面上的步驟係在一預定結構下執行,特別是它與該金屬元件之該結構完全匹配,該金屬元件可特別是該結構化金屬元件。
- 如以上所有請求項中之任一項所述的方法,其特徵在於,該金屬元件為一金屬箔,可特別是一銅箔。
- 如請求項3至11中之任一項所述的方法,其特徵在於,該金屬元件之該第一面及/或該第二面之該塗層是用一鍍鋅法執行。
- 如請求項3至12中之任一項所述的方法,其特徵在於,該第一塗層系統與該第二塗層系統為不同的金屬,該等金屬較佳地為鎳、銀及/或金。
- 如以上所有請求項中之任一項所述的方法,可特別如請求項6至13中之任一項所述的方法,其特徵在於,預乾燥施加於該支撐介質上的該接觸材料,可特別為外加燒結膏,及/或燒結薄膜,及/或該外加焊料。
- 如以上所有請求項中之任一項所述的方法,其特徵在於,該金屬元件,可特別是該金屬元件之該第二面,在該接合製程期間,可特別是在壓合該金屬元件與該支撐介質期間,可用一加熱壓印器加熱到60℃至100℃的溫度,可特別是70℃至90℃,可特別是80℃。
- 如請求項15所述之方法,其特徵在於,在該壓合製程期間,一對立支撐物及/或一對立壓印器在該支撐介質中的一面上操作,該支撐介質中的該面較佳地為沒有接觸材料。
- 如以上所有請求項中之任一項所述的方法,特別是如請求項1或3至16中之任一項所述的方法,其特徵在於,該轉印元件為一轉印薄膜,可特別是有一黏著劑塗 層的一自黏薄膜,較佳地為一PSA(壓敏黏著劑)黏著劑塗層。
- 如以上所有請求項中之任一項所述的方法,其特徵在於,該經結構化及視需要有塗層之金屬元件,其係與該支撐介質及/或該接觸材料接合,且視需要設有該轉印元件,其較佳地用鋸切法、及/或雷射切割法、及/或壓印法、及/或蝕刻法、及/或水刀切割法來劃分。
- 一種基材配接器,其係使用如以上所有請求項中之任一項所述的方法製成。
- 一種用於提供與半導體元件接觸的目的之方法,該半導體可特別是一功率組件,該方法係藉由如請求項19所述之基材配接器,該方法係包含下列步驟:從該支撐介質拆下一經劃分之基材配接器,其係包含與接觸材料接合的該視需要有塗層之金屬元件以及該轉印元件,安置該基材配接器於一半導體元件上,使得該接觸材料與該半導體元件係面對面,藉由熱及/或施加壓力使該基材配接器附著於該半導體元件上,移除該轉印元件及暴露該視需要有塗層之金屬元件的該第二面,使用一接觸元件提供與該視需要有塗層之金屬元件之第二面的接觸,該接觸元件可特別是焊線,可特別 是銅製焊線,及/或金屬帶,及/或銅夾。
- 一種用於提供與半導體元件接觸的目的之方法,該半導體可特別是一功率組件,該方法係藉由如請求項19所述之基材配接器,該方法係包含下列步驟:從該支撐介質拆下一經劃分的基材配接器,其係包含與接觸材料接合的該視需要有塗層之金屬元件以及該轉印元件,安置該基材配接器於一半導體元件上使得該接觸材料與該半導體元件係面對面,藉由熱及/或施加壓力使該基材配接器附著於該半導體元件上,使用一接觸元件提供與該視需要有塗層之金屬元件之該第二面的接觸,該接觸元件可特別是焊線,可特別是銅製焊線,及/或金屬帶,及/或銅夾。
- 如請求項20或21所述之方法,其特徵在於,該基材配接器燒結及/或焊接及/或黏著至該半導體元件及/或包含該半導體元件的一基材。
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