CN106471873A - 嵌入迹线 - Google Patents

嵌入迹线 Download PDF

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CN106471873A
CN106471873A CN201580026644.0A CN201580026644A CN106471873A CN 106471873 A CN106471873 A CN 106471873A CN 201580026644 A CN201580026644 A CN 201580026644A CN 106471873 A CN106471873 A CN 106471873A
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laminated substrate
trace
passage
trace passage
pcb
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康斯坦丁·卡拉瓦克斯
肯尼斯·S·巴尔
史蒂夫·卡尼
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Sierra Circuits Inc
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Serra Circuit
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    • HELECTRICITY
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    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/185Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method by making a catalytic pattern by photo-imaging
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
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    • H05K2201/01Dielectrics
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    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0236Plating catalyst as filler in insulating material
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    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
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Abstract

印刷电路板包含层压基板,层压基板包含催化材料。所述催化材料在表面未被烧蚀的情况下可以抗金属电镀。金属迹线在层压基板内的迹线通道形成。所述迹线通道在催化材料表层以下延伸。

Description

嵌入迹线
背景技术
相关专利申请的交叉引用:
本申请涉及并要求2014年5月19号提交的名为《嵌入迹线》的美国专利申请第14/281,631号的利益和优先权,整体在此通过参照的方式引入。
发明内容
在典型的印刷电路板(PCB)制作工艺中,可以在印刷电路板的两侧使用覆铜箔层压板。
在印刷电路板的两侧涂覆感光抗蚀剂并将其曝光和显影以产生电路。然后使用铜化学蚀刻溶液去除电路之间的不需要的铜。然后使用化学方法去除抗蚀剂。对于多层结构,玻璃增强的未完全固化的树脂预浸料可以放置在成品芯的两侧,并在热、真空和压力下使用印刷电路板两侧的铜箔进行层压。可以使用诸如钻孔或激光等机械手段来形成孔,以形成盲孔将外层和内层互连。没有用合成树脂浸渍过的预浸料可以用合成树脂加强。
附图说明
图1显示了根据一种实施方式制成并具有嵌入迹线的印刷电路板结构的简化图。
图2显示了根据一种实施方式制作具有嵌入迹线的印刷电路板的简化流程图。
图3、图4、图5、图6、图7、图8、图9和图10显示了根据一种实施方式制作具有嵌入迹线的印刷电路板的简化流程图。
具体实施方式
在印刷电路板(PCB)的制作中,迹线在层压板表面上方0.5-2.5密耳处形成,如果PCB是双层板,则存在在预浸料层压期间或在焊料掩模施加期间空隙可能被夹在迹线之间的可能性。此外,信号完整性和导体阻抗是影响迹线之间电介质间隔的因素。当PCB迹线在层压板表面上方形成时,印刷电路板迹线上方的电介质空间将根据板的长度和宽度的不同而发生变化。这使得难以精确地控制PCB迹线的阻抗。此外,当PCB迹线在层压板表面上方形成并且迹线宽度和间隔小于1密耳时,精细迹线未能恰当地粘附到层压板表面可能导致制造产率低和可靠性问题。例如,当在层压表面上形成迹线时,由于光刻和化学铜蚀刻的限制导致的不准确性,迹线的几何结构可能由于迹线的长度不同而发生变化。迹线的不同几何结构可能导致信号传播和迹线阻抗较差的问题。
为了解决PCB迹线在层压板表面上方形成而产生的上述问题,PCB迹线被嵌入在层压基板中,使其不会在层压板表面上方延伸。如图2所示,其中PCB迹线12嵌入在层压基板10内。下一层13可以是,例如用于双层PCB板的焊料掩模或用于PCB板的预浸料压层,其包括超过两层或非玻璃增强的催化粘合剂。
PCB迹线12在具有一定深度(例如0.25到2.5密耳)的迹线通道中形成。在层压基板10的表面烧蚀迹线通道。嵌入PCB迹线12能够提供更好的电性能,因为迹线通道形成工艺可以很好地控制PCB迹线的几何形状。同样地,将PCB迹线12嵌入层压基板10中解决了当迹线非常精细时产生的粘附问题,例如当迹线厚度和迹线之间的间距小于1密耳时。嵌入PCB迹线时,它们在三个侧面被层压表面约束。
图2示出了总结用于制造具有嵌入迹线的印刷电路板的过程的简化流程图。在方框31中,所述过程从一个层压基板开始。例如,使用没有任何铜的催化基层压板。例如,催化基层压板使用包括由无机填料高岭土制成的钯催化颗粒的钯粉末。例如,通过将硅酸铝的表面处的盐钯和诸如高岭土的粘土与还原剂混合在一起来制备无机填料。或者可以使用另一种金属(如银,)的盐来代替钯的盐。
水合肼可用作还原剂以将钯盐还原成钯金属。可以将填料与浆料形式的水一起加入到混合罐中,然后向混合物中加入氯化钯(PdCI)和盐酸(HCI)溶液,随后加入水合肼。关于制造这种催化效力的更多信息,参见USPN 4,287,253。
催化粉末可以在环氧树脂井中充分地扩散。内含催化填料的环氧树脂可用来浸透玻璃布,树脂和催化剂使用常见的玻璃布涂覆设备和干燥设备。涂层的半固化树脂/玻璃布可以为印刷电路板制作层压板,这些层压板通过使用标准真空层压设备将涂层半固化树脂/玻璃布按压到一起制成。所得层状层压材料可用作印刷电路板的催化层压基板。
例如,层压基板10是厚度在2和60密耳之间的催化层压基板。例如,层压基板10由非包层催化基层压板组成,外部预浸料富含树脂,使得在真空层压之后,所得到的成品层压板具有富含树脂的表面。例如,富含树脂的预浸料可具有(但不限于)71%树脂含量的106式玻璃或具有65%树脂含量的1035式玻璃。当制备迹线通道时,使用富树脂层压板表面来确保主要除去的是树脂而不是玻璃。这可以加速迹线通道形成过程并提高所述迹线通道的质量。例如,富树脂催化层压板的表面最初用离型膜来保护,使得表面免受刮伤,因为划痕将导致镀铜并产生缺陷。当准备形成迹线通道时,从层压基板10两侧去除离型膜。
在方框32中,使用激光烧蚀打破层压基板10的表面以形成迹线通道11,如图4所示。激光烧蚀可以通过紫外线(UV)准分子激光、钇铝石榴石(YAG)激光、紫外线钇铝石榴石激光或一些其他的激光来实现,或者,通过非激光烧蚀工艺。准分子激光烧蚀能够很好地控制深度和产生良好的迹线通道分辨率。
作为使用激光烧蚀来形成迹线通道的替代方案,层压基板10的两边都可以使用抗蚀剂。抗蚀剂被曝光和显影以描绘迹线通道的位置。例如,抗蚀剂厚度要厚于迹线通道的深度。例如,迹线通道深度为0.5密耳时,抗蚀剂厚度可以为1.0密耳至1.5密耳。然后迹线通道就可以通过使用等离子刻蚀和气体组合(例如:氧气、四氟甲烷、氩等)外加适当的电力和持续时间而形成。我们期望迹线通道将以不同于抗蚀剂的速度被侵蚀。例如,抗蚀剂厚度应该大于迹线通道深度以便于当达到迹线通道深度时,还有一些剩下的抗蚀剂保护层压基板10中未暴露的表面区域。等离子刻蚀之后,可以用一个抗蚀剂剥离剂来清除剩下的抗蚀剂。
或者,实施等离子刻蚀时也可以使用其他保护性材料代替抗蚀剂来保护层压基板表面。例如,可以使用施加到层压基板10上的箔,如铜箔或铝箔来实现保护。箔的镜面可以朝着层压基板10放置,迹线通道形成后,可以剥除箔。例如,将箔应用到层压基板10之后,将抗蚀剂应用到箔上。抗蚀剂被暴露/显影以暴露迹线通道区域的箔。并蚀刻箔以暴露层压基板10中的迹线通道区域。剩下的抗蚀剂则会被清除,并对迹线通道进行等离子蚀刻。然后剥除剩下的箔,并继续加工过程。
或者,可以使用高压水切割来形成迹线通道。使用可编程的高压水切割机(如用于切割钢铁和不锈钢等硬质材料的切割机)可实施高压水切割。另一如钻孔和镂铣的机械加工工艺可用于制作迹线通道。
在方框33中,层压基板被清洗以清除迹线通道11的碎片。例如,这种清洗可以通过声波频率在40兆赫兹到160兆赫兹之间的超声波清洗来完成。通常不使用更具侵蚀性的化学清洗,此种清洗可能会导致层压基板10的表面变粗糙或受到侵蚀。如果层压基板10的表面受到侵蚀,这会导致原先位置的金属电镀不再处于形成的迹线通道内。
在方框34中,迹线12在迹线通道11中形成,如图5所示。例如,迹线12由一种金属制成,如铜。例如,要形成铜质迹线,层压基板10需被浸入快速无电镀铜镀液中。整个迹线通道11和略高于层压基板10的表面部分都被电镀。化学镀铜镀液只对烧蚀过程中暴露的催化性区域进行电镀。由于在制作层压基板10的层压过程中,铜只在层压基板10表面被烧蚀、划损或粗糙的地方催化,因此迹线通道11外的区域无镀铜。因此,铜质迹线在层压基板10表面被烧蚀的地方形成。层压基板10内经简化的迹线俯视图如图6所示。
在方框35中,例如使用精细网格砂纸(例如:420砂砾至1200砂砾)对所述层压基板10的表面进行抛光。
抛光移除了所有延伸到迹线通道以上的额外的铜。例如,可以使用MASS,Inc.生产的密抛光机。最终的抛光效果如图7所示。双层印刷电路板往往使用焊接掩模。例如,在分离和检查后进行局部镀金,印刷电路板就完成了。
在方框36中,当印刷电路板超过两层时,富树脂催化预浸料13层压在层压基板的两侧。例如,使用诸如聚氟乙烯或聚四氟乙烯离型膜。结果如图8所示。可以使用非催化材料替代富树脂催化预浸料13,如采用催化性粘着材料作为非玻璃加强催化性粘着剂的一层。
在方框37中,例如,通过使用激光器或诸如钻头的机械设备,形成盲孔和通孔。结果如图9所示,图中展示了盲孔14、盲孔15和通16。
在方框38中,在水中进行超声波清洗之后,迹线17形成。例如,迹线17由铜等金属构成。例如,迹线17通过化学镀铜形成。化学镀铜将会导致迹线在孔14、15和16内形成,正如迹线区域18、19和20所示。这会导致出现图10所示的四层电路板结构。例如,可以通过实施如焊接掩模、进行局部镀金、分离(如从一个阵列中分离)和检查等加工步骤完成印刷电路板的制作。
或者根据需要重复方框36、37和38,在方框39中添加附加层直至达到想要的层数。在方框40中,当达到想要的层数时,可以通过实施如焊接掩模、进行局部镀金、分离(如从一个阵列中分离)和检查等加工步骤完成印刷电路板的制作。
上述讨论仅揭露并描述了典型的方法和具体表现。正如本领域技术人员所理解的那样,在不脱离本发明的精神或特性的情况下,可以以其它具体形式来实施所揭露的主旨。相应地,本文的揭露意在说明而不是限制本发明保护范围,本发明保护范围以权利要求为准。

Claims (20)

1.一种形成印刷电路板的方法,其特征在于:其包含:
在层压基板中形成迹线通道,其中所述层压基板包含除了被烧蚀的催化材料的表面以外的抗金属电镀的催化材料,在被烧蚀的所述催化材料的表面下的所述迹线通道被烧蚀;
在金属熔池中浸泡所述层压基板以便金属在所述迹线通道内电镀,而不是在未被烧蚀的催化材料的表面电镀;和
抛光所述层压基板,使得所述迹线通道内的金属镀层与所述层压基板的表面齐平。
2.如权利要求1所述的方法,其特征在于:所述金属熔池为化学镀铜溶池。
3.如权利要求1所述的方法,其特征在于:所述迹线通道使用激光烧蚀形成。
4.如权利要求1所述的方法,其特征在于:所述迹线通道通过以下步骤形成:
在所述层压基板上施加抗蚀剂;
曝光和显影所述抗蚀剂以描绘所述迹线通道的位置;和,
执行等离子蚀刻以形成所述迹线通道。
5.如权利要求1所述的方法,其特征在于:所述迹线通道通过以下步骤形成:
在所述层压基板上施加箔;
在所述箔上施加抗蚀剂;
曝光和显影所述抗蚀剂以暴露描绘的所述迹线通道的位置的所述箔的部分;
蚀刻所述箔的暴露部分;和,
执行等离子蚀刻以形成所述迹线通道。
6.如权利要求1所述的方法,其特征在于:所述方法还包含:
在所述层压基板上层压富树脂催化预浸料;
形成通孔;和,
在所述富树脂催化预浸料的表面上形成附加迹线,包括在所述通孔内形成迹线。
7.如权利要求1所述的方法,其特征在于:在所述层压基板中形成迹线通道包括在所述层压基板两侧上形成迹线通道。
8.如权利要求1所述的方法,其特征在于:所述层压基板包含钯催化粒子。
9.如权利要求1所述的方法,其特征在于:所述层压基板包含在环氧树脂中充分扩散的催化粉末。
10.如权利要求1所述的方法,其特征在于:在所述层压基板中,被烧蚀的所述迹线通道的区域富含树脂。
11.如权利要求1所述的方法,其特征在于:所述迹线通道由以下方式之一形成:
高压水切割;
钻孔;
镂铣。
12.一种印刷电路板,其特征在于:其包括:
层压基板,所述层压基板包含除了被烧蚀的催化材料的表面以外的抗金属电镀的催化材料;和
在所述层压基板内形成的迹线通道内的金属迹线,所述迹线通道在被烧蚀的催化材料的表面下延伸。
13.如权利要求12所述的印刷电路板,其特征在于:所述印刷电路板还包括:
所述层压基板上的催化材料;
穿过所述催化材料的通孔;和,
包括所述通孔内的迹线在内的催化材料表面上的附加迹线。
14.如权利要求13所述的印刷电路板,其特征在于:所述催化材料由以下材料之一组成:
富树脂催化预浸料;
催化性粘合材料。
15.如权利要求12所述的印刷电路板,其特征在于:所述层压基板包含钯催化粒子。
16.如权利要求12所述的印刷电路板,其特征在于:所述层压基板包含在环氧树脂中充分扩散的催化粉末。
17.一种形成印刷电路板迹线的方法,其特征在于:其包含:
在层压基板中形成迹线通道,所述层压基板包含除了被烧蚀的所述催化材料的表面以外的抗金属电镀的催化材料,其中在被烧蚀的所述催化材料的表面下所述迹线通道被烧蚀;
实施化学镀铜液工艺以在所述迹线通道内放置铜迹线;和,
抛光所述层压基板,使得所述铜迹线与所述层压基板的表面齐平。
18.如权利要求17所述的方法,其特征在于:所述迹线通道通过以下步骤形成:
在所述层压基板上施加抗蚀剂;
曝光和显影所述抗蚀剂以描绘所述迹线通道的位置;和,
执行等离子蚀刻以形成所述迹线通道。
19.如权利要求17所述的方法,其特征在于:所述迹线通道通过以下步骤形成:在所述层压基板上施加箔;
在所述箔上施加所述抗蚀剂;
曝光和显影所述抗蚀剂以暴露所述箔描绘的所述迹线通道的位置部分;
蚀刻所述箔的暴露部分;和,
执行等离子蚀刻以形成所述迹线通道。
20.如权利要求17所述的方法,其特征在于:所述迹线通道由以下方式之一形成:
激光烧蚀;
高压水切割;
钻孔;
镂铣。
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