CN106449554A - 带有封闭空腔的芯片嵌入式封装结构及其制作方法 - Google Patents
带有封闭空腔的芯片嵌入式封装结构及其制作方法 Download PDFInfo
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- CN106449554A CN106449554A CN201611109949.0A CN201611109949A CN106449554A CN 106449554 A CN106449554 A CN 106449554A CN 201611109949 A CN201611109949 A CN 201611109949A CN 106449554 A CN106449554 A CN 106449554A
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Classifications
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (16)
Priority Applications (1)
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CN201611109949.0A CN106449554B (zh) | 2016-12-06 | 2016-12-06 | 带有封闭空腔的芯片嵌入式封装结构及其制作方法 |
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CN201611109949.0A CN106449554B (zh) | 2016-12-06 | 2016-12-06 | 带有封闭空腔的芯片嵌入式封装结构及其制作方法 |
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CN106449554B CN106449554B (zh) | 2019-12-17 |
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Cited By (26)
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CN107910274A (zh) * | 2017-12-18 | 2018-04-13 | 苏州晶方半导体科技股份有限公司 | 一种指纹芯片的封装方法以及封装结构 |
CN107958882A (zh) * | 2017-12-20 | 2018-04-24 | 苏州晶方半导体科技股份有限公司 | 芯片的封装结构及其制作方法 |
CN108091616A (zh) * | 2017-12-15 | 2018-05-29 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装方法以及封装结构 |
CN108257921A (zh) * | 2018-03-27 | 2018-07-06 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108269781A (zh) * | 2018-03-27 | 2018-07-10 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108470724A (zh) * | 2018-03-27 | 2018-08-31 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108711569A (zh) * | 2018-08-10 | 2018-10-26 | 付伟 | 带有容纳滤波器芯片腔室的多芯片封装结构及其制作方法 |
CN108766956A (zh) * | 2018-08-10 | 2018-11-06 | 付伟 | 具有多腔室的多芯片封装结构及其制作方法 |
CN108766955A (zh) * | 2018-08-10 | 2018-11-06 | 付伟 | Rf开关芯片电极外设的多腔室封装结构及其制作方法 |
CN108807350A (zh) * | 2018-08-10 | 2018-11-13 | 付伟 | 放大器芯片电极外设的多腔室封装结构及其制作方法 |
CN108831875A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 滤波器芯片内嵌且电极外设的封装结构及其制作方法 |
CN108831876A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 滤波器芯片内嵌且具有孔洞的封装结构及其制作方法 |
CN108831881A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 带有腔室的上下堆叠式多芯片封装结构及其制作方法 |
CN109065531A (zh) * | 2018-08-10 | 2018-12-21 | 付伟 | 外设式多芯片封装结构及其制作方法 |
CN109087912A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 带有腔室的多芯片封装结构及其制作方法 |
CN109087909A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 具有金属柱的多腔室封装结构及其制作方法 |
CN109087911A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 带有容纳功能芯片腔室的多芯片封装结构及其制作方法 |
CN109103173A (zh) * | 2018-08-10 | 2018-12-28 | 付伟 | 滤波器芯片内嵌且引脚上置的封装结构及其制作方法 |
CN109257874A (zh) * | 2018-11-16 | 2019-01-22 | 深圳市和美精艺科技有限公司 | 一种在pcb板制作过程中芯片埋入的方法及其结构 |
CN109494163A (zh) * | 2018-11-20 | 2019-03-19 | 苏州晶方半导体科技股份有限公司 | 芯片的封装结构以及封装方法 |
WO2020001583A1 (zh) * | 2018-06-29 | 2020-01-02 | 宁波舜宇光电信息有限公司 | 线路板组件、感光组件、摄像模组及其制作方法 |
CN110650593A (zh) * | 2019-10-21 | 2020-01-03 | 深圳市和美精艺科技有限公司 | 一种制作空腔传感器的生产方法 |
US10575397B1 (en) | 2019-04-30 | 2020-02-25 | Unimicron Technology Corp. | Circuit carrier structure, manufacturing method thereof and chip package structure |
WO2020248466A1 (zh) * | 2019-06-14 | 2020-12-17 | 苏州敏芯微电子技术股份有限公司 | 背孔引线式压力传感器及其制备方法 |
JP2022002296A (ja) * | 2020-06-19 | 2022-01-06 | ズハイ アクセス セミコンダクター シーオー., エルティーディーZhuhai Access Semiconductor Co., Ltd | 空気共振キャビティを有する埋め込みパッケージ構造の製造方法 |
CN115632034A (zh) * | 2022-12-20 | 2023-01-20 | 珠海妙存科技有限公司 | eMMC模组封装结构及其制作方法 |
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Cited By (31)
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CN108091616A (zh) * | 2017-12-15 | 2018-05-29 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装方法以及封装结构 |
CN107910274A (zh) * | 2017-12-18 | 2018-04-13 | 苏州晶方半导体科技股份有限公司 | 一种指纹芯片的封装方法以及封装结构 |
CN107958882A (zh) * | 2017-12-20 | 2018-04-24 | 苏州晶方半导体科技股份有限公司 | 芯片的封装结构及其制作方法 |
CN108257921A (zh) * | 2018-03-27 | 2018-07-06 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108269781A (zh) * | 2018-03-27 | 2018-07-10 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
CN108470724A (zh) * | 2018-03-27 | 2018-08-31 | 苏州晶方半导体科技股份有限公司 | 一种芯片的封装结构以及封装方法 |
WO2020001583A1 (zh) * | 2018-06-29 | 2020-01-02 | 宁波舜宇光电信息有限公司 | 线路板组件、感光组件、摄像模组及其制作方法 |
CN109087912A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 带有腔室的多芯片封装结构及其制作方法 |
CN108766956A (zh) * | 2018-08-10 | 2018-11-06 | 付伟 | 具有多腔室的多芯片封装结构及其制作方法 |
CN108807350A (zh) * | 2018-08-10 | 2018-11-13 | 付伟 | 放大器芯片电极外设的多腔室封装结构及其制作方法 |
CN108831875A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 滤波器芯片内嵌且电极外设的封装结构及其制作方法 |
CN108831876A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 滤波器芯片内嵌且具有孔洞的封装结构及其制作方法 |
CN108831881A (zh) * | 2018-08-10 | 2018-11-16 | 付伟 | 带有腔室的上下堆叠式多芯片封装结构及其制作方法 |
CN109065531A (zh) * | 2018-08-10 | 2018-12-21 | 付伟 | 外设式多芯片封装结构及其制作方法 |
CN108831875B (zh) * | 2018-08-10 | 2024-03-05 | 浙江熔城半导体有限公司 | 滤波器芯片内嵌且电极外设的封装结构及其制作方法 |
CN109087909A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 具有金属柱的多腔室封装结构及其制作方法 |
CN109087911A (zh) * | 2018-08-10 | 2018-12-25 | 付伟 | 带有容纳功能芯片腔室的多芯片封装结构及其制作方法 |
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