WO2020001583A1 - 线路板组件、感光组件、摄像模组及其制作方法 - Google Patents

线路板组件、感光组件、摄像模组及其制作方法 Download PDF

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Publication number
WO2020001583A1
WO2020001583A1 PCT/CN2019/093532 CN2019093532W WO2020001583A1 WO 2020001583 A1 WO2020001583 A1 WO 2020001583A1 CN 2019093532 W CN2019093532 W CN 2019093532W WO 2020001583 A1 WO2020001583 A1 WO 2020001583A1
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Prior art keywords
photosensitive
circuit board
electrodes
chip
electrode
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PCT/CN2019/093532
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English (en)
French (fr)
Inventor
王明珠
黄桢
田中武彦
陈振宇
郭楠
赵波杰
Original Assignee
宁波舜宇光电信息有限公司
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Priority claimed from CN201810998040.8A external-priority patent/CN110661939B/zh
Application filed by 宁波舜宇光电信息有限公司 filed Critical 宁波舜宇光电信息有限公司
Publication of WO2020001583A1 publication Critical patent/WO2020001583A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the present application relates to the field of optical technology, and in particular, the present application relates to a circuit board component, a photosensitive component, a camera module, and a manufacturing method thereof.
  • the camera module usually includes an optical lens component and a photosensitive component.
  • the photosensitive component generally includes a circuit board and a photosensitive chip 103 mounted on the circuit board.
  • the photosensitive chip 103 is usually connected to the circuit layer through a "gold wire” (ie, wire bonding or wire bonding) process or a flip chip (ie, flip chip) process.
  • the flip chip process As a series of problems brought about by gold wires. For example, in the flip chip process, since the chip is directly attached to the bottom side of the circuit board, and then the chip and the circuit board are connected by a gold ball, the conduction length of the circuit board and the photosensitive chip is greatly shortened in this process. Reduced delay and effectively improved electrical performance.
  • the Flip Chip process has high requirements for continuity accuracy and flatness, and it is necessary to use a ceramic substrate with high structural strength and not easy to bend as a circuit board (ie, a circuit board), which is very expensive.
  • this process solution requires that the pad size and pad density of the circuit board be consistent or substantially the same as the pad size and pad density of the photosensitive chip.
  • the minimum size of the pads of the circuit board is limited, and the gold ball bump line width is large, such as about 100um.
  • the number of pads that can be arranged on the photosensitive chip is reduced, or increasing the number of pads will increase the size of the photosensitive chip, which is not conducive to reducing the size of the camera module.
  • the higher the number of pixels of the photosensitive chip the larger the amount of image data that needs to be output, and more I / O ports are required to output data.
  • the smaller number of pads results in fewer I / O ports for output data. Therefore, the existing flip chip process is not conducive to increasing the number of pixels of the photosensitive chip.
  • the present application aims to provide a solution capable of overcoming at least one drawback of the prior art.
  • a photosensitive component including: a photosensitive chip having a photosensitive region and a non-photosensitive region surrounding the photosensitive region, wherein the non-photosensitive region is provided with a plurality of chip electrodes; a circuit board, It has a through hole corresponding to the photosensitive region, and the lower surface of the circuit board has a plurality of first electrodes; and a redistribution layer (the redistribution layer here and related wiring processes, including but not limited to existing semiconductors) RDL process, wiring board additive wiring process, or other higher-precision wiring processes, etc.), is formed on the lower surface of the circuit board, and the lower surface of the rewiring layer has a plurality of second electrodes, the plurality of second electrodes Each of the first electrodes is electrically connected to a corresponding second electrode through a rewiring trace, respectively; and the photosensitive chip is attached to a lower surface of the rewiring layer, and the plurality of second electrodes
  • the second electrode is closer to the through hole than the first electrode.
  • the area of the second electrode is smaller than the area of the first electrode.
  • the density of the plurality of second electrodes is higher than that of the plurality of first electrodes.
  • the circuit board is a rigid-flex board
  • the rigid-flex board includes a rigid board and a flexible board
  • the through holes are located on the rigid board
  • the plurality of first electrodes are located on a lower surface of the rigid board.
  • the width of the traces of the rewiring layer is smaller than the width of the traces of the circuit board.
  • the traces of the rewiring layer are directly formed on a surface of the circuit board.
  • the process temperature for forming the insulating layer is lower than the critical temperature at which the circuit board is warped.
  • the lower surface of the circuit board has a groove, and the photosensitive chip is located in the groove.
  • the photosensitive component further includes a metal sheet attached to the circuit board and covering the groove.
  • a gap is left between the metal sheet and the photosensitive chip.
  • the lower surface of the circuit board is a surface after the planarization treatment.
  • the second electrode is a metal pillar.
  • the lower surface of the metal pillar has a conductive attachment material.
  • a circuit board assembly including: a circuit board having a through hole corresponding to the photosensitive region, a lower surface of the circuit board having a plurality of first electrodes; and A wiring layer is formed on a lower surface of the circuit board, and a lower surface of the rewiring layer has a plurality of second electrodes, and each of the plurality of first electrodes is respectively rewired with the corresponding second electrode through rewiring.
  • the electrodes are electrically connected; and the photosensitive chip is attached to a lower surface of the rewiring layer, and the size and layout of the plurality of second electrodes are suitable for attaching the photosensitive chip based on a flip-chip process such that the plurality of The two electrodes are in one-to-one correspondence with a plurality of chip electrodes of the photosensitive chip and are turned on.
  • the second electrode is closer to the through hole than the first electrode.
  • the area of the second electrode is smaller than the area of the first electrode.
  • the density of the plurality of second electrodes is higher than that of the plurality of first electrodes.
  • a camera module including: the aforementioned photosensitive component; and an optical lens mounted on the photosensitive component.
  • a method for manufacturing a photosensitive component comprising: forming a rewiring layer on a lower surface of a circuit board to form a circuit board assembly, wherein the lower surface of the circuit board has a plurality of first electrodes, A lower surface of the rewiring layer has a plurality of second electrodes, each of the plurality of first electrodes is electrically connected to a corresponding second electrode through rewiring, respectively; and a photosensitive chip is attached to the The circuit board assembly, wherein the plurality of second electrodes are in one-to-one correspondence with the plurality of chip electrodes and are electrically connected.
  • the step of forming a rewiring layer on the lower surface of the wiring board includes: flattening the lower surface of the wiring board; and forming the rewiring layer on the lower surface of the wiring board after the planarization process.
  • the step of forming a redistribution layer on the lower surface of the circuit board includes: directly fabricating a redistribution wiring layer on the lower surface of the circuit board, and the routing of the redistribution wiring layer moves the first electrode away from the A first end of the light-through hole of the circuit board is connected to a second end near the light-through hole; and the second electrode is formed at a position of the second end of the rewiring wiring layer.
  • the step of forming a rewiring layer on the lower surface of the circuit board further includes: covering the protective layer after the second electrode is fabricated.
  • the step of forming a rewiring layer on the lower surface of the circuit board includes: forming an insulating layer on the lower surface of the circuit board, wherein the process temperature for forming the insulating layer is lower than the critical temperature at which the circuit board is warped; A layer of a redistribution routing layer is formed on the surface of the layer, and the routing of the redistribution routing layer connects the first electrode from a first end far from the through-hole of the circuit board to a second near the through-hole. And the second electrode is formed at a position of the second end of the rewiring wiring layer.
  • the circuit board is a soft-hard board, and before performing the step of forming a re-wiring layer on the lower surface of the circuit board, the soft-hard board is first produced.
  • the circuit board has a through hole corresponding to the photosensitive area; before performing the step of forming a rewiring layer on the lower surface of the circuit board, the through hole is filled so that the lower surface of the circuit board and the filler Forming a complete plane on the lower surface; and removing the filler to expose the through hole before performing the step of attaching a photosensitive chip to the circuit board assembly.
  • the filler is a photoresist.
  • the present application can realize the connection of the circuit board pads / circuits with larger line widths to the light-sensitive chips with smaller contacts, and realize the high-density packaging of the light-sensitive chips of the camera module.
  • This application can realize that the circuit board pads relatively close to the outside of the light window are conducted to the chip pads closer to the light window.
  • the present application can realize that the camera module uses a conventional printed circuit board to implement a flip-chip process to achieve high I / O number packaging.
  • FIG. 1 is a schematic cross-sectional view of a photosensitive component according to an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a photosensitive component including a metal plate in another embodiment of the present application.
  • FIG. 6 shows a cross-sectional view of a redistribution layer 102 in the prior art
  • FIG. 7 shows a cross-sectional view of a redistribution layer 102 in which a polymide layer is omitted
  • FIG. 8 shows a schematic diagram of a redistribution circuit 1021 and a circuit board circuit 1016 in an embodiment of the present application
  • FIG. 9 shows a redistribution layer 102 according to another embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • FIG. 11 shows a schematic diagram of a slope formed by a photoresist layer near an edge of a through hole
  • FIG. 17 shows a manufacturing process of a photosensitive component in another embodiment
  • FIG. 18 shows a camera module in an embodiment of the present application
  • FIG. 19 is a cross-sectional view of a photosensitive member according to another embodiment of the present application.
  • FIG. 20 is a cross-sectional view of a photosensitive member according to another embodiment of the present application.
  • the expressions of the first, second, etc. are only used to distinguish one feature from another feature, and do not indicate any limitation on the feature. Therefore, without departing from the teachings of this application, the first subject discussed below may also be referred to as the second subject.
  • FIG. 1 is a schematic cross-sectional view of a photosensitive component according to an embodiment of the present application.
  • the photosensitive assembly includes a photosensitive chip 103, a circuit board 101, and a rewiring layer 102.
  • the photosensitive chip 103 has a photosensitive region 1031 and a non-photosensitive region 1032 surrounding the photosensitive region 1031.
  • the non-photosensitive region 1032 is provided with a plurality of chip electrodes 1033.
  • the plurality of chip electrodes 1033 (or may be referred to as chip pads) may surround the photosensitive region 1031.
  • the circuit board 101 in this embodiment may be a rigid-soft board.
  • the rigid-flex board includes a rigid-board region 1011 and a flexible-board region 1012.
  • the hard-board region 1011 has a through hole 1013 in the center.
  • the hard board region can be understood as a region where the whole of the rigid-flex board is rendered rigid (inflexible at normal temperature), and the soft board region can be understood as the whole of the rigid-flex board as Flexible (i.e., bendable) areas.
  • the rigid board region may be a region that is rigid as a whole formed by laminating a plurality of rigid boards and a flexible board, and does not necessarily consist of only a rigid board.
  • the lower surface of the hard board region 1011 has a plurality of first electrodes 1014 (or may be referred to as first pads).
  • a redistribution layer 102 is formed on the lower surface of the hard board 1011.
  • the lower surface of the redistribution layer 102 has a plurality of second electrodes 1022 (or may be referred to as second pads).
  • Each of the plurality of first electrodes 1014 Each is electrically connected to the corresponding second electrode 1022 through a redistribution circuit 1021 (ie, a redistribution wiring); and the photosensitive chip 103 is attached to the lower surface of the redistribution layer 102, and Each of the second electrodes 1022 is in contact with and electrically connected to the plurality of chip electrodes 1033 in a one-to-one correspondence.
  • the through-hole 1013 may be a light-through hole, and a position and a size of the through-hole are adapted to the photosensitive region 1031 of the photosensitive chip 103.
  • the area of the first electrode 1014 may be larger than the area of the second electrode 1022.
  • the area of the second electrode 1022 matches the area of the chip electrode 1033 (for example, is equal or substantially equal).
  • the first electrode 1014 is located outside the second electrode 1022 (that is, the second electrode 1022 is closer to the light-passing hole than the first electrode 1014).
  • the electrodes may be all metal electrodes.
  • the pad size range of the rigid-flex board is 60-80 ⁇ m, and the pad size of the rewiring layer can be 20-50 ⁇ m. Therefore, in the above embodiment, by forming the redistribution layer 102 on the flexible and rigid bonded board 101 and implementing fan-in packaging, the flexible and rigid bonded board assembly composed of the flexible and rigid bonded board 101 and the rerouted layer 102 can have a small area.
  • a soft-hard board is a flexible circuit board (flexible board) and a rigid circuit board (hard board). After pressing and other processes, they are combined according to relevant process requirements to form an FPC and PCB circuit board. At present, the manufacturing process of flexible and rigid bonded boards is relatively mature, and it has a large cost advantage compared to other processes such as ceramic substrates.
  • connection belt of the photosensitive component of the above embodiment is made by using a manufacturing process of a rigid-flexible board, which can avoid attaching the connection belt after attaching the photosensitive chip through a process that requires high temperature hot pressing such as ACF.
  • the connecting tape can electrically connect the hard board area to the connector so as to be electrically connected to the main board of a terminal device (such as a mobile phone).
  • the flexible board of the rigid-flex board can be directly used as the connection belt of the photosensitive component.
  • the flexible board region extends to the rigid board region through the side of the rigid board region.
  • the connecting strip connects the hard board through a hard board surface (usually an edge region of the hard board surface).
  • the rigid-flexible board 101 in the embodiment shown in FIG. 1 may be replaced by a rigid board (such as a PCB board).
  • Fan-in packaging is realized by forming the rewiring layer 102 on the PCB board, so that the circuit board assembly composed of the PCB board and the rewiring layer 102 can have a small area and densely arranged metal electrodes, so that the electrodes of the soft-hard combined board assembly It can contact and conduct one-to-one correspondence with the densely arranged chip electrodes 1033, thereby avoiding various defects brought by the existing wire bonding process. At the same time, it also helps to increase the number of pixels of the light-sensitive component of the filp chip process solution.
  • the attachment point (which may be a solder joint) of the photosensitive chip 103 and the circuit board assembly in the flip-chip process , Compression points, or other types of attachment points) are closer to the photosensitive area 1031.
  • the chip pad 1033 of the photosensitive chip 103 can be located closer to the photosensitive region 1031, which helps reduce the total area of the photosensitive chip 103 (the total area here refers to the total area including the photosensitive region 1031 and the non-photosensitive region 1032 ). Therefore, the circuit board assembly of this embodiment helps to reduce the total area of the photosensitive chip 103, and further contributes to the miniaturization and development of the camera module.
  • Fig. 2 shows a schematic cross-sectional view of a photosensitive member in another embodiment of the present application.
  • the second electrode 1022 may be implemented as a metal pillar, for example, a copper pillar 1022a.
  • a plurality of photoresist layers are spin-coated on a PCB, and then exposed, developed, and copper-plated to form multiple pillars.
  • a copper pillar 1022a corresponding to the chip electrode 1033. After the photoresist is spin-coated on the surface of the soft-hard board, by controlling the speed and time of spin coating, the upper surface of the photoresist layer can be ensured to have a high flatness, thereby ensuring the upper end surface of each copper pillar 1022a.
  • the upper end faces of the copper pillars are on the same surface, so the chip electrode 1033 of the photosensitive chip 103 can contact the upper end faces of the copper pillars at the same time, thereby solving part of the chip electrodes 1033 caused by the warpage of the PCB board Problems with electrical connection.
  • the copper pillar and the chip electrode 1033 may be electrically connected by a suitable process such as ultrasonic welding, and the conduction manner thereof is not limited in this application.
  • FIG. 3 shows a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • a conductive attachment material 1022b such as nickel, palladium, gold, solder paste, or conductive silver paste may be further attached to the upper surface of the copper pillar 1022a, and the chip electrode 1033 and the copper pillar may pass through the attached conductive attachment material 1022b. Continuity is achieved while also facilitating attachment (such as welding or crimping) between the electrodes.
  • FIG. 4 is a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • the hard board region has a recess 1015 suitable for receiving the redistribution layer 102 and the photosensitive chip 103, thereby reducing the height dimension of the photosensitive component and protecting the photosensitive chip 103.
  • the size of the groove 1015 may be slightly larger than the size of the photosensitive chip 103. On the one hand, it facilitates the installation of the photosensitive chip 103, and on the other hand, it provides space for the rewiring layer 102 to run.
  • the groove 1015 is formed in the hard board region, correspondingly, the routing space of the hard board region will be reduced, so a part of the lines originally formed on the hard board region can be transferred to It is formed in the redistribution layer 102, thereby alleviating the problem of tight wiring after the groove 1015 is formed in the hard board region.
  • FIG. 5 is a schematic cross-sectional view of a photosensitive component including a metal plate in another embodiment of the present application.
  • the photosensitive component may further include a metal plate 104 such as a steel plate, and the metal plate 104 is attached to the bottom of the hard board region 101 having the groove 1015 to isolate the photosensitive chip 103 from the external environment. Prevent the photosensitive chip 103 from being damaged by external force.
  • a gap is kept between the metal plate 104 and the photosensitive chip 103, so as to prevent collision between the metal plate 104 and the photosensitive chip 103, which may cause damage to the photosensitive chip 103 or electrical connection failure.
  • the gap can be filled with air, glue, molding, insulation, and other materials to better protect the chip.
  • FIG. 6 shows a cross-sectional view of a redistribution layer 102 in the prior art.
  • the rewiring layer 102 includes a circuit layer and an insulating layer 1023 covering the circuit layer.
  • polymide is generally used as the material of the insulating layer, and the insulating layer 1023 is cured after being baked at a high temperature.
  • the rewiring layer 102 is formed on the lower surface of the circuit board 101.
  • the circuit board 101 is generally manufactured based on a lamination process, and is easily deformed (such as warped) under high-temperature baking. This may cause the rewiring layer 102 attached to the circuit board 101 to warp. Performing the wiring process on the warped surface will cause the reliability of the redistribution layer 102 to decrease, which is not conducive to improving the yield.
  • a redistribution layer 102 is further provided in which a polymide layer is omitted.
  • FIG. 7 shows a cross-sectional view of a redistribution layer 102 in which a polymide layer is omitted.
  • the first layer of the redistribution circuit that is, the redistribution trace
  • One end is connected to the first electrode 1014 (ie, the first pad) of the hard board region 101, so that the circuit 1016 of the hard board region 101 and the rewiring circuit 1021 are conducted.
  • the wiring width of the redistribution circuit 1021 of the redistribution layer 102 is significantly smaller than that of the circuit board 101. That is, under the current process conditions, the circuit accuracy on the circuit board 101 is such that the minimum value of the trace width of the circuit board 101 is 60-80 ⁇ m (that is, the highest-precision trace width is 60-80 ⁇ m).
  • the PCB board's highest precision trace width can reach 60 ⁇ m, while the rigidity of the flexible board can be lower than that of the PCB board, and its highest precision trace width is about 75 ⁇ m.
  • the width of the trace formed by the rewiring technology can be controlled within 20 ⁇ m, for example, 10 to 20 ⁇ m. Further, FIG.
  • the rewiring circuit 1021 is further formed with a plurality of second pads 1022, and each of the second pads 1022 corresponds to the chip pads 1033 of the non-photosensitive region 1032 of the photosensitive chip 103, so that So that the two can be fixed and connected by means of inverted bonding.
  • the size of the first pad 1014 of the hard board region 101 is larger than the size of the second pad 1022 of the redistribution circuit 1021 formed by the redistribution layer 102, and the second pad 1022 is exposed to the redistribution layer The exterior of 102 for attachment to a die pad (eg, soldering or crimping).
  • a die pad eg, soldering or crimping
  • FIG. 9 shows a redistribution layer 102 according to another embodiment of the present application.
  • a protection layer is provided above the redistribution circuit 1021.
  • the protection layer 1029 can protect the rewiring circuit 1021, and the protection layer 1029 can prevent the circuits in the rewiring circuit 1021 from interfering with each other and causing a short circuit;
  • the protective layer 1029 is supported by a material that can be cured by a process such as low temperature or ultraviolet irradiation to prevent warpage caused by high temperature curing.
  • the pads on the hard board or the hard board area include, but are not limited to, copper pillars, gold balls, and the like.
  • the size of the pad of the circuit board 101 can be reduced to a size consistent with the routing of the circuit 1016 of the circuit board, that is, the first end of the rewiring circuit 1021 is directly connected to the circuit board.
  • the circuit 1016 is bonded and conducted (that is, the pad of the hard board can be transformed into a part of the hard board circuit trace). It can be understood that, in the prior art, the pad size of the hard board is too large, so that the size of the hard board cannot be reduced. However, in this embodiment, the pad is eliminated, and the first end of the rewiring circuit 1021 can be directly connected to the circuit 1016 of the hard board. Under the condition that the rewiring circuit 1021 and the circuit 1016 of the hard board are connected, it is also possible. The size of the circuit board 101 is reduced.
  • the performance of the hard board or the hard board region can be further improved so that it can withstand higher temperature baking without warping, thereby avoiding adhesion to it.
  • the rewiring layer 102 does not warp.
  • the baking temperature of the insulating layer can also be lowered.
  • the insulating layer can be made of a material that can be cured at a lower temperature instead of the traditional polymide. In this way, the hard board will not warp during the curing process.
  • FIG. 10 shows a schematic cross-sectional view of a photosensitive component in another embodiment of the present application.
  • the upper image in FIG. 10 is a state of the soft-hard combined plate 101 in an original state.
  • the CTE values of the dielectric layers have a large difference, so they are prone to bend after lamination and baking. Therefore, the flatness of the surface of the soft-hard bonded board 1011a is low, which is not convenient for the subsequent re-wiring process.
  • the surface of the flexible and rigid bonding board 101 (referring to the surface for attaching the re-wiring layer 102) is subjected to a planarization treatment, such as grinding, hot pressing, heavy pressing baking, etc.
  • the surface 1011a of the soft-hard bonded board has a high flatness, and then subsequent processes such as subsequent rewiring are performed.
  • FIG. 11 shows a schematic diagram of the photoresist layer forming a slope near the edge of the through hole. Since the circuit board 101 in this application has a through hole 1013, after the photoresist is spin-coated, the photoresist layer 1021a may form a slope 1021b as shown in FIG. 11 at the through hole 1013.
  • the chip electrode 1033 is usually located on the peripheral side of the photosensitive area 1031 and is very close to the photosensitive area 1031 to reduce the chip size.
  • the copper pillar 1022a formed on the rewiring layer 102 will also be located near the through hole 1013. Corresponds to the chip electrode 1033.
  • the copper pillar 1022a may be formed on the slope 1021b of the photoresist layer 1021a. As shown in the cross-sectional view in FIG. 11, since the copper pillar 1022a is formed by plating copper into the through hole 1013 of the photoresist layer 1021a, the copper material may overflow from the inclined surface, resulting in unevenness of the upper surface of the copper pillar 1022a, or Electrical connection with other copper pillars 1022a.
  • an embodiment of the present application proposes a manufacturing process of a photosensitive component, which can avoid the problems caused by the aforementioned unevenness of the photoresist layer 1021a.
  • 12 to 16 illustrate a manufacturing process of a photosensitive component according to an embodiment of the present application.
  • a filler material 101 b such as a photoresist
  • the layers are laminated together to form the circuit board 101 (or a rigid-flexible board).
  • the through-holes 1013 of the circuit board 101 formed at this time are filled with the multilayer photoresist 101b.
  • the circuit board 101 is filled. Without the through hole 1013, the surface of the circuit board 101 is a flat and complete surface at this time, and then the photoresist is spin-coated on the circuit board 101, and the situation of the slope 1021b in FIG. 11 will no longer occur. As a result, the top surface of the copper pillars 1022a is flat and the top surfaces of the copper pillars 1022a are flush with each other. It should be noted that when manufacturing a rigid-flex board, the flexible board 101c and the rigid board 101a can be combined by a lamination process, and a rigid board formed by laminating a plurality of rigid boards and a flexible board as a whole constitutes a rigid board.
  • a region consisting of only a flexible board forms a flexible board region.
  • a redistribution layer 102 is formed on the circuit board 101, and the copper pillar 1022 a is further formed on the redistribution layer 102.
  • all photoresist (including the photoresist in the through hole and A photoresist layer corresponding to the light-through hole in the redistribution layer 102) forms a through-hole 1013 corresponding to the photosensitive chip 103.
  • a conductive attachment material 1022 b such as nickel, palladium, gold, solder paste, or conductive silver paste may be further attached to the upper surface of the copper pillar 1022 a.
  • a photosensitive chip 103 is attached to a lower surface of the circuit board 101, that is, a surface having a rewiring layer 102, so that the photosensitive chip 103 and the copper pillar 1022 a are electrically connected, thereby forming the photosensitive chip 103.
  • Photosensitive components are attached to a lower surface of the circuit board 101, that is, a surface having a rewiring layer 102, so that the photosensitive chip 103 and the copper pillar 1022 a are electrically connected, thereby forming the photosensitive chip 103.
  • FIG. 17 shows a manufacturing process of a photosensitive component in another embodiment.
  • the circuit board 101 having the through hole 1013 may be filled, for example, the through hole 1013 is filled.
  • Filling the photoresist material 101c, so that the circuit board 101 has a flat surface, and then performing a rewiring process and a copper implantation process on the circuit board having the flat surface can also prevent the photoresist layer from appearing a slope 1021b. Case.
  • the photoresist material 101c at the through hole 1013 is removed, and the through hole 1013 is exposed again to provide a clear aperture for the photosensitive chip 103. Further, the photosensitive chip 103 and copper The pillar 1022a is turned on to form the photosensitive member.
  • FIG. 18 shows a camera module according to an embodiment of the present application.
  • the camera module includes an optical lens 200 mounted on the photosensitive component 100.
  • the light collected by the optical lens 200 can Along the through hole 1013, the photosensitive member 100 is contacted, and an imaging reaction is performed on the photosensitive member 100.
  • the type of the optical lens 200 can be adjusted according to the needs of the camera module.
  • the optical lens can be implemented as an integrated optical lens, a split optical lens, a naked lens, or an optical lens including a lens barrel. Wait, this is not limited by this application.
  • FIG. 19 is a cross-sectional view of a photosensitive member according to another embodiment of the present application.
  • the circuits in the circuit board may be replaced by the circuits in the redistribution layer 102, that is, all of the circuit boards may be formed by a redistribution process. Circuit, thereby providing a thinner and lighter, high-performance camera module.
  • FIG. 20 is a cross-sectional view of a photosensitive member according to another embodiment of the present application.
  • the photosensitive component includes a photosensitive chip 103, a molding part 109, a redistribution layer 102, and a circuit board 101.
  • the lower surface of the circuit board 101 has a plurality of first electrodes 1014.
  • the photosensitive chip 103 has a photosensitive region 1031 and a non-photosensitive region 1032 surrounding the photosensitive region 1031.
  • a chip electrode 1033 is disposed in the non-photosensitive region 1032.
  • the molding portion 109 is formed around the photosensitive chip 103, and the upper surface of the molding portion 109 is flush with the upper surface of the photosensitive chip 103 to form an overall flat surface.
  • the rewiring layer 102 is formed on the flat surface.
  • the upper surface of the rewiring layer 102 has a plurality of second electrodes 1022 corresponding to the plurality of first electrodes 1014, and each of the second electrodes 1022 through the circuit layer of the rewiring layer 102 is in communication with the corresponding chip electrode 1033.
  • the photosensitive component includes a photosensitive chip and a circuit board.
  • the circuit board has a through hole corresponding to the photosensitive area of the photosensitive chip.
  • the optical axis of the photosensitive chip overlaps or deviates from the physical centerline of the through hole. Smaller.
  • the distance between the first pad on the lower surface of the circuit board and the through hole is relatively long.
  • chip upside-down assembly in order to attach the chip pads to the first pads of the circuit board in a one-to-one correspondence, the chip pads have to be located far from the through holes. This will increase the area of the photosensitive chip, which is not conducive to miniaturization of the camera module.
  • the attachment and conduction of the photosensitive chip 103 and the circuit board 101 are achieved through other processes without increasing the distance between the chip pad 1033 and the through hole 1013.
  • the photosensitive component includes a photosensitive chip component 105, a circuit board 101, and a rewiring layer 102.
  • the photosensitive chip component 105 includes a photosensitive chip 103 and an expansion layer 109 extending on both sides of the photosensitive chip 103.
  • the photosensitive chip 103 has a photosensitive region 1031 and a non-photosensitive region 1032 surrounding the photosensitive region 1031.
  • the non-photosensitive region 1032 is provided with a plurality of chip electrodes 1033.
  • the extension layer 109 extends from the non-photosensitive region 1032 to the peripheral side, so that the length and width dimensions of the photosensitive chip 103 component are expanded relative to the size of the photosensitive chip 103.
  • the extension layer 109 is formed by, for example, but not limited to, a photolithography process, a molding process, and the like.
  • the redistribution layer 102 is formed on an upper surface of the photosensitive chip assembly 105, that is, the redistribution layer 102 is disposed on a non-photosensitive region 1032 of the photosensitive chip 103 of the photosensitive chip assembly 105 and The upper surface of the extension layer 109, wherein the upper surface of the redistribution layer 102 is attached to the lower surface of the circuit board 101.
  • the lower surface of the circuit board 101 has a plurality of first pads 1014.
  • the lower surface of the redistribution layer 102 has a plurality of second pads 1022. Each of them is electrically connected to the corresponding second pad 1022 through a redistribution wiring 1021.
  • the redistribution wiring 1021 has a plurality of first ends and a plurality of second ends, and the plurality of first ends are located at The upper surface of the redistribution layer 102 and the first pads 1014 respectively attached to the lower surface of the circuit board 101.
  • the second ends are located on the lower surface of the redistribution layer 102 and connected to the second pads. 1022.
  • the second pads 1022 are in one-to-one correspondence with the plurality of chip electrodes 1033 and are electrically connected, so that the photosensitive chip 103 is electrically connected to the redistribution layer 102 through the second pads 1022, and The redistribution layer 102 is electrically connected to the first pad 1014 of the circuit board 101, so that the photosensitive element 103 and the circuit board 101 are electrically connected.
  • the size (or area) of the first pad 1014 is larger than the size of the second pad 1022, and preferably, the size of the second pad 1022 is close to the size of the second pad 1022.
  • Chip electrode 1033 size is larger than the size of the second pad 1022, and preferably, the size of the second pad 1022 is close to the size of the second pad 1022.
  • the first pad 1014 is projected (orthographically projected) on the upper surface of the photosensitive chip 103 component along the optical axis direction of the photosensitive chip 103 (or perpendicular to the component direction of the photosensitive chip 103 component),
  • the first pad 1014 is projected outside the second pad 1022, or is located on the extension layer 109.
  • an expansion layer 109 is preferably formed on the peripheral side of the photosensitive chip 103 to obtain the photosensitive chip module 105, and the rewiring is provided on the photosensitive chip module 105.
  • Layer 102, secondly, the photosensitive chip component 105 and the semi-finished product of the redistribution layer 102 manufactured and attached together are attached to the lower surface of the circuit board 101, wherein the second pad 1022 of the redistribution layer 102 corresponds to The photosensitive electrode connected to the photosensitive chip 103, the upper surface of the rewiring layer 102 is correspondingly attached to the lower surface of the circuit board 101, and the second pad 1022 is connected to the first wiring layer through the rewiring layer.
  • a pad 1014 is turned on, so that the photosensitive chip 103 can be connected to the circuit board 101. It is worth mentioning that, when forming the expansion layer 109, the photosensitive chip 103 may be performed separately; or at least one of the photosensitive chips 103 may be implemented by imposition, thereby improving process efficiency.
  • the photosensitive chip assembly 105 includes a photosensitive element 103 and an expansion layer 109.
  • the expansion layer 109 is integrally extended to the photosensitive element, that is, during the processing of the photosensitive chip 103, the non-photosensitive area 1032 of the photosensitive chip 103 can be appropriately expanded, and the expansion layer 109 is formed. Therefore, the process of manufacturing the extension layer 109 can be omitted.
  • the circuit board can also be implemented as a molded circuit board with embedded circuits.
  • the molded circuit board is made by copper implantation, molding, grinding and other processes.
  • the molded circuit board has High structural strength, flatness, and smaller line width, such as 30 ⁇ m, its higher flatness is suitable for the subsequent re-wiring process, copper implantation process.
  • a series of electronic components of the camera module such as resistors and capacitors, can be embedded in the molded circuit board, thereby playing the role of electromagnetic shielding and protecting electronic components. The length and width of the camera module are smaller.
  • the area of the second electrode is smaller than the area of the corresponding first electrode, but the application is not limited thereto.
  • the second electrode may be made into an elongated shape. At this time, the area of the second electrode may be greater than or equal to the area of the corresponding first electrode.
  • This solution can increase the number of attachment points (such as soldering points or pressing points) per unit width while ensuring the contact area between the chip electrode and the second electrode.
  • the chip electrode has a long shape and is arranged along an edge of the photosensitive region, and a short side of the chip electrode is parallel to the photosensitive region and is located on a side of the chip electrode. Side.
  • the second electrode is elongated, and the short side of the second electrode is parallel to the side of the photosensitive region on the side of the second electrode.
  • the circuit board for each side of the photosensitive region, has a plurality of rows of first electrodes corresponding to the sides, and the plurality of rows of first electrodes are connected to the rewiring layer to A single row of second electrodes, the single row of second electrodes being attached to and conducting with a single row of chip electrodes corresponding to the photosensitive chip.
  • the circuit board may have a plurality of rows of first electrodes corresponding to the sides, and the plurality of rows of first electrodes are connected to the rewiring layer to A single row of second electrodes, the single row of second electrodes being attached to and conducting with a single row of chip electrodes corresponding to the photosensitive chip.
  • photoresist refers to materials that do not require high temperature processing.
  • the photoresist curing process includes, but is not limited to, processes with low thermal effects such as light, moisture, pressure, radiation, and crystallization.

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Abstract

本申请提供了一种感光组件，包括：感光芯片，其设置有多个芯片电极；线路板，其具有与所述感光区域对应的通孔，所述线路板的下表面具有多个第一电极；以及再布线层，形成于所述线路板的下表面，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线走线与对应的所述第二电极电连接；以及，所述感光芯片附接于所述再布线层的下表面，并且所述多个第二电极分别与所述多个芯片电极一一对应地接触并导通。本申请还提供了相应的感光组件制作方法，以及相应的线路板组件和摄像模组。本申请可以实现将线宽较大的线路板焊盘/线路导通至更小触点的感光芯片，实现摄像模组感光芯片的高密度封装。

Description

线路板组件、感光组件、摄像模组及其制作方法
相关申请的交叉引用
本申请要求于2018年6月29日递交于中国国家知识产权局(CNIPA)的、申请号为201810717540.X、发明名称为“线路板组件、感光组件、摄像模组及其制作方法”的中国发明专利申请以及于2018年8月29日递交于CNIPA的、申请号为201810998040.8、发明名称为“线路板组件、感光组件、摄像模组及感光组件制作方法”的中国发明专利申请的优先权和权益，这两项申请通过引用整体并入本文。
技术领域
本申请涉及光学技术领域，具体地说，本申请涉及线路板组件、感光组件、摄像模组及其制作方法。
背景技术
随着智能手机及其他电子设备的飞速发展，由于手机屏幕越来越趋向于全面屏化、轻薄化，因此对摄像模组的小型化需求越来越强烈。
摄像模组通常包括光学镜头组件和感光组件。其中感光组件通常包括线路板和安装于线路板的感光芯片103。在现有的摄像模组中，感光芯片103通常是通过“打金线”(即wire bond或wire bonding)工艺或倒贴芯片(即flip chip)工艺实现与电路层的导通。
传统印刷电路板，受限于电流要求、线路板材质导致的线路发热，以及印刷电路板制程能力等因素，导致常见的印刷电路板线宽线距在70μm左右，极限工艺能力下可达到30μm，但成本非常高。与之对应的，受限于传统线路板的线宽线距，芯片导通时也会顾及线路板的因素，焊盘间距无法再进一步减小，而其与芯片不断小型化的发展趋势相背离。另外，由于芯片的焊盘越来越密集，间距也在逐渐逼近极限，在wire bond工艺下，在这种金线十分密集的情况下，容易发生金 线间干涉，从而导致电路故障。另一方面，在整个制造流程中，wire bond工艺之后还将进行一系列的例如模塑、镜座等步骤，都将对金线连接的可靠性造成影响。再者，金线具有一定的弧高，因此在模组中为了避让金线通常要增加一段额外的高度，因此，金线的存在可能阻碍模组的小型化发展。
如今，部分厂商采用flip chip工艺来解决金线带来的一系列问题。例如flip chip工艺中，由于其是将芯片直接贴附于电路板底侧，而后芯片与电路板之间通过金球实现导通，这种工艺下线路板与感光芯片导通的长度大大缩短，减小了延迟，有效地提高了电性能。另一方面，Flip Chip工艺对于导通精度和平整度要求高，需要采用具有高结构强度不易弯曲的陶瓷基板来做线路板(即电路板)，而其价格十分昂贵。此外，这种工艺方案要求线路板的焊盘尺寸及焊盘密集度与感光芯片的焊盘尺寸和焊盘密集度一致或基本一致。通常来说，由于工艺限制，线路板的焊盘的最小尺寸是受限的，同时金球凸点线宽较大，比如100um左右。为了适应flip chip工艺，感光芯片焊盘的尺寸难以进一步缩小，以使其与线路板的焊盘尺寸适配。这样感光芯片上能够布置的焊盘数量就减少了，或者增加焊盘数量会导致感光芯片尺寸增大，不利于摄像模组的尺寸减小。这是由于感光芯片的像素越高，所需要输出的图像数据量就越大，也就需要更多的I/O端口来输出数据。而较少的焊盘数目导致输出数据的I/O端口减少。因此，现有的flip chip工艺不利于感光芯片像素数目的提高。
发明内容
本申请旨在提供一种能够克服现有技术的至少一个缺陷的解决方案。
根据本申请的一个方面，提供了一种感光组件，包括：感光芯片，其具有感光区域和围绕在感光区域周围的非感光区域，其中所述非感光区域设置有多个芯片电极；线路板，其具有与所述感光区域对应的通孔，所述线路板的下表面具有多个第一电极；以及再布线层(此处的再布线层和相关布线工艺，包括但不限于现有的半导体RDL工艺、 线路板加成法布线工艺或其他更高精度的布线工艺等)，形成于所述线路板的下表面，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线走线与对应的所述第二电极电连接；以及，所述感光芯片附接于所述再布线层的下表面，并且所述多个第二电极分别与所述多个芯片电极一一对应地接触并导通。
其中，所述第二电极比所述第一电极靠近所述通孔。
其中，所述第二电极的面积小于所述第一电极的面积。
其中，所述多个第二电极的密集度高于所述多个第一电极。
其中，所述线路板是软硬结合板，所述软硬结合板包括硬板和软板，所述通孔位于所述硬板，所述多个第一电极位于所述硬板下表面。
其中，所述再布线层的走线的宽度小于所述线路板的走线的宽度。
其中，所述再布线层的走线直接形成于所述线路板的表面。
其中，所述再布线层的走线与所述线路板的表面之间具有绝缘层，且形成所述绝缘层的工艺温度低于所述线路板发生翘曲的临界温度。
其中，所述线路板的下表面具有凹槽，所述感光芯片位于所述凹槽内。
其中，所述感光组件还包括金属片，所述金属片附接于所述线路板并盖住所述凹槽。
其中，所述金属片与所述感光芯片之间留有间隙。
其中，所述线路板的下表面为平坦化处理后的表面。
其中，所述第二电极为金属柱。
其中，所述金属柱的下表面具有导电附接材料。
根据本申请的另一方面，还提供了一种线路板组件，包括：线路板，其具有与所述感光区域对应的通孔，所述线路板的下表面具有多个第一电极；以及再布线层，形成于所述线路板的下表面，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线与对应的所述第二电极电连接；以及，所述感光芯片附接于所述再布线层的下表面，并且所述多个第二电极的尺寸和布局适于基于倒贴工艺附接感光芯片，使得所述多个第二电极分别与所述感光芯片的多个芯片电极一一对应地接触并导通。
其中，所述第二电极比所述第一电极靠近所述通孔。
其中，所述第二电极的面积小于所述第一电极的面积。
其中，所述多个第二电极的密集度高于所述多个第一电极。
根据本申请的另一方面，还提供了一种摄像模组，包括：前述的感光组件；以及安装于所述感光组件的光学镜头。
根据本申请的另一方面，还提供了一种感光组件制作方法，包括：在线路板的下表面形成再布线层构成线路板组件，其中所述线路板的下表面具有多个第一电极，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线与对应的所述第二电极电连接；以及将感光芯片附接于所述线路板组件，其中所述多个第二电极分别与所述多个芯片电极一一对应地接触并导通。
其中，在线路板的下表面形成再布线层的步骤包括：对线路板下表面进行平坦化处理；以及在平坦化处理后的线路板下表面上形成所述再布线层。
其中，在线路板的下表面形成再布线层的步骤包括：在线路板的下表面直接制作再布线走线层，所述再布线走线层的走线将所述第一电极从远离所述线路板的通光孔的第一端连接至靠近所述通光孔的第二端；以及在再布线走线层的所述第二端的位置上制作所述第二电极。
其中，在线路板的下表面形成再布线层的步骤还包括：在制作所述第二电极后覆盖保护层。
其中，在线路板的下表面形成再布线层的步骤包括：在线路板的下表面形成绝缘层，其中形成所述绝缘层的工艺温度低于所述线路板发生翘曲的临界温度；在绝缘层表面形成再布线走线层，所述再布线走线层的走线将所述第一电极从远离所述线路板的通光孔的第一端连接至靠近所述通光孔的第二端；以及在再布线走线层的所述第二端的位置上制作所述第二电极。
其中，所述线路板为软硬结合板，执行所述在线路板的下表面形成再布线层的步骤前，先制作所述软硬结合板。
其中，所述线路板具有与感光区域对应的通孔；执行所述在线路板的下表面形成再布线层的步骤前，将所述通孔填充使得所述线路板的下表面和填充物的下表面形成一完整的平面；以及执行将感光芯片附接于所述线路板组件的步骤前，去除所述填充物以露出所述通孔。
其中，将所述通孔填充的步骤中，所述填充物为光刻胶。
与现有技术相比，本申请具有下列至少一个技术效果：
1、本申请可以实现将线宽较大的线路板焊盘/线路导通至更小触点的感光芯片，实现摄像模组感光芯片的高密度封装。
2、本申请可以实现相对靠近光窗外侧的线路板焊盘导通至更靠近光窗的芯片焊盘。
3、本申请可以实现摄像模组采用常规印刷线路板实现倒贴芯片工艺，以实现高I/O数的封装。
附图说明
在参考附图中示出示例性实施例。本文中公开的实施例和附图应被视作说明性的，而非限制性的。
图1示出了本申请一个实施例的感光组件的剖面示意图；
图2示出了本申请另一个实施例中的感光组件的剖面示意图；
图3示出了本申请另一个实施例中的感光组件的剖面示意图；
图4示出了本申请另一个实施例中的感光组件的剖面示意图；
图5示出了本申请另一个实施例中的包含金属板的感光组件的剖面示意图；
图6示出了现有技术中一种再布线层102的剖视图；
图7示出了一种省略polymide层的再布线层102的剖视图；
图8示出了本申请一个实施例中的再布线电路1021和线路板电路1016的示意图；
图9示出了本申请另一个实施例的再布线层102；
图10示出了本申请另一个实施例中的感光组件的剖面示意图；
图11示出了光刻胶层在靠近通孔的边缘处形成斜坡的示意图；
图12～16示出了本申请一实施例的感光组件制作流程；
图17示出了另一实施例中的感光组件制作流程；
图18示出了本申请一个实施例中的一摄像模组；
图19示出了本申请另一实施例的感光组件的剖视图；
图20示出了本申请另一实施例的感光组件的剖视图。
具体实施方式
为了更好地理解本申请，将参考附图对本申请的各个方面做出更详细的说明。应理解，这些详细说明只是对本申请的示例性实施方式的描述，而非以任何方式限制本申请的范围。在说明书全文中，相同的附图标号指代相同的元件。表述“和/或”包括相关联的所列项目中的一个或多个的任何和全部组合。
应注意，在本说明书中，第一、第二等的表述仅用于将一个特征与另一个特征区分开来，而不表示对特征的任何限制。因此，在不背离本申请的教导的情况下，下文中讨论的第一主体也可被称作第二主体。
在附图中，为了便于说明，已稍微夸大了物体的厚度、尺寸和形状。附图仅为示例而并非严格按比例绘制。
还应理解的是，用语“包括”、“包括有”、“具有”、“包含”和/或“包含有”，当在本说明书中使用时表示存在所陈述的特征、整体、步骤、操作、元件和/或部件，但不排除存在或附加有一个或多个其它特征、整体、步骤、操作、元件、部件和/或它们的组合。此外，当诸如“...中的至少一个”的表述出现在所列特征的列表之后时，修饰整个所列特征，而不是修饰列表中的单独元件。此外，当描述本申请的实施方式时，使用“可以”表示“本申请的一个或多个实施方式”。并且，用语“示例性的”旨在指代示例或举例说明。
如在本文中使用的，用语“基本上”、“大约”以及类似的用语用作表近似的用语，而不用作表程度的用语，并且旨在说明将由本领域普通技术人员认识到的、测量值或计算值中的固有偏差。
除非另外限定，否则本文中使用的所有用语(包括技术用语和科学用语)均具有与本申请所属领域普通技术人员的通常理解相同的含义。还应理解的是，用语(例如在常用词典中定义的用语)应被解释为具有与它们在相关技术的上下文中的含义一致的含义，并且将不被以理想化或过度正式意义解释，除非本文中明确如此限定。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例 中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
图1示出了本申请一个实施例的感光组件的剖面示意图。参考图1，该感光组件包括：感光芯片103、线路板101和再布线层102。其中感光芯片103具有感光区域1031和围绕在感光区域1031周围的非感光区域1032，所述非感光区域1032设置有多个芯片电极1033。这多个芯片电极1033(或者可以称为芯片焊盘)可以围绕在感光区域1031周围。本实施例中的线路板101可以是软硬结合板。软硬结合板包括硬板区1011和软板区1012，所述硬板区1011中央具有通孔1013。本文中，所述硬板区可以理解为软硬结合板中的整体上呈现为刚性(在常温下不可弯曲)的区域，所述软板区可以理解为软硬结合板中的整体上呈现为柔性(即可弯曲)的区域。需注意，硬板区可以是由多个硬板和软板层压而形成的整体上呈现刚性的区域，并不一定仅由硬板构成。进一步地，硬板区1011的下表面具有多个第一电极1014(或者可以称为第一焊盘)。再布线层102形成于硬板1011下表面，所述再布线层102的下表面具有多个第二电极1022(或者可以称为第二焊盘)，所述多个第一电极1014中的每个分别通过再布线电路1021(即再布线走线)与对应的所述第二电极1022电连接；并且，所述感光芯片103附接于所述再布线层102的下表面，并且所述多个第二电极1022分别与所述多个芯片电极1033一一对应地接触并导通。所述通孔1013可以是通光孔，该通光孔的位置和尺寸与所述感光芯片103的感光区域1031适配。第一电极1014的面积可以大于第二电极1022的面积。第二电极1022的面积与芯片电极1033的面积适配(例如相等或基本相等)。本实施例中，第一电极1014位于第二电极1022的外侧(即第二电极1022比第一电极1014靠近所述通光孔)。本实施例中，电极可以均为金属电极。
在现有技术中，软硬结合板的焊盘尺寸范围为60～80μm，而再布线层的焊盘尺可以做到20～50μm。因此，上述实施例中，通过在软硬结合板101上形成再布线层102并实现扇入式封装，使得软硬结合板 101和再布线层102共同构成的软硬结合板组件可以具有小面积且密集排布的金属电极(即焊盘)，从而使得软硬结合板组件的电极(即焊盘)可以与密集排布的芯片电极1033一一对应地接触并导通，从而有助于提高filp chip工艺方案的感光组件的像素数目，同时避免了现有wire bond工艺所带来的各种缺陷。另一方面，软硬结合板是一种柔性线路板(软板)与硬性线路板(硬板)，经过压合等工序，按相关工艺要求组合在一起，形成的具有FPC特性与PCB特性的线路板。目前，软硬结合板的制作工艺已经比较成熟，相对于陶瓷基板等其它工艺的线路板具有较大的成本优势。再者，上述实施例的感光组件的连接带利用软硬结合板的制作工艺制成，可以避免附接感光芯片后再通过ACF等需要高温热压的工艺来贴附连接带。连接带可以将硬板区电连接至连接器，以便与终端设备(例如手机)的主板电连接。软硬结合板的软板可直接作为感光组件的连接带，在软硬结合板中，软板区是通过硬板区的侧面延伸至所述硬板区的。而基于ACF工艺，则连接带是通过硬板表面(通常是硬板表面的边缘区域)来连接所述硬板。
需要注意，图1所示的实施例的软硬结合板101可以用硬板(例如PCB板)代替。通过在PCB板上形成再布线层102实现扇入封装，使得PCB板和再布线层102共同构成的线路板组件可以具有小面积且密集排布的金属电极，从而使得软硬结合板组件的电极可以与密集排布的芯片电极1033一一对应地接触并导通，进而避免了现有wire bond工艺所带来的各种缺陷。同时，还有助于提高filp chip工艺方案的感光组件的像素数目。进一步地，由于线路板组件的所述第二焊盘1022比所述第一焊盘1014靠近通光孔1013，使得在倒贴工艺中，感光芯片103与线路板组件的附接点(可以是焊接点、压合点或其它类型的附接点)更加靠近感光区域1031。这样感光芯片103的芯片焊盘1033可以设置在更加靠近感光区域1031的位置，有助于减小感光芯片103的总面积(这里的总面积是指包含感光区域1031和非感光区域1032的总面积)。因此本实施例的线路板组件有助于缩小感光芯片103的总面积，进而有助于摄像模组的小型化发展。
进一步地，图2示出了本申请另一个实施例中的感光组件的剖面 示意图。在本实施例中，所述第二电极1022可被实施为金属柱，例如铜柱1022a，通过在PCB板上旋涂一层光刻胶层，而后通过曝光、显影、植铜，形成多个与芯片电极1033相对应的铜柱1022a。由于光刻胶旋涂于软硬结合板上表面后，通过控制旋涂的转速、时间等，可以保证光刻胶层上表面具有较高的平整度，进而保证了各铜柱1022a的上端面齐平，也就是说各铜柱的上端面位于同一表面，因此感光芯片103的芯片电极1033得以同时接触各铜柱的上端面，从而解决了由于PCB板易发生翘曲导致的部分芯片电极1033无法实现电连接的问题。进一步地，所述铜柱与所述芯片电极1033间可利用超声焊等合适的工艺实现电连接，其导通方式本申请不做限制。
进一步地，图3示出了本申请另一个实施例中的感光组件的剖面示意图。所述铜柱1022a的上表面可以进一步附着镍、钯、金、锡膏或导电银胶等导电附接材料1022b，所述芯片电极1033与所述铜柱间通过该附着的导电附接材料1022b实现导通，同时还便于电极之间的附接(例如焊接或压合)。
图4示出了本申请另一个实施例中的感光组件的剖面示意图。所述硬板区具有一适于容纳再布线层102和感光芯片103的凹槽1015，从而利于降低感光组件的高度尺寸，并对感光芯片103起到保护作用。所述凹槽1015的尺寸可以略大于感光芯片103的尺寸，一方面，便于感光芯片103的安装，另一方面，为再布线层102走线提供空间。在本实施例中，由于所述硬板区形成凹槽1015，对应地，所述硬板区的走线空间将被缩减，因此，部分原形成于所述硬板区上的线路可以转至形成于再布线层102中，从而缓解了硬板区形成凹槽1015后走线紧张的问题。
图5示出了本申请另一个实施例中的包含金属板的感光组件的剖面示意图。如图5所示，所述感光组件可进一步包括一金属板104，如钢板，所述金属板104贴附于具有凹槽1015的硬板区101的底部，使感光芯片103隔离于外界环境，防止感光芯片103受到外力冲击而导致损坏。所述金属板104与感光芯片103间保持预留间隙，从而防止金属板104与感光芯片103间发生碰撞而导致感光芯片103损坏或 电连接失效。间隙可以被空气、胶水、模塑、绝缘层等材料填充，以更好地保护芯片。
进一步地，图6示出了现有技术中一种再布线层102的剖视图。再布线层102包括电路层及包覆电路层的绝缘层1023。在现有技术中，通常采用polymide作为绝缘层材料，该绝缘层1023经过高温烘烤后固化。然而，本申请中，再布线层102形成在线路板101的下表面，线路板101通常是基于层压工艺制作的，在高温烘烤下易发生变形(例如翘曲)。这样可能会导致附着于线路板101上的再布线层102也出现翘曲的问题。在带有翘曲的面上进行布线工艺将导致再布线层102的可靠性下降，不利于提升良率。
基于前述分析，根据本申请的一个实施例，还进一步地提供了一种省略polymide层的再布线层102。图7示出了一种省略polymide层的再布线层102的剖视图。如图7所示，在本申请的一实施例中，所述再布线层102的电路层形成于所述硬板区101上后，将所述再布线电路(即再布线走线)的第一端连通于硬板区101的第一电极1014(即第一焊盘)，从而使得硬板区101的电路1016和所述再布线电路1021导通。值得注意的是，如图7所示，所述再布线层102的所述再布线电路1021的走线宽度明显小于所述线路板101的走线宽度。即，在现有技术的工艺条件下，线路板101上的电路精度使得所述线路板101的走线宽度的最小值为60～80μm(即最高精度的走线宽度为60～80μm)。例如PCB板最高精度的走线宽度可以达到60μm，而软硬结合板走线精度可能低于PCB板，其最高精度的走线宽度大约为75μm。而采取再布线技术形成的走线宽度可控制于20μm以内，例如10到20μm。进一步地，图8示出了本申请一个实施例中的再布线电路1021和线路板电路1016的示意图。参考图7和图8，所述再布线电路1021还形成有多个第二焊盘1022，每个第二焊盘1022对应于感光芯片103的非感光区1032的芯片焊盘1033对应分布，从而使得两者之间可以通过倒贴方式固定和导通。值得一提的是，硬板区101的第一焊盘1014尺寸大于再布线层102的所述再布线电路1021的形成的第二焊盘1022尺寸，且第二焊盘1022暴露在再布线层102的外部，以便与芯 片焊盘附接(例如焊接或压合)。
进一步地，图9示出了本申请另一个实施例的再布线层102，参考图9，本实施例中，形成所述再布线电路1021之后，于所述再布线电路1021上方设置一保护层1029，所述保护层1029可保护所述再布线电路1021，且所述保护层1029可预防所述再布线电路1021中各个电路不会互相干扰而发生短路；值得注意的是，本实施例中该保护层1029采取低温或紫外线照射等工艺即可固化的材料支撑，预防高温固化带来的翘曲问题。在本实施例中，硬板或硬板区的焊盘包括但不限于铜柱、金球等。
在本申请一变形实施例中，线路板101的焊盘的尺寸可以缩小到与线路板的电路1016的走线一致的尺寸，即所述再布线电路1021的第一端直接与所述线路板的电路1016贴合导通(也就是说，硬板的焊盘可以蜕化为硬板电路走线的一部分)。可以理解的是，现有技术中，硬板的焊盘尺寸偏大，从而导致硬板尺寸无法得以减小。而本实施例取消焊盘，所述再布线电路1021的第一端直接可连接于硬板的电路1016，在确保所述再布线电路1021和硬板的电路1016导通的情况下，还可以使得线路板101尺寸减小。
值得一提的是，在本申请另一实施例中，可以采取进一步提高硬板或硬板区的性能，使其可承受更高温度的烘烤而不出现翘曲，从而避免附着于其上的再布线层102不出现翘曲。本申请的另一实施例中，还可以将绝缘层烘烤温度降低，例如绝缘层材料可以采用较低温即可固化的材料代替传统的polymide。这样在固化过程中，硬板不会发生翘曲。
进一步地，图10示出了本申请另一个实施例中的感光组件的剖面示意图，图10中的上图中为原始状态的软硬结合板101的状态，软硬结合板101由于金属层与介电层的CTE值相差较大，因此经过层压、烘烤后容易发生弯曲，因此所述软硬结合板表面1011a平整度较低，从而不便于后续的再布线工艺的进行。在本实施例中，在执行再布线工艺前，先对软硬结合板101的表面(指用于附着再布线层102的表 面)进行平坦化处理，如研磨、热压、重压烘烤等处理，使所述软硬结合板表面1011a具有较高的平整度，而后再进行后续的再布线等后续工艺。
进一步地，图11示出了光刻胶层在靠近通孔的边缘处形成斜坡的示意图。由于本申请中的线路板101具有通孔1013，因此在旋涂光刻胶后，光刻胶层1021a在通孔1013处可能会形成如图11中所示的斜坡1021b，而由于感光芯片103的芯片电极1033通常设置在感光区域1031周侧，并十分靠近感光区域1031，以减小芯片尺寸，对应地，形成于再布线层102的铜柱1022a也将位于靠近通孔1013处的位置，以与芯片电极1033相对应。因此，铜柱1022a将可能形成在光刻胶层1021a的斜坡1021b位置。如图11中的剖视图所示，由于铜柱1022a是通过向光刻胶层1021a的通孔1013中镀铜形成的，因此铜材料将可能自斜面溢出，导致铜柱1022a上表面不平整，或与其他铜柱1022a电连接等问题。
为了解决该问题，本申请的一个实施例提出了一种感光组件制作流程，该流程可以避免前述光刻胶层1021a不平坦而导致的问题。图12～16示出了本申请一实施例的感光组件制作流程。在本实施例中，如图12所示，在所述线路板的制造过程中，预先在其每一层材料101a中，都于通孔1013位置处施加填充材料101b，例如光刻胶，再将各层层压在一起形成所述线路板101(或软硬结合板)，此时形成的所述线路板101的通孔1013被多层光刻胶101b填充，此时所述线路板101不具有所述通孔1013，因此此时所述线路板101的表面为一平整、完整的表面，再于线路板101上旋涂光刻胶即不会再出现图11中的斜坡1021b情况，从而保证了铜柱1022a上表面的平整，及各铜柱1022a上表面相齐平。需注意，在制造软硬结合板时，可以将软板101c与硬板101a通过层压工艺结合在一起，由多个硬板和软板层压而形成的整体上呈现刚性的区域构成硬板区，仅由软板构成的区域形成软板区。进一步地，如图13、图14所示，于所述线路板101上形成再布线层102，再于所述再布线层102上形成所述铜柱1022a。进一步地，如图15所示，在再布线层102及再布线层102上的铜柱1022a形成后，再 去除通孔1013处的全部的光刻胶(包括通光孔中的光刻胶及再布线层102中与通光孔对应的的光刻胶层)，形成与感光芯片103对应的通孔1013。可选地，如图15所示，所述铜柱1022a的上表面可以进一步附着镍、钯、金、锡膏或导电银胶等导电附接材料1022b。
进一步地，如图16所示，将感光芯片103附接于所述线路板101的下表面，也就是具有再布线层102的表面，使感光芯片103与铜柱1022a导通，从而形成所述感光组件。
进一步地，图17示出了另一实施例中的感光组件制作流程。如图17所示，在本申请的另一实施例中，也可于所述线路板101层压成形后，再对具有通孔1013的所述线路板101进行填充，例如向通孔1013中填充光刻胶材料101c，使所述线路板101具有一平整的表面，而后再于具有平整表面的线路板上进行再布线工艺、植铜工艺，同样也可以达到防止光刻胶层出现斜坡1021b的情况。再布线层102、铜柱1022a成形后，去除通孔1013处的光刻胶材料101c，重新显露出所述通孔1013，为感光芯片103提供通光孔径，进一步地，将感光芯片103与铜柱1022a导通，形成所述感光组件。
进一步地，图18示出了本申请一个实施例中的一摄像模组，所述摄像模组包括一安装于所述感光组件100上的光学镜头200，所述光学镜头200所采集的光线能够沿着所述通孔1013抵至所述感光组件100，并于所述感光组件100进行成像反应。所述光学镜头200的类型可根据所述摄像模组的需求作相应调整，例如所述光学镜头可被实施为一体式光学镜头、分体式光学镜头、裸镜头、或包括一镜筒的光学镜头等，对此，并不为本申请所局限。
图19示出了本申请另一实施例的感光组件的剖视图。如图19所示，在本申请的另一实施例中，所述线路板中的线路可被再布线层102中的线路代替，也就是说，可通过再布线工艺形成所述线路板的所有线路，从而提供一更加轻薄化，高性能化摄像模组。
图20示出了本申请另一实施例的感光组件的剖视图。该实施例中，感光组件包括感光芯片103、模塑部109、再布线层102以及线路板101。其中线路板101的下表面具有多个第一电极1014。感光芯片 103具有感光区域1031和围绕所述感光区域1031的非感光区域1032芯片电极1033设置在非感光区域1032。模塑部109形成于感光芯片103周围，并且模塑部109的上表面与感光芯片103的上表面齐平，构成一个整体的平整面。再布线层102形成于所述平整面。该再布线层102的上表面具有与多个第一电极1014一一对应的多个第二电极1022，并且通过再布线层102的电路层各个第二电极1022分别与对应的芯片电极1033连通。
在现有设计中，感光组件包括一感光芯片和一线路板，线路板具有一通孔，该通孔对应于所述感光芯片的感光区域；感光芯片的光轴与通孔物理中心线重叠或者偏差较小。但通常来说，由于工艺限制，线路板下表面的第一焊盘与通孔的距离较远。当采取芯片倒贴组装时，为了使芯片焊盘与线路板的第一焊盘一一对应地附接，不得不将芯片焊盘设置于离通孔较远的位置。这样将导致感光芯片的面积增大，不利于摄像模组的小型化。而上述实施例中，则通过其他工艺在不增加芯片焊盘1033到所述通孔1013距离的前提下，实现感光芯片103和线路板101的附接和导通。
在一个实施例中，所述感光组件包括一感光芯片组件105、一线路板101和一再布线层102，所述感光芯片组件105包括一感光芯片103以及延伸于感光芯片103两侧的扩展层109，其中所述感光芯片103具有感光区域1031和围绕在感光区域1031周围的非感光区域1032，其中所述非感光区域1032设置有多个芯片电极1033。其中，所述扩展层109从所述非感光区域1032往周侧延伸，从而使得所述感光芯片103组件长宽尺寸相对于所述感光芯片103尺寸得以扩张。其中，所述扩展层109举例但不限定于通过光刻工艺、模塑工艺等形成。
进一步地，所述再布线层102成形成于所述感光芯片组件105的上表面，即所述再布线层102被设置于所述感光芯片组件105的所述感光芯片103的非感光区域1032和所述扩展层109的上表面，其中所述再布线层102上表面贴于所述线路板101的下表面。详细地讲，所述线路板101的下表面具有多个第一焊盘1014，进一步，所述再布线层102下表面具有多个第二焊盘1022，所述多个第一焊盘1014中的 每个分别通过再布线线路1021与对应的所述第二焊盘1022电连接，可理解的是，所述再布线线路1021具有多个第一端和第二端，多个第一端位于所述再布线层102上表面，并在分别附接所述线路板101下表面的第一焊盘1014，所述第二端位于所述再布线层102下表面并连接所述第二焊盘1022。所述第二焊盘1022分别与所述多个芯片电极1033一一对应地接触并导通，从而使得所述感光芯片103通过第二焊盘1022与所述再布线层102布线导通，再通过所述再布线层102导通于所述线路板101的所述第一焊盘1014，从而使得所述感光元件103与所述线路板101导通。值得注意的是，本申请该实施例中，所述第一焊盘1014的尺寸(或面积)大于所述第二焊盘1022的尺寸，优选地所述第二焊盘1022尺寸接近于所述芯片电极1033尺寸。再者，所述第一焊盘1014沿着所述感光芯片103的光轴方向(或垂直所述感光芯片103组件方向)被投影(正投影)于所述感光芯片103组件上表面时，所述第一焊盘1014投影位于所述第二焊盘1022外侧，或位于所述扩展层109。
进一步地，在本申请的一个实施例中，优选地于所述感光芯片103周侧形成扩展层109，以得到所述感光芯片组件105，再于所述感光芯片组件105上设置所述再布线层102，其次，将制造形成的所述感光芯片组件105和所述再布线层102半成品，一同贴附于所述线路板101下表面，其中所述再布线层102第二焊盘1022对应附接于所述感光芯片103的感光电极，所述再布线层102上表层，对应贴和于所述线路板101下表面，且所述第二焊盘1022通过所述再布线层与所述第一焊盘1014导通，以使得所述感光芯片103可导通于所述线路板101。值得一提的是，在形成所述扩展层109时，可以对所述感光芯片103单独进行；也可以对至少一所述感光芯片103采取拼版方式进行，从而提升制程效率。
在本申请另一变形实施例中，所述感光芯片组件105包括一感光元件103和一扩展层109，与图20所述的实施例不同的是，在本变形实施例中，所述扩展层109为一体延伸于所述感光元件，即在所述感光芯片103加工过程中，所述感光芯片103的非感光区域1032可适当 扩展，并形成所述扩展层109。从而可省去额外制造所述扩展层109的工艺。
进一步地，所述线路板也可被实施为一内嵌电路的模制电路板，所述模制电路板通过植铜、模制、研磨等工艺制作而成，所述模制电路板具有较高的结构强度、平整度，以及更小的线路宽度，例如30μm，其较高的平整度适于后续的再布线工艺、植铜工艺的进行。另外，所述摄像模组的一系列电子元器件、例如电阻、电容，可被内嵌于所述模制电路板，从而起到电磁屏蔽、保护电子元器件的作用，同时也可一定程度较小所述摄像模组的长宽尺寸。
需要注意，前述实施例中，第二电极的面积均小于对应的第一电极的面积，但本申请并不限于此。例如在本申请的一个变形的实施例中，可以将第二电极制作成细长的形状，此时第二电极的面积可以大于或等于对应的第一电极的面积。这种方案可以在保证芯片电极与第二电极的接触面积的同时，提高单位宽度的附接点(例如焊接点或压合点)的数量。
进一步地，在一个实施例中，所述芯片电极为长条形，其沿着所述感光区域的边布置，并且所述芯片电极的短边平行于所述感光区域的位于该芯片电极一侧的边。相应地，所述第二电极为长条形，并且所述第二电极的短边平行于所述感光区域的位于该第二电极一侧的边。
进一步地，在一个实施例中，对于所述感光区域的每一条边，所述线路板具有与该边对应的多排第一电极，所述多排第一电极通过所述再布线层连接至单排第二电极，所述单排第二电极与所述感光芯片对应的单排芯片电极附接并导通。需注意，本实施例还可以有其它变形。例如，所述感光区域的四条边中，可以仅有一条边一侧的线路板具有多排第一电极。当然，所述感光区域的四条边中，也可以有两条边或三条边一侧的线路板分别具有多排第一电极。
需注意，本文中，光刻胶指的是不需要高温加工的材料，光刻胶固化工艺包括但不限于光照、湿气、压力、辐射、结晶等热效应较低 的工艺。
以上描述仅为本申请的较佳实施方式以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (26)

  1. 一种感光组件，其特征在于，包括：
    感光芯片，其具有感光区域和围绕在所述感光区域周围的非感光区域，其中所述非感光区域设置有多个芯片电极；
    线路板，其具有与所述感光区域对应的通孔，所述线路板的下表面具有多个第一电极；以及
    再布线层，形成于所述线路板的下表面，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线走线与对应的所述第二电极电连接；以及，所述感光芯片附接于所述再布线层的下表面，并且所述多个第二电极分别与所述多个芯片电极一一对应地接触并导通。
  2. 根据权利要求1所述的感光组件，其特征在于，所述第二电极比所述第一电极靠近所述通孔。
  3. 根据权利要求1所述的感光组件，其特征在于，所述第二电极的面积小于所述第一电极的面积。
  4. 根据权利要求1所述的感光组件，其特征在于，所述多个第二电极的密集度高于所述多个第一电极。
  5. 根据权利要求1所述的感光组件，其特征在于，所述芯片电极为长条形，其沿着所述感光区域的边布置，并且所述芯片电极的短边平行于所述感光区域的位于该芯片电极一侧的边。
  6. 根据权利要求5所述的感光组件，其特征在于，所述第二电极为长条形，并且所述第二电极的短边平行于所述感光区域的位于该第二电极一侧的边。
  7. 根据权利要求1所述的感光组件，其特征在于，对于所述感光区域的至少一条边，所述线路板具有与该边对应的多排第一电极，所述多排第一电极通过所述再布线层连接至单排第二电极，所述单排第二电极与所述感光芯片对应的单排芯片电极附接并导通。
  8. 根据权利要求1所述的感光组件，其特征在于，所述再布线层的走线的宽度小于所述线路板的走线的宽度。
  9. 根据权利要求1所述的感光组件，其特征在于，所述线路板的下表面具有凹槽，所述感光芯片位于所述凹槽内。
  10. 根据权利要求9所述的感光组件，其特征在于，所述感光组件还包括金属片，所述金属片附接于所述线路板并盖住所述凹槽。
  11. 根据权利要求10所述的感光组件，其特征在于，所述金属片与所述感光芯片之间留有间隙。
  12. 根据权利要求1所述的感光组件，其特征在于，所述线路板的下表面为平坦化处理后的表面。
  13. 根据权利要求1所述的感光组件，其特征在于，所述第二电极为金属柱。
  14. 根据权利要求13所述的感光组件，其特征在于，所述金属柱的下表面具有导电附接材料。
  15. 一种线路板组件，其特征在于，包括：
    线路板，其具有与所述感光区域对应的通孔，所述线路板的下表面具有多个第一电极；以及
    再布线层，形成于所述线路板的下表面，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线与对应的所述第二电极电连接；以及，所述感光芯片附接于所述再布线层的下表面，并且所述多个第二电极的尺寸和布局适于基于倒贴工艺附 接感光芯片，使得所述多个第二电极分别与所述感光芯片的多个芯片电极一一对应地接触并导通。
  16. 根据权利要求15所述的线路板组件，其特征在于，所述第二电极比所述第一电极靠近所述通孔。
  17. 根据权利要求15所述的线路板组件，其特征在于，所述第二电极的面积小于所述第一电极的面积。
  18. 根据权利要求15所述的线路板组件，其特征在于，所述多个第二电极的密集度高于所述多个第一电极。
  19. 一种摄像模组，其特征在于，包括：
    权利要求1～14中任一项所述的感光组件；以及
    安装于所述感光组件的光学镜头。
  20. 一种感光组件制作方法，其特征在于，包括：
    在线路板的下表面形成再布线层构成线路板组件，其中所述线路板的下表面具有多个第一电极，所述再布线层的下表面具有多个第二电极，所述多个第一电极中的每个分别通过再布线与对应的所述第二电极电连接；以及
    将感光芯片附接于所述线路板组件，其中所述多个第二电极分别与所述多个芯片电极一一对应地接触并导通。
  21. 根据权利要求20所述的感光组件制作方法，其特征在于，在线路板的下表面形成再布线层的步骤包括：
    对所述线路板的下表面进行平坦化处理；以及
    在平坦化处理后的线路板的下表面上形成所述再布线层。
  22. 根据权利要求21所述的感光组件制作方法，其特征在于， 在线路板的下表面形成再布线层的步骤包括：
    在线路板的下表面直接制作再布线走线层，所述再布线走线层的走线将所述第一电极从远离所述线路板的通光孔的第一端连接至靠近所述通光孔的第二端；以及
    在再布线走线层的所述第二端的位置上制作所述第二电极。
  23. 根据权利要求22所述的感光组件制作方法，其特征在于，在线路板的下表面形成再布线层的步骤还包括：在制作所述第二电极后覆盖保护层。
  24. 根据权利要求20所述的感光组件制作方法，其特征在于，在线路板的下表面形成再布线层的步骤包括：
    在线路板的下表面形成绝缘层，其中形成所述绝缘层的工艺温度低于所述线路板发生翘曲的临界温度；
    在绝缘层表面形成再布线走线层，所述再布线走线层的走线将所述第一电极从远离所述线路板的通光孔的第一端连接至靠近所述通光孔的第二端；以及
    在所述再布线走线层的所述第二端的位置上制作所述第二电极。
  25. 根据权利要求20所述的感光组件制作方法，其特征在于，所述线路板具有与感光区域对应的通孔；
    执行所述在线路板的下表面形成再布线层的步骤前，将所述通孔填充使得所述线路板的下表面和填充物的下表面形成一完整的平面；以及
    执行将感光芯片附接于所述线路板组件的步骤前，去除所述填充物以露出所述通孔。
  26. 根据权利要求25所述的感光组件制作方法，其特征在于，将所述通孔填充的步骤中，所述填充物为光刻胶。
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CN208956151U (zh) * 2018-06-29 2019-06-07 宁波舜宇光电信息有限公司 线路板组件、感光组件及摄像模组

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