CN106233450B - 晶片支承构造体 - Google Patents

晶片支承构造体 Download PDF

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CN106233450B
CN106233450B CN201680001162.4A CN201680001162A CN106233450B CN 106233450 B CN106233450 B CN 106233450B CN 201680001162 A CN201680001162 A CN 201680001162A CN 106233450 B CN106233450 B CN 106233450B
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tray plate
lateral electrode
substrate
chip
wafer supporting
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CN106233450A (zh
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竹林央史
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NGK Insulators Ltd
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    • H—ELECTRICITY
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    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
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Abstract

本发明提供一种晶片支承构造体。该晶片支承构造体(10)在陶瓷制的基板(20)的上表面配置有具备多个对晶片(W)进行载置的晶片载置部(14)的陶瓷制的托盘板(12)。基板(20)内置有基体侧电极(22)，托盘板(12)内置有托盘侧电极(18)。在该晶片支承构造体(10)中，在晶片载置部(14)载置有晶片(W)的状态下对施加于基体侧电极(22)以及托盘侧电极(18)的电压进行调整。由此，产生将基板(20)和托盘板(12)相互拉近的静电的力，并且产生将托盘板(12)和晶片(W)相互拉近的静电的力。

Description

晶片支承构造体
技术领域
本发明涉及晶片支承构造体。
背景技术
以往，已知有具备多个对晶片进行载置的晶片载置部的晶片支承构造体(例如专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2010-59494号公报
发明内容
发明所要解决的课题
然而，作为这样的晶片支承构造体，已知有图8所示的构造体。该晶片支承构造体100将具备多个对晶片W进行载置的晶片载置部104的输送用Al2O3板102配置于AlN静电卡盘110的上表面。在输送用Al2O3板102的背面形成有导电材料(例如Ni)的镀层106。另外，在AlN静电卡盘110中内置有正负一对电极112、114。若在各晶片载置部104载置晶片W的状态下对电极112、114施加直流电源DC1、DC2的直流电压，则在输送用Al2O3板102的镀层106和AlN静电卡盘110之间产生Johnsen-Rahbek力(JR力)，输送用Al2O3板102吸附于AlN静电卡盘110。此外，晶片载置部104的表面(与晶片W接触的面)为研磨面。另外，在AlN静电卡盘110中与镀层106对置的面形成有压纹(省略图示)，压纹的表面(与镀层106接触的面)为镜面。
然而，在图8的晶片支承构造体中，晶片W仅载置于输送用Al2O3板102的晶片载置部104，因此晶片W与晶片载置部104的表面的接触热电阻较大。因此，存在如下情况，在从上部存在等离子体热量输入的情况下，晶片W的温度变得过高、晶片W的温度分布(最高温度与最低温度之差)变得过大。
本发明鉴于上述的课题而完成，其主要目的在于防止晶片变得过于高温、晶片的温度分布变得过大。
解决课题所用的方法
本发明的晶片支承构造体，在陶瓷制的基板的上表面配置有陶瓷制的托盘板，该托盘板具备多个对晶片进行载置的晶片载置部，所述晶片支承构造体的特征在于，
所述基板内置有基体侧电极，
所述托盘板内置有托盘侧电极，
在所述晶片载置部载置有所述晶片的状态下对施加于所述基体侧电极以及所述托盘侧电极的电压进行调整，由此产生将所述基板和所述托盘板相互拉近的静电的力，并且产生将所述托盘板和所述晶片相互拉近的静电的力。
在该晶片支承构造体中，在晶片载置部载置有上述晶片的状态下对施加于上述基体侧电极以及上述托盘侧电极的电压进行调整，从而在基板和托盘板之间以及托盘板和晶片之间产生静电的力(吸附力)。由此，晶片和晶片载置部之间的接触热电阻与在晶片和晶片载置部之间不产生吸附力的情况相比变小。因此，在从上方对晶片进行加热的情况下，能够防止晶片的温度变得过高、晶片的温度分布变得过大。
在本发明的晶片支承构造体中，所述托盘板也可以在与所述基板对置的面具有金属层，在所述晶片载置部载置有所述晶片的状态下对所述基体侧电极以及所述托盘侧电极双方施加电压，由此产生将所述基板和所述托盘板的所述金属层相互拉近的静电的力，并且产生将所述托盘板和所述晶片相互拉近的静电的力。或者，所述托盘板也可以在与所述基板对置的面不具有金属层，在所述晶片载置部载置有所述晶片的状态下对所述托盘侧电极施加电压，由此产生将所述基板和所述托盘板相互拉近的静电的力，并且产生将所述托盘板和所述晶片相互拉近的静电的力。
在本发明的晶片支承构造体中，上述晶片载置部中与上述晶片接触的面也可以形成平坦的镜面。这样一来，同与晶片接触的面为研磨面的情况相比，晶片与晶片载置部的接触面积增大，因此本发明的效果变得显著。
在本发明的晶片支承构造体中，上述托盘板可以为Al2O3制，上述基板也可以为AlN制。
在本发明的晶片支承构造体中，上述托盘侧电极为具有负极和正极的双极构造，各晶片载置部的上述负极与上述正极的面积比也可以为0.7～1：0.7～1(优选为0.9～1：0.9～1)。这样一来，在晶片难以产生吸附力较强的地方和较弱的地方，从而能够进一步缩小晶片的温度分布。
附图说明
图1是第一实施方式的晶片支承构造体10的纵向剖视图。
图2是第一实施方式的晶片支承构造体10的俯视图。
图3是第二实施方式的晶片支承构造体30的纵向剖视图。
图4是表示从上方观察构成第二实施方式的托盘侧电极的负极18a、正极18b时的一个例子的透视图。
图5是表示从上方观察构成第二实施方式的托盘侧电极的负极18a、正极18b时的一个例子的透视图。
图6是表示从上方观察构成第二实施方式的托盘侧电极的负极18a、正极18b时的一个例子的透视图。
图7是第三实施方式的晶片支承构造体40的纵向剖视图。
图8是以往的晶片支承构造体100的纵向剖视图。
具体实施方式
[第一实施方式]
以下，使用图1以及图2对本发明的晶片支承构造体的一个例子进行说明。图1是第一实施方式的晶片支承构造体10的纵向剖视图，图2是晶片支承构造体10的俯视图。
晶片支承构造体10用于对利用等离子体进行CVD、蚀刻等的晶片W进行支承，安装于半导体工艺用的腔室(省略图示)的内部。
晶片支承构造体10在陶瓷制(此处为AlN制)的基板20的上表面配置有具备多个对晶片W进行载置的晶片载置部14的陶瓷制(此处为Al2O3制)的托盘板12。
托盘板12是用于输送晶片W的圆盘状的板，在上表面具有多个晶片载置部14。晶片载置部14是从上方观察到的形状呈圆形的凹陷，并形成为比圆盘状的晶片W稍大的尺寸。此处，就晶片载置部14而言，在从上方观察托盘板12时，在中央形成有一个，在托盘板12的同心圆上空开60°地形成六个，合计形成有七个(参照图2)。晶片载置部14的表面即与晶片W接触的面被加工成平坦的镜面。在托盘板12的背面即与基板20对置的面形成有导电材料(例如Ni)的镀层16。托盘板12内置有圆盘状的托盘侧电极18。托盘侧电极18埋设于距晶片载置部14的表面0.35±0.05mm的位置。该托盘侧电极18的供电销17从基板20的下表面贯通基板20而到达托盘侧电极18。供电销17的前端可以为平坦面，也可以为曲面(球面)。
基板20为圆盘状的板，并内置有基体侧电极22。基体侧电极22由梳齿负极22a和梳齿正极22b构成，并将相互的梳齿配置为保持非接触状态地相互进入。梳齿负极22a与梳齿正极22b的面积比为0.7～1：0.7～1。该基体侧电极22埋设于距上表面1±0.5mm的位置。在基板20的上表面换句话说与托盘板12对置的面形成有多个压纹(省略图示)。这些压纹的表面(与镀层16接触的面)被加工为镜面。基板20具备从下表面到达梳齿负极22a的供电销24a和从下表面到达梳齿正极22b的供电销24b。另外，在基板20设置为沿上下方向贯通绝缘套筒26。托盘侧电极18的供电销17插通该绝缘套筒26。供电销17被调节为通过设置于绝缘套筒26内的弹性体(省略图示)使向托盘侧电极18的接触负载成为200g。托盘侧电极18以及基体侧电极22可以通过印刷而形成，也可以通过埋设网目而形成。
接下来，对本实施方式的晶片支承构造体10的使用例进行说明。首先，在各晶片载置部14载置晶片W。而且，对供电销24a、24b分别施加直流电源DC1、DC2的电压，对供电销17施加直流电源DC3的电压。另外，对未图示的平行平板施加高频电压从而在晶片W的上方产生等离子体。等离子体起到晶片W的接地电极的作用。由此，在基体侧电极22和托盘板12的镀层16之间产生JR力，从而在托盘侧电极18和各晶片W之间产生库伦力。在该状态下，利用等离子体对晶片W实施CVD成膜、实施蚀刻。
根据以上详述的晶片支承构造体10，晶片W和晶片载置部14之间的接触热电阻与不在晶片W和晶片载置部14之间产生吸附力的情况相比变小。因此，在从上方对晶片W进行加热的情况下，能够防止晶片W变得过于高温、晶片W的温度分布变得过大。另外，晶片载置部14中与晶片W接触的面为平坦的镜面，因此与该面为研磨面的情况相比，晶片W与晶片载置部14的接触面积增大，从而能够显著地获得本发明的效果。
[第二实施方式]
如图3所示，第二实施方式的晶片支承构造体30除了变更了托盘板12的托盘侧电极的结构以外，与晶片支承构造体10相同。具体来说，就晶片支承构造体30而言，由锯齿形状的负极18a和正极18b构成内置于托盘板12的托盘侧电极，并将它们配置为保持相互非接触状态地相互进入。另外，在负极18a连接供电销17，在正极18b连接供电销19。供电销19插通于贯通基板20的绝缘套筒27。另外，在供电销17、19分别施加直流电源DC3、DC4的电压。此处，图4～图6表示从上方观察托盘板12时的透视图。图4是在托盘板12载置21个2英寸的晶片W的例子，图5以及图6是在托盘板12载置7个4英寸的晶片W的例子。在各图中，利用较细的网眼表示负极18a，利用较粗的网眼表示正极18b。负极18a和正极18b的间隔没有特别地限定，例如选为2～6mm即可。另外，托盘侧电极18的电极端(外周端)和托盘板12的距离也没有特别地限定，例如优选为1～4mm。图4～图6中的任一个均设定为在观察一个晶片W时负极18a与正极18b的面积比成为0.7～1：0.7～1(在图4～图6中，为1：1)。在使用该晶片支承构造体30时，首先，在各晶片载置部14载置晶片W。而且，对供电销24a、24b分别施加直流电源DC1、DC2的电压，对供电销17、19施加直流电源DC3、DC4的电压。另外，对未图示的平行平板施加高频电压从而在晶片W的上方产生等离子体。由此，在基体侧电极22和托盘板12的镀层16之间产生JR力，在托盘侧电极(负极18a和正极18b)和各晶片W之间产生库伦力。因此，能够获得与晶片支承构造体10相同的效果。另外，在观察一个晶片W时，负极18a与正极18b的面积比成为0.7～1：0.7～1，因此各晶片W难以产生吸附力较强的地方和较弱的地方，从而能够缩小晶片W的温度分布。
[第三实施方式]
如图7所示，第三实施方式的晶片支承构造体40除了未形成托盘板12的镀层16、变更了基板20的基体侧电极的结构以外，与晶片支承构造体10相同。具体而言，晶片支承构造体40未在托盘板12的下表面形成镀层16而是直接载置于基板20。另外，基板20的基体侧电极42做成一张圆盘状的电极，并使其通过接地管脚42a而接地。基体侧电极42配置于距上表面0.5±3mm处。另外，托盘侧电极18配置于距晶片载置面14的表面以及托盘板12的下表面0.35±0.05mm处。在使用该晶片支承构造体40时，首先，在各晶片载置部14载置晶片W。然后，对供电销17分别施加直流电源DC1的电压。另外，对未图示的平行平板施加高频电压从而在晶片W的上方产生等离子体。等离子体起到晶片W的接地电极的作用。由此，在基体侧电极42和托盘侧电极18之间产生库伦力，在托盘侧电极18和各晶片W之间产生库伦力。因此，能够获得与晶片支承构造体10相同的效果。此外，托盘板12的使用温度的体积电阻率优选在1×1015Ωcm以上。
此外，上述的实施方式不对本发明造成任何限定，不言而喻只要属于本发明的技术范围，则能够以各种方式实施。
实施例
针对第一实施方式～第三实施方式的晶片支承构造体10、30、40以及以往的晶片支承构造体100，对产生等离子体热量输入时的晶片W的温度以及温度分布进行测定。
就晶片支承构造体10而言，对直流电源DC1、DC2、DC3分别施加－500V、+500V、－2.5kV。就晶片支承构造体30而言，对直流电源DC1、DC2、DC3、DC4分别施加－500V、+500V、－2.5kV、+2.5kV。就晶片支承构造体40而言，对直流电源DC1施加－2.5kV。就晶片支承构造体100而言，对直流电源DC1、DC2分别施加－500V、+500V。在如上施加电压的状态下，针对各晶片支承构造体10、30、40、100以如下方式进行控制，将等离子体热量输入设定为1kW，使基板20的温度成为40℃。此外，在基板20的下表面安装铝冷却板，在铝冷却板的内部循环冷却液。然后，测定设置于托盘板12的晶片载置部14的七个晶片W的温度的平均值和各晶片W的温度分布(最高温度与最低温度之差)中的最大值。其结果示于表1。如表1所示，第一实施方式～第三实施方式的晶片支承构造体10、30、40与以往的晶片支承构造体100相比，能够减少晶片W的温度，并且能够将晶片W的温度分布抑制得较小。
表1
(表格文字说明：晶片支承构造体，晶片与托盘板的吸附力，托盘板与基板的吸附力，晶片的温度，晶片的温度分布)
本申请主张于2015年1月20日申请的美国临时申请第62/105371号的优先权，通过引用将其内容的全部包含于本说明书。
此外，上述的实施例不言而喻不对本发明进行任何限定。
工业上的可利用性
本发明能够利用于对晶片进行成膜、蚀刻等的晶片处理装置。
附图标记的说明
10—晶片支承构造体，12—托盘板，14—晶片载置部，16—镀层，17—供电销，18—托盘侧电极，18a—负极，18b—正极，19—供电销，20—基板，22—基体侧电极，22a—梳齿负极，22b—梳齿正极，24a—供电销，24b—供电销，6—绝缘套筒，27—绝缘套筒，30—晶片支承构造体，40—晶片支承构造体，42—基体侧电极，42a—接地管脚，100—晶片支承构造体，102—输送用Al2O3板，104—晶片载置部，106—镀层，110—AlN静电卡盘，112、114—电极。

Claims (7)

1.一种晶片支承构造体，在陶瓷制的基板的上表面配置有陶瓷制的托盘板，该托盘板具备多个对晶片进行载置的晶片载置部，所述晶片支承构造体的特征在于，
所述基板内置有基体侧电极，
所述托盘板内置有托盘侧电极，
在所述晶片载置部载置有所述晶片的状态下对施加于所述基体侧电极以及所述托盘侧电极的电压进行调整，由此产生将所述基板和所述托盘板相互拉近的静电的力，并且产生将所述托盘板和所述晶片相互拉近的静电的力，
所述托盘侧电极为具有负极和正极的双极构造，各晶片载置部中所述负极与所述正极的面积比为0.7～1：0.7～1。
2.根据权利要求1所述的晶片支承构造体，其特征在于，
所述托盘板在与所述基板对置的面具有金属层，
在所述晶片载置部载置有所述晶片的状态下对所述基体侧电极以及所述托盘侧电极双方施加电压，由此产生将所述基板和所述托盘板的所述金属层相互拉近的静电的力，并且产生将所述托盘板和所述晶片相互拉近的静电的力。
3.根据权利要求1所述的晶片支承构造体，其特征在于，
所述托盘板在与所述基板对置的面不具有金属层，
在所述晶片载置部载置有所述晶片的状态下对所述托盘侧电极施加电压，由此产生将所述基板和所述托盘板相互拉近的静电的力，并且产生将所述托盘板和所述晶片相互拉近的静电的力。
4.根据权利要求1～3中任一项所述的晶片支承构造体，其特征在于，
所述托盘侧电极埋设于距所述晶片载置部的表面0.35±0.05mm的位置。
5.根据权利要求1～3中任一项所述的晶片支承构造体，其特征在于，
所述基体侧电极埋设于距所述基板的上表面1±0.5mm的位置。
6.根据权利要求1～3中任一项所述的晶片支承构造体，其特征在于，
在所述基板上设置有贯通所述基板的绝缘套筒，
所述托盘侧电极通过插通于所述绝缘套筒的供电销而被供电。
7.根据权利要求1～3中任一项所述的晶片支承构造体，其特征在于，
所述托盘板为Al2O3制，
所述基板为AlN制。
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