CN106233426A - 贴合式soi晶圆的制造方法及贴合式soi晶圆 - Google Patents

贴合式soi晶圆的制造方法及贴合式soi晶圆 Download PDF

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CN106233426A
CN106233426A CN201580020540.9A CN201580020540A CN106233426A CN 106233426 A CN106233426 A CN 106233426A CN 201580020540 A CN201580020540 A CN 201580020540A CN 106233426 A CN106233426 A CN 106233426A
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CN106233426B (zh
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目黑贤二
若林大士
小林德弘
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Shin Etsu Handotai Co Ltd
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Abstract

一种贴合式SOI晶圆的制造方法，为关于均以单晶硅构成的贴合晶圆及基底晶圆借由绝缘膜贴合的贴合式SOI晶圆的制造方法，包含下列步骤：堆积多晶硅层于该基底晶圆的贴合面侧，研磨该多晶硅层的表面，于该贴合晶圆的贴合面形成该绝缘膜，透过该绝缘膜将该基底晶圆的该多晶硅层的研磨面与该贴合晶圆贴合，以及将经贴合的该贴合晶圆薄膜化而形成SOI层，其中，该基底晶圆使用电阻率100Ω·cm以上的单晶硅晶圆，该堆积多晶硅层的步骤进一步包含于贴合晶圆的堆积该多晶硅层的表面预先形成氧化膜，该多晶硅层的堆积以900℃以上的温度进行。借此能够堆积多晶硅层而使其即使经过SOI晶圆制造步骤的热处理步骤或装置制造步骤的热处理步骤也不会进行单晶化。

Description

贴合式SOI晶圆的制造方法及贴合式SOI晶圆
技术领域
本发明是关于一种贴合式SOI晶圆的制造方法及贴合式SOI晶圆。
背景技术
作为对应高频率(Radio Frequency,RF)装置的SOI晶圆，一直是以将基底晶圆予以电阻率以解决。但是，为对应进一步的高速化，而逐渐有对应更高的频率的必要，仅使用已知的高电阻晶圆已经逐渐无法解决。
在此，作为对策提出于SOI晶圆的埋入氧化膜层(BOX层)正下方，加入具有使产生的载子消灭的层(载体捕陷层)，逐渐有必要将用以使高电阻晶圆中所产生的载子再结合的多晶硅层形成于基底晶圆上。
专利文献1中，记载有于BOX层及基底晶圆的境界面形成作为载子捕陷层的多晶硅层或非晶硅层。
另一方面，专利文献2中，也记载有于BOX层及基底晶圆的境界面形成作为载子捕陷层的多晶硅层，进一步限制多晶硅层形成后的热处理温度以防止多晶硅层的再结晶化。
在另一专利文献3中，虽未记载有形成作为载子捕陷层的多晶硅层或非晶硅层，但记载有透过将与贴合晶圆贴合的一侧的基底晶圆表面的表面粗糙度放大，能够得到与载子捕陷层同样的效果。
〔现有技术文献〕
专利文献1：日本特表2007-507093号公报
专利文献2：日本特表2013-513234号公报
专利文献3：日本特开2010-278160号公报
发明内容
[发明所欲解决的问题]
如同前述，为了制造对应更高频率的装置，逐渐有必要于SOI晶圆的BOX层下形成载子捕陷层。
但是，若堆积一般的多晶硅层而形成载子捕陷层，依SOI晶圆制造步骤中或装置制造步骤中的热经历则会有多晶硅层被退火处理而单晶化，使其作为离子捕陷层的效果减少的问题。
因此，有使多晶硅层堆栈后即使进行热处理也不会进行单晶化的必要。换句话说，有堆积经过SOI晶圆制造步骤的热处理步骤或装置制造步骤的热处理步骤也不会进行单晶化、成本低廉而效果持久的多晶硅层的必要。
但是，前述的专利文献1至3中，均没有揭示及建议关于即使多晶硅层堆积后进行热处理也不会进行单晶化的技术。
本发明鉴于前述问题，目的在于提供一种SOI晶圆的制造方法，能够堆积多晶硅层而使其即使经过SOI晶圆制造步骤的热处理步骤或装置制造步骤的热处理步骤也不会进行单晶化。
[解决问题的技术手段]
为达成前述目的，本发明提供一种贴合式SOI晶圆的制造方法，是关于均以单晶硅构成的贴合晶圆及基底晶圆借由绝缘膜贴合的贴合式SOI晶圆的制造方法，包含下列步骤：
堆积多晶硅层于该基底晶圆的贴合面侧；
研磨该多晶硅层的表面；
于该贴合晶圆的贴合面形成该绝缘膜；
透过该绝缘膜将该基底晶圆的该多晶硅层的研磨面与该贴合晶圆贴合；以及
将经贴合的该贴合晶圆薄膜化而形成SOI层，
其中，该基底晶圆使用电阻率100Ω·cm以上的单晶硅晶圆，
该堆积多晶硅层的步骤进一步包含于贴合晶圆的堆积该多晶硅层的表面预先形成氧化膜，
该多晶硅层的堆积以900℃以上的温度进行。
如此，透过于基底晶圆的单晶硅表面及堆积的多晶硅层之间预先形成氧化膜，能够抑制堆积后SOI制造步骤的热处理步骤或装置制造步骤的热处理致使的单晶化。
进一步而言，借由将堆积温度设为900℃以上的温度，即使SOI晶圆的制造步骤的热处理步骤或装置制造步骤的热处理为相对高温(例如，1000至1200℃左右)，也能够抑制多晶硅层的晶界成长，维持作为载子捕陷层的效果。
此时，该氧化膜以透过湿洗形成为佳。
由于使氧化膜存在基底晶圆及多晶硅层之间可能影响RF装置的特性，因此所形成的氧化膜厚度以较薄为佳，例如以10nm以下的厚度为佳。作为形成如此厚度的氧化膜的方法，能够举出湿洗为最简易的方法。
此时，以该多晶硅层堆积的温度为1010℃以下为佳。
当以湿洗净形成数纳米的氧化膜时，若于其上堆积多晶硅层的温度在1010℃以下，则多晶硅层的堆积步骤中，能够抑制基层氧化膜的一部分消失，基底晶圆的单晶硅的表面与多晶硅层接触而被促进的多晶硅层的单晶化。
在此，该多晶硅层经堆积后，以较该多晶硅层的堆积温度更高温的非氧化性氛围进行热处理，之后将该基底晶圆及该贴合晶圆贴合为佳。
虽然为了使作为载子捕陷层的效果提高而以使多晶硅层的厚度较厚为宜，但是厚度愈厚堆积后的晶圆的翘曲将会变大，成为贴合不良的原因。但是，能够于堆积多晶硅层后的贴合之前，以较多晶硅层的堆积温度更高温的非氧化性氛围进行热处理以减低晶圆的翘曲。
此时，以该多晶硅层贴合时的厚度在2μm以上为佳。
借由使多晶硅层的贴合时厚度在2μm以上虽然会由于晶圆的翘曲的影响而提高贴合不良的机率，但即使多晶硅层的贴合时的厚度在2μm以上，若是以高温的非氧化性氛围进行热处理，则能够降低晶圆的翘曲，因此能够提高作为载子捕陷层的效果，并追求贴合不良的减低。
本发明还提供一种贴合式SOI晶圆，具有：
基底晶圆，其由单晶硅所构成；
多晶硅层，位于该基底晶圆上；
绝缘膜，位于该多晶硅层上；以及
SOI层，位于该绝缘膜上，
该基底晶圆的电阻率为100Ω·cm以上，该基底晶圆与该多晶硅层的境界部的氧气浓度，高于该基底晶圆中的氧气浓度及该多晶硅层中的氧气浓度。
如此，基底晶圆与多晶硅层的境界部的氧浓度，若是高于基底晶圆中的氧浓度及多晶硅层中的氧浓度，则能够抑制多晶硅层的单晶化，而维持作为载子捕陷层的效果。
[对照现有技术的功效]
如同前述，依照本发明的贴合式晶圆的制造方法，透过于基底晶圆的单晶硅表面及堆积的多晶硅层之间预先形成氧化膜，能够抑制堆积后SOI制造步骤的热处理步骤或装置制造步骤的热处理致使的单晶化。
进一步而言，借由将堆积温度设为900℃以上的温度，即使SOI晶圆的制造步骤的热处理步骤或装置制造步骤的热处理为相对高温(例如，1000至1200℃左右)，亦能够抑制多晶硅层的晶界成长，维持作为载子捕陷层的效果。
又依照本发明的贴合式晶圆，若是使基底晶圆与多晶硅层的境界部的氧浓度高于基底晶圆中的氧浓度及多晶硅层中的氧浓度，则能够抑制多晶硅层的单晶化，而维持作为载子捕陷层的效果。
附图简要说明
图1是显示本发明的贴合式SOI晶圆的制造方法的实施例之一的制造流程图。
图2是显示本发明的贴合式SOI晶圆的制造方法的实施例之一的步骤剖面示意图。
图3是显示本发明的贴合式SOI晶圆的剖面图。
具体实施方式
以下关于本发明，虽作为实施例之一而参照图式进行说明，但本发明并非限定于此。
如同前述，虽然为了制作对应更高频率的装置而逐渐有必要于SOI晶圆的BOX层下形成载子捕陷层，但若堆积一般的多晶硅层以形成载子捕陷层，则依SOI晶圆的制造步骤中或是装置制造步骤中的热经历，将会有使多晶硅层受到退火处理而单晶化，使其作为载子捕陷层的效果减低的问题。
在此，本申请的发明人积极研究能够堆积即使经过SOI晶圆的制造步骤的热处理步骤或装置制造步骤的热处理步骤亦不会进行单晶化的多晶硅层或非晶硅层的SOI晶圆的制造方法。
其结果发现透过于基底晶圆的单晶硅表面及堆积的多晶硅层之间预先形成氧化膜，能够抑制堆积后SOI制造步骤的热处理步骤或装置制造步骤的热处理致使的单晶化，进一步而言，借由将堆积温度设为900℃以上的温度，即使SOI晶圆的制造步骤的热处理步骤或装置制造步骤的热处理为相对高温(例如，1000至1200℃度)，亦能够抑制多晶硅层的晶界成长，维持作为载子捕陷层的效果，而完成本发明。
以下参照图1至2，说明本发明的贴合式SOI晶圆的制造方法的实施例之一。
首先，准备由单晶硅所构成的贴合晶圆10(参照图1的步骤S11及图2的步骤(a))。
接着，透过例如热氧化或化学气相沉积等，于贴合晶圆10，使成为埋入氧化膜层(BOX层)16的绝缘膜(例如氧化膜)13成长(参照图1的步骤S12及图2的步骤(b))。
接着，于该绝缘膜13的上方以离子注入机注入氢离子及堕性气体离子中的至少一种气体离子，于贴合晶圆10内形成离子注入层17(参照图1的步骤S13及图2的步骤(c))。此时，选择离子注入加速电压以得到目标的SOI层15的厚度。
接着进行贴合前洗净(参照图1的步骤S14)，以除去贴合晶圆10的贴合面的微粒子。
另一方面，除了前述之外，准备由单晶硅所构成的基底晶圆11(参照图1的步骤S21及图2的步骤(d))。
接着，于基底晶圆11上形成氧化膜(基底氧化膜)20(参照图1的步骤S22及图2的步骤(e))。氧化膜20的厚度虽无特别限定，但使氧化膜存在基底晶圆及多晶硅层之间可能影响RF装置的特性，因此所形成的氧化膜厚度以较薄为佳，例如以0.3nm以上，10nm以下的厚度为佳。
作为形成如此厚度的氧化膜的方法，能够举出湿洗为最简易的方法。具体而言，能够透过使用SC1(NH4OH与H2O2的混合水溶液)、SC2(HCl与H2O2的混合水溶液)、SPM(H2SO4与H2O2的混合水溶液)及臭氧水等的洗净，或是进行将此些组合的洗净，以形成厚度在0.5至3nm的均匀的氧化膜。
接着，使多晶硅层12堆积于氧化膜(基底氧化膜)20上(参照图1的步骤S23及图2的步骤(f))。此处，使堆积温度为900℃以上。
若是堆积温度为900℃，或是较900℃更高温，则即使SOI晶圆制造步骤的热处理步骤或装置制造步骤的热处理为相对高温(例如，1000至1200℃左右)，也能够抑制多晶硅层的晶界成长，维持作为载子捕陷层的效果。
又若是堆积温度为900℃，或是较900℃更高温，则能够使用一般的磊晶成长用的化学气相沉积装置，作为原料气体使用三氯氢硅，以常压高速堆积多晶硅层12。
虽若是多晶硅成长，则不特别限定堆积温度的上限，但没有高于SOI晶圆制造步骤或装置制造步骤的最高温度的必要(过高则容易发生滑移错位或金属污染)，因此以其最高温度以下，例如1200℃以下为佳。
接着，将于基底晶圆11所堆积的多晶硅层12的表面透过研磨而平坦化(参照图1的步骤S24及图2的步骤(g))。由于以900℃以上的温度堆积的多晶硅层12的表面粗糙度较大，如此将会难以贴合，因此有必要将多晶硅层12的表面透过研磨而平坦化。
接着，进行贴合前洗净以去除经研磨后的多晶硅层12的表面的微粒子(参照图1的步骤S25)。
另外，图1的步骤S11至S14，与图1的步骤S1至S25可为并行进展。
接着，将形成有多晶硅层12的基底晶圆11与形成有绝缘膜13的贴合晶圆10密着而贴合，以使基底晶圆11形成有的多晶硅层12的面与贴合晶圆10的注入面相接(参照图1的步骤S31及图2的步骤(h))。
接着，对贴合的晶圆施以使离子注入层17产生微小气泡层的热处理(剥离热处理)，于所发生的微小气泡层剥离，而制作基底晶圆11上形成有埋入氧化膜层16及SOI层15的贴合晶圆式14(参照图1的步骤S32及图2的步骤(i))。另外，于此时派生有具有剥离面19的剥离晶圆18。
接着对贴合式晶圆14施以结合热处理(参照图1的步骤S33)，以使贴合界面的结合强度增加。
如同前述而能够制造贴合式SOI晶圆。
本发明的贴合式SOI晶圆的制造方法中，透过于基底晶圆的单晶硅表面及堆积的多晶硅层之间预先形成氧化膜，能够抑制堆积后SOI制造步骤的热处理步骤或装置制造步骤的热处理致使的单晶化，进一步而言，透过使多晶硅层的堆积温度为900℃以上的温度，即使SOI晶圆的制造步骤的热处理步骤或装置制造步骤的热处理为相对高温(例如，1000至1200℃度)，也能够抑制多晶硅层的晶界成长，维持作为载子捕陷层的效果。
又当以湿洗净形成数纳米的基底氧化膜时，若于其上堆积多晶硅层的温度在1010℃以下，则多晶硅层的堆积步骤中，能够抑制基层氧化膜的一部分消失，基底晶圆的单晶硅的表面与多晶硅层接触而被促进的多晶硅层的单晶化。
进一步而言，虽然为了使作为载子捕陷层的效果提高而以使多晶硅层的厚度较厚为宜，但是厚度愈厚堆积后的晶圆的翘曲将会变大，成为贴合不良的原因。但是，能够于堆积多晶硅层厚的贴合之前，以较多晶硅层的堆积温度更高温的非氧化性氛围进行热处理以减低晶圆的翘曲。以非氧化性氛围而言，可为氢气氛围。若为氢气氛围，则只要在多晶硅层堆积后停止原料气体的导入即可简单切换。
又借由使多晶硅层的贴合时厚度在2μm以上虽然会由于晶圆的翘曲的影响而提高贴合不良的机率，但即使多晶硅层的贴合时的厚度在2μm以上，由于能够以在多晶硅层堆积后(贴合前)以高温在非氧化氛围下进行热处理以降低晶圆的翘曲，因此能够提高作为载子捕陷层的效果，同时追求贴合不良的降低。
另外，在高温的非氧化性氛围下的热处理，虽于研磨多晶硅层的表面的步骤的前后皆可进行，由于研磨后不进行洗净以外的步骤便贴合能够使贴合不良降低，因此前述热处理，以于研磨前进行为佳。又多晶硅层的贴合时的厚度以10μm以下为佳。
另外基底晶圆11的电阻率只要为100Ω·cm以上便适合用于高频率装置制造，为1000Ω·cm以上则更佳，3000Ω·cm以上则特佳。电阻率的上限虽无特别限定，但可为例如50000Ω·cm。
接着参照图3，说明本发明的贴合式SOI晶圆。
本发明的贴合式SOI晶圆1，具有由单晶硅所构成的基底晶圆11，位于该基底晶圆11上的多晶硅层12，位于该多晶硅层12上的绝缘膜16以及位于该绝缘膜16上的SOI层15，该基底晶圆11的电阻率为100Ω·cm以上，该基底晶圆11与该多晶硅层12的境界部21的氧气浓度，高于该基底晶圆11中的氧气浓度及该多晶硅层12中的氧气浓度。
若将堆积多晶硅层12前所形成的氧化膜透过湿洗净以形成，则由于所形成的氧化膜较薄，因此以900℃以上堆积多晶硅层12时基底氧化膜容易消失。但是，当堆积温度相对低的状况下(例如在1010℃以下)，则由于氧的扩散并无充分进行，因此基底晶圆11与多晶硅层12的境界部(界面部)21残留有高浓度的氧，借此能够抑制多晶硅层的单晶化，而能够维持作为载子捕陷层的效果。
实施例
以下虽显示实施例及比较例以更具体的说明本发明，但本发明并不限定于此。
(实施例1)
使用于图1至2所说明的制造方法制作贴合式SOI晶圆。但是，作为基底晶圆，使用直径200mm、晶体方位<100>、电阻率700Ω·cm、p型的单晶硅，形成基底氧化膜、堆积多晶硅(使用三氯氢硅作为原料气体)、BOX氧化、注入氢离子、剥离热处理、结合热处理以以下的条件进行。
另外，不进行堆积后退火处理。
又测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况(以剖面SEM观察而确认)。显示其结果于表1。
(实施例2)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以920℃、常压、膜厚度1.5(研磨后1.0μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(实施例3)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以940℃、常压、膜厚度2.1μm(研磨后1.6μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(实施例4)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以960℃、常压、膜厚度2.9μm(研磨后2.4μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(实施例5)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以980℃、常压、膜厚度3.8μm(研磨后3.3μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(实施例6)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以1000℃、常压、膜厚度3.5μm(研磨后3.0μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
进一步而言，关于所制作的贴合式SOI晶圆，以电子显微镜观察(剖面SEM及剖面TEM观察)确认多晶硅层与基底晶圆的境界部的氧化膜的有无。又境界部的氧浓度以二次离子质谱法(Secondary Ion Mass Spectrometry,SIMS)以测量。
其结果，于由电子显微镜画面的目视判断中，并无观察到于境界部有层状连续的氧化膜。又相对于基底晶圆及多晶硅层中的氧浓度皆为1×1017至2×1017atoms/cm3，境界部观察到较基底晶圆及多晶硅层中的氧浓度更高的峰值，峰值的最大值约为8×1020atoms/cm3。
(实施例7)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以1000℃、常压、膜厚度4.9μm(研磨后3.0μm)的条件以进行，堆积后的退火处理于贴合前以1130℃、10分钟、100％H2的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(实施例8)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积，以1010℃、常压、膜厚度5.5μm(研磨后5.0μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(实施例9)
与实施例1同样制作贴合式SOI晶圆。但是基底氧化膜的形成，以800℃、dryO2氧化、氧化膜厚度30nm的条件以进行，多晶硅的堆积，以1040℃、常压、膜厚度1.5μm(研磨后1.0μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(比较例1)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积(使用甲硅烷作为原料气体)，以650℃、减压、膜厚度1.5μm(研磨后1.0μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(比较例2)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积(使用甲硅烷作为原料气体)，以850℃、常压、膜厚度1.5μm(研磨后1.0μm)的条件以进行。
与实施例1同样测量多晶硅层研磨后的晶圆的翘曲，调查结合热处理后的多晶硅层的单晶化状况。显示其结果于表1。
(比较例3)
与实施例1同样制作贴合式SOI晶圆。但是多晶硅层的堆积(使用甲硅烷作为原料气体)，以1020℃、常压、膜厚度6.1μm的条件以进行。
于比较例3中，以多晶硅层堆积后的SEM观察确认到单晶的堆积，由于没有堆积为多晶硅层，因此不实施之后的步骤。
【表1】
自表一可得知，将基底氧化膜的形成以湿洗净进行的实施例1至8，比较例1至3中，将多晶硅层的堆积以900℃以上，1010℃以下进行的实施例1至8中多晶硅层的单晶化虽没有发生，将多晶硅层的堆积于前述温度范围外进行的比较例1至3中发生了多晶硅层的单晶化。
又将基底氧化膜的形成以dryO2氧化进行的实施例9中，虽将多晶硅层堆积以1040℃进行，但并没有发生多晶硅层的单晶化，这可以推测是由于基底氧化膜形成为相对厚的30nm，而没有发生后续步骤的热处理所致的基底氧化膜的消失。
进一步来说，进行堆积后退火处理的实施例7中，减低了晶圆的翘曲。
另外，本发明并不为前述实施例所限制。前述实施例为例示，具有与本发明的申请专利范围所记载的技术思想为实质相同的构成，且达成同样作用效果者，皆包含于本发明的技术范围。

Claims (6)

1.一种贴合式SOI晶圆的制造方法，为关于均以单晶硅构成的贴合晶圆及基底晶圆借由绝缘膜贴合的贴合式SOI晶圆的制造方法，包含下列步骤：
堆积多晶硅层于该基底晶圆的贴合面侧；
研磨该多晶硅层的表面；
于该贴合晶圆的贴合面形成该绝缘膜；
透过该绝缘膜将该基底晶圆的该多晶硅层的研磨面与该贴合晶圆贴合；以及
将经贴合的该贴合晶圆薄膜化而形成SOI层，
其中，该基底晶圆使用电阻率100Ω·cm以上的单晶硅晶圆，
该堆积多晶硅层的步骤进一步包含于贴合晶圆的堆积该多晶硅层的表面预先形成氧化膜，
该多晶硅层的堆积以900℃以上的温度进行。
2.如权利要求1所述的贴合式SOI晶圆的制造方法，其中该氧化膜由湿洗所形成。
3.如权利要求2所述的贴合式SOI晶圆的制造方法，其中该多晶硅层堆积的温度为1010℃以下。
4.如权利要求1至3的任一项所述的贴合式SOI晶圆的制造方法，其中该多晶硅层经堆积后，以较该多晶硅层的堆积温度更高温的非氧化性氛围进行热处理，之后将该基底晶圆及该贴合晶圆贴合。
5.如权利要求4所述的贴合式SOI晶圆的制造方法，其中该多晶硅层的贴合时的厚度在2μm以上。
6.一种贴合式SOI晶圆，具有：
基底晶圆，其由单晶硅所构成；
多晶硅层，位于该基底晶圆上；
绝缘膜，位于该多晶硅层上；以及
SOI层，位于该绝缘膜上，
该基底晶圆的电阻率为100Ω·cm以上，该基底晶圆与该多晶硅层的境界部的氧气浓度，高于该基底晶圆中的氧气浓度及该多晶硅层中的氧气浓度。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023045129A1 (zh) * 2021-09-22 2023-03-30 苏州华太电子技术股份有限公司 半导体结构的制作方法以及半导体结构

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483152B2 (en) 2014-11-18 2019-11-19 Globalwafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
WO2016140850A1 (en) 2015-03-03 2016-09-09 Sunedison Semiconductor Limited Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
US10332782B2 (en) 2015-06-01 2019-06-25 Globalwafers Co., Ltd. Method of manufacturing silicon germanium-on-insulator
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6447439B2 (ja) * 2015-09-28 2019-01-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US10529616B2 (en) 2015-11-20 2020-01-07 Globalwafers Co., Ltd. Manufacturing method of smoothing a semiconductor surface
JP6443394B2 (ja) * 2016-06-06 2018-12-26 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US11142844B2 (en) 2016-06-08 2021-10-12 Globalwafers Co., Ltd. High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
JP6614076B2 (ja) 2016-09-07 2019-12-04 信越半導体株式会社 貼り合わせ用基板の表面欠陥の評価方法
JP2018137278A (ja) * 2017-02-20 2018-08-30 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP7123182B2 (ja) 2018-06-08 2022-08-22 グローバルウェーハズ カンパニー リミテッド シリコン箔層の移転方法
JP6827442B2 (ja) 2018-06-14 2021-02-10 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法及び貼り合わせｓｏｉウェーハ
CN110943066A (zh) * 2018-09-21 2020-03-31 联华电子股份有限公司 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
JP2021190660A (ja) * 2020-06-04 2021-12-13 株式会社Sumco 貼り合わせウェーハ用の支持基板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863659A (en) * 1996-03-28 1999-01-26 Shin-Etsu Handotai Co., Ltd. Silicon wafer, and method of manufacturing the same
US6174740B1 (en) * 1995-09-18 2001-01-16 Shin-Etsu Handotai, Co., Ltd. Method for analyzing impurities within silicon wafer
US20020045329A1 (en) * 1998-10-29 2002-04-18 Mitsubishi Materials Silicon Corporation Dielectrically separated wafer and method of manufacturing the same
US20020068420A1 (en) * 2000-12-01 2002-06-06 Lucent Technologies Inc. Method for making an integrated circuit device with dielectrically isolated tubs and related circuit
CN1539166A (zh) * 2001-07-31 2004-10-20 英特尔公司 含具有集成电路和金刚石层的管芯的电子组件及其制作方法
CN102640278A (zh) * 2009-12-04 2012-08-15 Soitec公司 使电损耗减小的绝缘体上半导体型结构的制造方法及相应的结构
CN103460371A (zh) * 2011-03-22 2013-12-18 Soitec公司 用于射频应用的绝缘型衬底上的半导体的制造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4631804A (en) * 1984-12-10 1986-12-30 At&T Bell Laboratories Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer
US4742020A (en) 1985-02-01 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Multilayering process for stress accommodation in deposited polysilicon
US4897360A (en) 1987-12-09 1990-01-30 Wisconsin Alumni Research Foundation Polysilicon thin film process
JPH0719839B2 (ja) * 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JP2766417B2 (ja) * 1992-02-10 1998-06-18 三菱マテリアル株式会社 貼り合わせ誘電体分離ウェーハの製造方法
KR100218347B1 (ko) * 1996-12-24 1999-09-01 구본준 반도체기판 및 그 제조방법
US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
US6991999B2 (en) * 2001-09-07 2006-01-31 Applied Materials, Inc. Bi-layer silicon film and method of fabrication
US6964880B2 (en) * 2003-06-27 2005-11-15 Intel Corporation Methods for the control of flatness and electron mobility of diamond coated silicon and structures formed thereby
FR2860341B1 (fr) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
JP2007507093A (ja) 2003-09-26 2007-03-22 ユニべルシテ・カトリック・ドゥ・ルベン 抵抗損を低減させた積層型半導体構造の製造方法
US6902977B1 (en) * 2003-10-03 2005-06-07 Advanced Micro Devices, Inc. Method for forming polysilicon gate on high-k dielectric and related structure
JP4730581B2 (ja) * 2004-06-17 2011-07-20 信越半導体株式会社 貼り合わせウェーハの製造方法
WO2007125771A1 (ja) * 2006-04-27 2007-11-08 Shin-Etsu Handotai Co., Ltd. Ｓｏｉウエーハの製造方法
JP5356872B2 (ja) * 2009-03-18 2013-12-04 パナソニック株式会社 個体撮像装置の製造方法
JP5532680B2 (ja) 2009-05-27 2014-06-25 信越半導体株式会社 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
US8815641B2 (en) * 2010-01-29 2014-08-26 Soitec Diamond SOI with thin silicon nitride layer and related methods
US8895435B2 (en) * 2011-01-31 2014-11-25 United Microelectronics Corp. Polysilicon layer and method of forming the same
JP5673170B2 (ja) * 2011-02-09 2015-02-18 信越半導体株式会社 貼り合わせ基板、貼り合わせ基板の製造方法、半導体デバイス、及び半導体デバイスの製造方法
JP2012174884A (ja) * 2011-02-22 2012-09-10 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US9356171B2 (en) * 2012-01-25 2016-05-31 The Trustees Of Dartmouth College Method of forming single-crystal semiconductor layers and photovaltaic cell thereon

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174740B1 (en) * 1995-09-18 2001-01-16 Shin-Etsu Handotai, Co., Ltd. Method for analyzing impurities within silicon wafer
US5863659A (en) * 1996-03-28 1999-01-26 Shin-Etsu Handotai Co., Ltd. Silicon wafer, and method of manufacturing the same
US20020045329A1 (en) * 1998-10-29 2002-04-18 Mitsubishi Materials Silicon Corporation Dielectrically separated wafer and method of manufacturing the same
US20020068420A1 (en) * 2000-12-01 2002-06-06 Lucent Technologies Inc. Method for making an integrated circuit device with dielectrically isolated tubs and related circuit
CN1539166A (zh) * 2001-07-31 2004-10-20 英特尔公司 含具有集成电路和金刚石层的管芯的电子组件及其制作方法
CN102640278A (zh) * 2009-12-04 2012-08-15 Soitec公司 使电损耗减小的绝缘体上半导体型结构的制造方法及相应的结构
CN103460371A (zh) * 2011-03-22 2013-12-18 Soitec公司 用于射频应用的绝缘型衬底上的半导体的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023045129A1 (zh) * 2021-09-22 2023-03-30 苏州华太电子技术股份有限公司 半导体结构的制作方法以及半导体结构

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