CN106165103A - 半导体器件及半导体器件的制造方法 - Google Patents

半导体器件及半导体器件的制造方法 Download PDF

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CN106165103A
CN106165103A CN201580018706.3A CN201580018706A CN106165103A CN 106165103 A CN106165103 A CN 106165103A CN 201580018706 A CN201580018706 A CN 201580018706A CN 106165103 A CN106165103 A CN 106165103A
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CN106165103B (zh
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高谷秀史
斋藤顺
添野明高
山本敏雅
副岛成雅
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Toyota Motor Corp
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Abstract

提供一种能实现更高耐压的半导体器件及其制造方法。所提供的半导体器件具有：p型的第四区，其与栅极沟槽的下端相接；终端沟槽，其在第二区的外侧形成于半导体基板的表面；p型的下端p型区，其与终端沟槽的下端相接；p型的侧面p型区，其与终端沟槽的外周侧的侧面相接，且与下端p型区相连，并在半导体基板的表面露出；p型的多个保护环区，其形成于比侧面p型区靠外周侧处，且在表面露出。

Description

半导体器件及半导体器件的制造方法
技术领域
(关联申请的相互参照)
本申请为2014年4月9日申请的日本专利申请特愿2014-080012号的关联申请，并要求基于该日本专利申请的优先权，且将该日本专利申请所记载的全部内容作为构成本说明书的内容而进行援用。
本说明书公开的技术涉及一种半导体器件。
背景技术
日本专利公开第2013-191734号公报中公开的半导体器件具有MOSFET和形成于MOSFET周围的多个终端沟槽。各终端沟槽环状延伸以将形成有MOSFET的区域包围。在各终端沟槽内，配置有绝缘层。此外，在与各终端沟槽的底面相接的范围内的半导体层，形成有p型浮置区。在MOSFET截止时，耗尽层从MOSFET的体区(body region)向外周侧(形成有终端沟槽的区域)延伸。当耗尽层延伸到最内侧的终端沟槽的下侧的p型浮置区时，耗尽层从该p型浮置区进一步向外周侧延伸。由此，当耗尽层延伸到相邻的p型浮置区时，耗尽层从该p型浮置区进一步延伸到外周侧。这样，耗尽层在经过各p型浮置区的同时在形成有MOSFET的区域的周围大幅扩展。由此，能提高半导体器件的耐压。
发明内容
发明要解决的问题
近年来，对于上述类型的半导体器件的耐压的要求正逐步提高。以往，上述p型浮置区通过在形成终端沟槽后向终端沟槽的底面注入p型杂质、然后使注入的p型杂质在半导体层内扩散而形成。然而，根据半导体的材料和/或其他制造工序的各种条件，而存在p型杂质的扩散距离变短、且不能使各p型浮置区之间的间隔足够窄的情况。在这样的情况下，难以使耗尽层在该间隔的区域充分地伸展。虽然也可考虑通过使各终端沟槽之间的间隔变窄来使各p型浮置区之间的间隔变窄，但是，因加工精度的问题等而在使各终端沟槽间的间隔变窄方面存在极限。在现有的终端沟槽的结构中，在耐压的提高方面存在极限。因此，在本说明书中，公开能实现更高耐压的半导体器件。
用于解决问题的手段
本说明书提供一种半导体器件，具有半导体基板、表面电极以及背面电极，对所述表面电极和所述背面电极之间进行通断切换，所述表面电极形成于所述半导体基板的表面，所述背面电极形成于所述半导体基板的背面。所述半导体基板具有：n型的第一区，其与所述表面电极相接；p型的第二区，其与所述表面电极相接，且与所述第一区相接；n型的第三区，其配置于所述第二区的下侧，且利用所述第二区而与所述第一区分离；栅极沟槽，其从所述表面贯穿所述第一区及所述第二区而到达所述第三区；p型的第四区，其与所述栅极沟槽的下端相接；终端沟槽，其在所述第二区的外侧形成于所述表面；p型的下端p型区，其与所述终端沟槽的下端相接；p型的侧面p型区，其与所述终端沟槽的外周侧的侧面相接，且与所述下端p型区相连，并在所述表面露出；p型的多个保护环区，其形成于比所述侧面p型区靠外周侧处，且在所述表面露出；以及n型的外周n型区，其形成于比所述终端沟槽靠外周侧处，且与所述第三区相连，并将所述侧面p型区与所述多个保护环区分离，将所述多个保护环区互相分离。
再有，在本说明书中，外周侧意指从第二区远离一侧。
在该半导体器件中，由第一区、第二区、第三区、和第四区形成开关元件。在开关元件截止时，耗尽层从第二区扩展到第三区内。在耗尽层到达栅极沟槽的下端时，耗尽层到达第四区。于是，耗尽层也从第四区扩展到第三区内。由此，能确保形成了开关元件的区域的耐压。另外，在从第二区扩展到第三区内的耗尽层到达终端沟槽的下端时，耗尽层到达下端p型区。于是，耗尽层从下端p型区及侧面p型区延伸到外周n型区内。在从侧面p型区延伸的耗尽层到达侧面p型区的相邻的保护环区时，耗尽层进一步从该保护环区向相邻的保护环区延伸。耗尽层经由各保护环区向外周侧扩展。由此，耗尽层在外周侧的区域大幅伸展，能确保耐压。这样，在该半导体器件中，通过在半导体基板的表面露出的保护环，能促进耗尽层的伸展。另外，由于保护环区形成于在半导体基板的表面露出的范围内，因此，能高精度地形成。因此，能容易地缩小保护环区之间的间隔。因此，在该半导体器件中，能由保护环区来确保足够的耐压。
附图说明
图1是实施例1的半导体器件10的俯视图。
图2是图1中II-II线的纵剖视图。
图3是实施例1的半导体器件10的制造工序的说明图。
图4是实施例1的半导体器件10的制造工序的说明图。
图5是实施例1的半导体器件10的制造工序的说明图。
图6是实施例1的半导体器件10的制造工序的说明图。
图7是实施例2的半导体器件的俯视图。
图8是图7中VIII-VIII线的纵剖视图。
图9是实施例2的半导体器件的制造工序的说明图。
图10是实施例2的半导体器件的制造工序的说明图。
图11是实施例2的半导体器件的制造工序的说明图。
图12是实施例3的半导体器件的俯视图。
图13是图12中XIII-XIII线的纵剖视图。
图14是图12中XIV-XIV线的纵剖视图。
具体实施方式
下面对以下说明的实施例的特征进行列举。再有，以下的特征皆为能独立发挥作用的特征。
(特征1)终端沟槽的宽度比栅极沟槽的宽度大。
(特征2)下端p型区和侧面p型区含有Al。
(特征3)在第二区(体区26)和终端沟槽之间的表面，形成有分离沟槽。在与分离沟槽的下端相接的位置处，形成有p型的第五区(p型浮置区103)。在终端沟槽和分离沟槽之间，形成有与终端沟槽的内周侧的侧面相接、与下端p型区相连、并在表面露出的p型的第六区(侧面p型区108)。分离沟槽将第二区和第六区分离。再有，在本说明书中，内周侧意指靠近第二区的一侧。
(特征4)终端沟槽具有：第一沟槽；第二沟槽，其形成于比第一沟槽靠外周侧处；和第三沟槽，其将第一沟槽和第二沟槽连接。侧面p型区与第二沟槽的外周侧的侧面相接。下端p型区与第一沟槽、第二沟槽及第三沟槽的下端相接。
(特征5)
还具有将终端沟槽的内周侧的侧面、底面及外周侧的侧面覆盖的绝缘膜。在将内周侧的侧面覆盖的绝缘膜和将外周侧的侧面覆盖的绝缘膜之间，形成有未填充绝缘膜的区域。
(特征6)
制造半导体器件的方法包括：在半导体基板形成终端沟槽的工序；和通过沿着相对于半导体基板的表面倾斜的方向对终端沟槽的侧面和底面注入p型杂质来形成下端p型区和侧面p型区的工序。
实施例1
如图1所示，实施例1涉及的半导体器件10具有由SiC(碳化硅)形成的半导体基板12。半导体基板12具有MOSFET区20和外周区50。在MOSFET区20，形成有MOSFET(金属-氧化物半导体场效应晶体管)。再有，在图1中，考虑到图的易于观看性，而在MOSFET区20仅表示了栅极沟槽34。外周区50为MOSFET区20外侧的区域。在本实施例中，外周区50为MOSFET区20和半导体基板12的端面12a之间的区域。在外周区50，形成有耐压结构。再有，在图1中，考虑到图的易于观看性，而在外周区50内仅表示了终端沟槽54和保护环区(guard ring region)64。
如图2所示，在MOSFET区20内，形成有源极区22、体区26、漂移区(drift region)28a、28b、漏极区30、p型浮置区32、栅极沟槽34、源电极36、以及漏电极38。
源电极36形成于MOSFET区20内的半导体基板12的上表面72。
漏电极38形成于半导体基板12的下表面。
源极区22在MOSFET区20内形成有多个。源极区22是含有高浓度的n型杂质的n型区域。源极区22形成于在半导体基板12的上表面露出的范围内。源极区22与源电极36导通。
体区26形成于源极区22的侧面以及下侧，并与源极区22相接。体区26是p型区。体区26在未形成源极区22的位置处露出于半导体基板12的上表面。体区26与源电极36导通。
漂移区28a是含有低浓度的n型杂质的n型区。漂移区28a的n型杂质比源极区22的n型杂质浓度低。漂移区28a形成于体区26的下侧。漂移区28a与体区26相接，并利用体区26而与源极区22分离。
漏极区30是含有高浓度的n型杂质的n型区。漏极区30的n型杂质浓度比漂移区28a的n型杂质浓度高。漏极区30形成于漂移区28a的下侧。漏极区30与漂移区28a相接，并利用漂移区28a而与体区26分离。漏极区30形成于在半导体基板12的下表面露出的范围内。漏极区30与漏电极38导通。
栅极沟槽34在MOSFET区20内形成有多个。栅极沟槽34是在半导体基板12的上表面72形成的槽。各栅极沟槽34贯穿源极区22和体区26，并到达漏极区28。如图1所示，多个栅极沟槽34互相平行地延伸。如图2所示，在各栅极沟槽34内，形成有底部绝缘层34a、栅极绝缘膜34b、和栅电极34c。底部绝缘层34a是在栅极沟槽34的底部形成的厚绝缘层。底部绝缘层34a的上侧的栅极沟槽34的侧面由栅极绝缘膜34b覆盖。在底部绝缘层34a的上侧的栅极沟槽34内，形成有栅电极34c。栅电极34c隔着栅极绝缘膜34b而与源极区22、体区26及漂移区28a对置。栅电极34c利用栅极绝缘膜34b及底部绝缘层34a而与半导体基板12绝缘。栅电极34c的上表面由绝缘层34d覆盖。
p型浮置区32形成于半导体基板12内的、与各栅极沟槽34的底面(即、下端)相接的范围内。p型浮置区32的范围被漂移区28包围。各p型浮置区32利用漂移区28而互相分离。另外，各p型浮置区32利用漂移区28而与体区26分离。
漂移区28b形成于外周区50内。漂移区28b是与漂移区28a连续的n型区，且具有与漂移区28a大体相同的n型杂质浓度。在下面，有时将漂移区28a和漂移区28b统称为漂移区28。在漂移区28b的下侧，形成有上述漏极区30。即、漂移区28和漏极区30从MOSFET区20跨及外周区50地形成。漂移区28和漏极区30扩展至半导体基板12的端面12a。此外，漏电极38形成于包括外周区50在内的半导体基板12的整个下表面。另外，外周区50内的半导体基板12的上表面72由绝缘膜70覆盖。
在外周区50内的半导体基板12的表面72，形成有终端沟槽54。终端沟槽54的内周侧的侧面55b、底面及外周侧的侧面55a由绝缘膜70覆盖。但是，终端沟槽54内没有完全被绝缘膜70填充，在将内周侧的侧面55b覆盖的绝缘膜70和将外周侧的侧面55a覆盖的绝缘膜70之间形成有间隙(空间)70a。再有，在间隙70a内，也可填充与绝缘膜70不同的物质。终端沟槽54形成于与体区26相邻的位置。终端沟槽54具有与栅极沟槽34大体相同的深度。如图1所示，在俯视观察半导体基板12的表面72时，终端沟槽54绕MOSFET区20的周围延伸一圈。因此，体区26利用终端沟槽54而与外周区50内的任一p型区分离。这样，由于比终端沟槽54靠外周侧的p型区不与源电极36导通，因此比终端沟槽54靠外周侧的p型区不是体区26。即、终端沟槽54形成于体区26的外侧。
如图2所示，在与终端沟槽54的下端(即、底面)相接的位置处，形成有下端p型区60。此外，在与终端沟槽54的外周侧的侧面55a相接的位置处，形成有侧面p型区62。侧面p型区62从表面72延伸到下端p型区60。即、侧面p型区62在表面72露出，并且与下端p型区60相连。由于下端p型区60和侧面p型区62是连续的一个p型区，因此在下面有时将两者统称为边界部p型区59。边界部p型区59含有Al来作为p型杂质。边界部p型区59除了不可控制的误差等级之外不含有Al以外的p型杂质。边界部p型区59形成为沿终端沟槽54绕MOSFET区20的周围一圈。边界部p型区59利用漂移区28而与体区26分离。
在侧面p型区62的外周侧，形成有多个保护环区64。各保护环区64是p型区，且形成于在表面72露出的范围内。各保护环区64仅形成于浅范围内。因此，各保护环区64的下端位于比侧面p型区62的下端靠上侧(表面72侧)处。在各保护环区64的下侧，形成有漂移区28b。在最内周侧(MOSFET区20侧)的保护环区64和侧面p型区62之间，形成有漂移区28b。由漂移区28b，而将最内周侧的保护环区64与侧面p型区62分离。此外，在各保护环区64之间，形成有漂移区28b。由漂移区28b，而将各保护环区64互相分离。各保护环区64含有Al作为p型杂质。各保护环区64除了不可控制的误差等级之外不含有Al以外的p型杂质。
接着，对半导体器件10的工作进行说明。在使半导体器件10工作时，在漏电极38和源电极36之间施加漏电极38为正的电压。进而，通过对栅电极34c施加栅极导通电压，而使MOSFET区20内的MOSFET导通。即、在与栅电极34c对置的位置的体区26形成沟道，电流从源电极36经源极区22、沟道、漂移区28、漏极区30而流向漏电极38。在停止向栅电极34c施加栅极导通电压时，沟道消失，MOSFET截止。在MOSFET截止时，耗尽层从体区26和漂移区28的边界部的pn结扩展到漂移区28内。在耗尽层到达MOSFET区20内的p型浮置区32时，耗尽层也从p型浮置区32向漂移区28内扩展。由此，能有效地使两个p型浮置区32之间的漂移区28耗尽。因此，能抑制MOSFET区20内的电场集中。由此，能实现MOSFET区20内的高耐压。
另外，从上述pn结延伸的耗尽层如图2的箭头82所示那样也到达终端沟槽54的下侧的边界部p型区59。于是，耗尽层从边界部p型区59扩展到漂移区28内。栅极沟槽34和终端沟槽54之间的漂移区28因从栅极沟槽34的下侧的p型浮置区32扩展的耗尽层和从终端沟槽54的下侧的边界部p型区59(即、下端p型区60)扩展的耗尽层而耗尽。此时，由于栅极沟槽34的深度和终端沟槽54的深度大体相等(即、p型浮置区32的深度方向的位置和下端p型区60的深度方向的位置大体相等)，因此，在栅极沟槽34和终端沟槽54之间的漂移区28中，等电位线沿横向(与表面72平行的方向)延伸。由此，能抑制终端沟槽54附近的电场集中。
另外，边界部p型区59从终端沟槽54的下端扩展到半导体基板12的表面72。因此，在表面72的附近，耗尽层从边界部p型区59向最内周侧的保护环区64扩展。在耗尽层到达最内周侧的保护环区64时，耗尽层从该保护环区64向其相邻的保护环区64伸展。这样，耗尽层依次经由各保护环区64而向外周侧扩展。因此，耗尽层在外周区50内大幅伸展。由此，能实现外周区50内的高耐压。
这样，在半导体器件10中，通过将终端沟槽54的下侧的边界部p型区59设置于与p型浮置区32同样深度的位置，从而能抑制MOSFET区20的外周端附近处的电场集中。另外，通过在比终端沟槽54靠外周侧处，边界部p型区59从终端沟槽54的底面延伸到半导体基板12的表面72，从而使耗尽层能到达仅在表面72附近的浅范围内形成的保护环区64。结果，能由多个保护环区64来促进外周区50中的耗尽层的伸展。另外，由于各保护环区64互相分离，因此能使电位在外周区50内较均等地分布。因此，能实现外周区50的高耐压。
接着，对半导体器件10的制造方法进行说明。再有，由于该制造方法的特征在于具有形成外周区50的工序，因此，在下面对形成外周区50的工序进行说明，且对形成MOSFET区20的工序省略说明。
首先，如图3所示，准备已形成有体区26和漂移区28的半导体基板12。接着，通过向半导体基板12的表面72中的与保护环区64相当的范围进行离子注入，而注入Al(p型杂质)。此处，通过将Al的注入能量设定得较低，而仅在半导体基板12的表面72附近的浅范围内注入Al。这样，在离子的注入深度浅时，能高精度地控制其注入范围。
接着，如图4所示，通过有选择地蚀刻半导体基板12的表面72，而形成终端沟槽54。终端沟槽54形成于与体区26相邻的位置。
接着，如图5所示，通过离子注入而对终端沟槽54注入Al。该离子注入在将表面72及终端沟槽54的内周侧的侧面55b进行遮蔽以使得不会被注入Al之后进行。此处，通过使离子注入的方向相对于半导体基板12的表面72倾斜，而向终端沟槽54的底面和外周侧的侧面55a注入Al。
接着，通过将半导体基板12退火，而使注入半导体基板12的Al活性化。由此，如图6所示，形成保护环区64、下端p型区60及侧面p型区62。
接着，如图2所示，在表面72及终端沟槽54的内表面形成绝缘膜70。由于终端沟槽54的宽度大，因此，终端沟槽54没有由绝缘膜70完全填充。即、在将内周侧的侧面55b覆盖的绝缘膜70与将外周侧的侧面55a覆盖的绝缘膜70之间，形成间隙70a。由此，外周区50完成。再有，在间隙70a，可在随后的工序中埋入与绝缘膜70不同的材料。
如上所述，在该制造方法中，通过对终端沟槽54的外周侧的侧面55a进行倾斜离子注入而形成侧面p型区62。根据向侧面55a的离子注入深度，能控制侧面p型区62的宽度(半导体器件12的横向(图2的横向)的尺寸)。由于能高精度地控制向侧面55a的离子注入深度，因此，根据该制造方法，能准确地控制侧面p型区62的宽度。因此，能形成宽度窄的侧面p型区62。另外，侧面p型区62通过Al的离子注入来形成。由于Al在SiC中的扩散系数小，因此，在上述退火时Al的扩散距离小。通过如上述那样使用Al来作为p型杂质，能使侧面p型区62的宽度更小。这样，根据上述制造方法，能高精度地形成宽度窄的侧面p型区62。
另外，保护环区64通过向表面72附近的浅范围进行离子注入而形成。通过向浅范围的离子注入，能准确地控制离子注入范围。因此，能形成宽度窄的保护环区64。另外，保护环区64通过Al的离子注入而形成。由此，能使保护环区64的宽度更小。这样，根据上述方法，能高精度地形成宽度窄的保护环区64。
此外，由于能如上述那样高精度地形成保护环区64和侧面p型区62，因此，根据该方法，能使侧面p型区62和保护环区64之间的间隔及各保护环区64之间的间隔狭小化。因此，根据该方法，能使耗尽层可靠地伸展到外周区50，能实现外周区50的高耐压。此外，根据该方法，能减小外周区50的面积，能制造小型的半导体器件10。
实施例2
图7、8所示的实施例2的半导体器件在体区26和终端沟槽54之间的表面72形成有分离沟槽102。在分离沟槽102内，埋入有绝缘层104。如图7所示，分离沟槽102形成为绕MOSFET区20的周围一圈。如图8所示，在与分离沟槽102的下端相接的位置，形成有p型浮置区103。p型浮置区103形成为沿分离沟槽102而绕MOSFET区20的周围一圈。在分离沟槽102的外周侧，形成有p型区106。p型区106形成于在半导体基板12的表面72露出的范围内。p型区106的表面72由绝缘膜70覆盖。因此，p型区106不与源电极36接触。分离沟槽102使p型区106与体区26分离。此外，在第二实施例的半导体器件中，沿终端沟槽54的内周侧的侧面55b而形成有侧面p型区108。侧面p型区108从p型区106延伸到下端p型区60。侧面p型区108与p型区106相连，并且与下端p型区60相连。侧面p型区108含有Al来作为p型杂质。实施例2的半导体器件的其他构成与实施例1的半导体器件的构成相同。
接着，对实施例2的半导体器件的外周区50中的耗尽层的扩展方式进行说明。在MOSFET截止时，如图8的箭头112所示，耗尽层从体区26和漂移区28的边界部的pn结到达分离沟槽102的下侧的p型浮置区103。于是，耗尽层从p型浮置区103如箭头114所示那样延伸。该耗尽层到达下端p型区60或侧面p型区108。于是，耗尽层从p型区106、侧面p型区108、下端p型区60及侧面p型区62整体扩展到这些区周围的漂移区28内。因此，在表面72附近，耗尽层从侧面p型区62向最内周侧的保护环区64扩展。在耗尽层到达最内周侧的保护环区64时，耗尽层从该保护环区64向其相邻的保护环区64伸展。这样，耗尽层依次经由各保护环区64向外周侧扩展。因此，耗尽层在外周区50内伸展。由此，能实现外周区50内的高耐压。
接着，对实施例2的半导体器件的制造方法(形成外周区50的工序)进行说明。首先，与实施例1同样，如图4所示那样加工半导体基板12。接着，通过与实施例1同样的倾斜离子注入来对终端沟槽54注入Al。但是，在实施例2中，在倾斜离子注入中没有将终端沟槽54的内周侧的侧面55b遮蔽。因此，在向图7的下侧的终端沟槽54a的内周侧的侧面55a注入Al时，也向图7的上侧的终端沟槽54b的内周侧的侧面55b注入Al，并且在向图7的上侧的终端沟槽54b的内周侧的侧面55a注入Al时，也向图7的下侧的终端沟槽54a的内周侧的侧面55b注入Al。因此，在实施例2中，如图9所示，向终端沟槽54的两侧的侧面注入Al。
接着，通过使半导体基板12退火，使向半导体基板12注入的Al活性化。由此，如图10所示，形成保护环区64、侧面p型区108、下端p型区60及侧面p型区62。即、在实施例2中，由于向终端沟槽54的内周侧的侧面55b注入Al，因此沿该内周侧的侧面55b形成侧面p型区108。
接着，如图11所示，通过有选择地蚀刻半导体基板12的表面72，而在终端沟槽54的内周侧的表面72形成分离沟槽102。由此，与终端沟槽54相邻的p型区106与体区26分离。接着，通过向分离沟槽102的底面进行离子注入，而形成p型浮置区103。接着，在分离沟槽102内，形成绝缘层104。接着，在表面72及终端沟槽54的内表面形成绝缘膜70。绝缘膜70形成为覆盖p型区106的整个表面。由此，能防止p型区106与后形成的源电极36接触。通过以上的工序，而完成图8所示的外周区50。
如上所述，在实施例2中，由于也向终端沟槽54b的内周侧的侧面55b注入Al，因此p型区106和下端p型区60由侧面p型区108连接。因此，为了将该p型区与体区26分离，而形成分离沟槽102。此外，通过在与分离沟槽102的下端相接的位置处形成p型浮置区103，使耗尽层易于向外周区50扩展。
实施例3
在图12～14所示的实施例3的半导体器件中，终端沟槽54的构成包括第一沟槽53a、第二沟槽53b和第三沟槽53c。如图12所示，第一沟槽53a延伸为绕MOSFET区20的周围一圈。第二沟槽53b形成于第一沟槽53a的外周侧的表面72，且延伸为绕第一沟槽53a的周围一圈。第三沟槽53c从内周侧向外周侧延伸。第三沟槽53c的一端与第一沟槽53a连接，第三沟槽53c的另一端与第二沟槽53b连接。如图13、14所示，沟槽53a～53c具有大体相同深度。下端p型区60形成于与沟槽53a～53c的下端相接的位置。下端p型区60沿沟槽53a～53c形成。此外，侧面p型区62形成于与第二沟槽53b的外周侧的侧面55a相接的范围内。但是，侧面p型区62仅形成于第二沟槽53b和第三沟槽53c的连接部处的第二沟槽53b的外周侧的侧面55a，而未形成于其他位置的第二沟槽53b。实施例3的半导体器件的其他构成与实施例1的半导体器件的构成相同。
实施例3的半导体器件在图14的截面中具有与图2所示的实施例1的半导体器件相同的结构。因此，与实施例1同样地，耗尽层向外周区50中扩展。此外，实施例3的半导体器件中，虽然终端沟槽54的形状与实施例1不同，但是，也可用与实施例1同样的工序来制造。在对侧面p型区62的离子注入(Al注入)中，如图14所示，由于在形成第三沟槽53c的部分终端沟槽54的宽度(图14的横向的尺寸)大，因此能向第二沟槽53b的外周侧的侧面55a注入Al。另一方面，在没有形成第三沟槽53c的部分，如图13所示，第一沟槽53a及第二沟槽53b的宽度(图13的横向的尺寸)小，因此几乎不会向外周侧的侧面注入Al。因此，侧面p型区62仅形成于第三沟槽53c和第二沟槽53b的连接部。
以上，对实施例1～3进行了说明。再有，虽然在实施例1～3中，对具有MOSFET的半导体器件进行了说明，但是，也可形成IGBT等其他元件来代替MOSFET。此外，在上述实施例中，半导体基板12由SiC构成，但是，也可使用由Si等其他材质构成的半导体基板。此外，可形成与预定电位连接的p型区来代替上述实施例的p型浮置区32、103。
以上，对本发明的具体示例进行了详细说明，但是这些仅为例示而并不对权利要求的范围进行限定。在权利要求书所记载的技术中包括将以上例示的具体示例进行各种变形、变更的技术。
本说明书或附图中所说明的技术要素为通过单独使用或各种组合而发挥技术作用的要素，并不限定于申请时权利要求记载的组合。此外，本说明书或附图所例示的技术为同时达成多个目的的技术，达成其中一个目的本身便具有技术上的有用性。

Claims (7)

1.一种半导体器件，具有半导体基板、表面电极以及背面电极，对所述表面电极和所述背面电极之间进行通断切换，所述表面电极形成于所述半导体基板的表面，所述背面电极形成于所述半导体基板的背面，所述半导体器件中，
所述半导体基板具有：
n型的第一区，其与所述表面电极相接；
p型的第二区，其与所述表面电极相接，且与所述第一区相接；
n型的第三区，其配置于所述第二区的下侧，且利用所述第二区而与所述第一区分离；
栅极沟槽，其从所述表面贯穿所述第一区及所述第二区而到达所述第三区；
p型的第四区，其与所述栅极沟槽的下端相接；
终端沟槽，其在所述第二区的外侧形成于所述表面；
p型的下端p型区，其与所述终端沟槽的下端相接；
p型的侧面p型区，其与所述终端沟槽的外周侧的侧面相接，且与所述下端p型区相连，并在所述表面露出；
p型的多个保护环区，其形成于比所述侧面p型区靠外周侧处，且在所述表面露出；以及
n型的外周n型区，其形成于比所述终端沟槽靠外周侧处，且与所述第三区相连，并将所述侧面p型区与所述多个保护环区分离，将所述多个保护环区互相分离。
2.根据权利要求1所述的半导体器件，其中，
所述终端沟槽的宽度比所述栅极沟槽的宽度大。
3.根据权利要求1或2所述的半导体器件，其中，
所述下端p型区和所述侧面p型区含有Al。
4.根据权利要求1至3中任一项所述的半导体器件，其中，
在所述第二区与所述终端沟槽之间的所述表面形成有分离沟槽，
在与所述分离沟槽的下端相接的位置形成有p型的第五区，
在所述终端沟槽与所述分离沟槽之间形成有p型的第六区，该第六区与所述终端沟槽的内周侧的侧面相接，且与所述下端p型区相连，并在所述表面露出，
所述分离沟槽将所述第二区和所述第六区分离。
5.根据权利要求1至4中任一项所述的半导体器件，其中，
所述终端沟槽具有第一沟槽、第二沟槽以及第三沟槽，所述第二沟槽形成于比所述第一沟槽靠外周侧处，所述第三沟槽将所述第一沟槽和所述第二沟槽连接，
所述侧面p型区与所述第二沟槽的外周侧的侧面相接，
所述下端p型区与所述第一沟槽、所述第二沟槽及所述第三沟槽的下端相接。
6.根据权利要求1至5中任一项所述的半导体器件，其中，
还具有绝缘膜，该绝缘膜将所述终端沟槽的内周侧的侧面、底面及外周侧的侧面覆盖，
在将内周侧的侧面覆盖的所述绝缘膜与将外周侧的侧面覆盖的所述绝缘膜之间，形成有未填充绝缘膜的区域。
7.一种半导体器件的制造方法，制造权利要求1至6中任一项所述的半导体器件，该制造方法包括：
在半导体基板形成所述终端沟槽的工序；和
通过沿着相对于所述半导体基板的表面倾斜的方向对所述终端沟槽的侧面和底面注入p型杂质，从而形成所述下端p型区和所述侧面p型区的工序。
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US9853139B2 (en) 2017-12-26
DE112015001751T5 (de) 2017-02-09
WO2015156024A1 (ja) 2015-10-15
US20170018643A1 (en) 2017-01-19
DE112015001751B4 (de) 2021-03-18

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