CN105849879A - 半导体装置的制造方法和热固性树脂片 - Google Patents

半导体装置的制造方法和热固性树脂片 Download PDF

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Publication number
CN105849879A
CN105849879A CN201480070680.2A CN201480070680A CN105849879A CN 105849879 A CN105849879 A CN 105849879A CN 201480070680 A CN201480070680 A CN 201480070680A CN 105849879 A CN105849879 A CN 105849879A
Authority
CN
China
Prior art keywords
resin sheet
thermosetting resin
chip
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480070680.2A
Other languages
English (en)
Chinese (zh)
Inventor
盛田浩介
石坂刚
石井淳
志贺豪士
饭野智绘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2013270095A external-priority patent/JP2015126124A/ja
Priority claimed from JP2014098068A external-priority patent/JP2015216229A/ja
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of CN105849879A publication Critical patent/CN105849879A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
CN201480070680.2A 2013-12-26 2014-12-22 半导体装置的制造方法和热固性树脂片 Pending CN105849879A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2013-270095 2013-12-26
JP2013270095A JP2015126124A (ja) 2013-12-26 2013-12-26 半導体パッケージの製造方法
JP2014098068A JP2015216229A (ja) 2014-05-09 2014-05-09 半導体装置の製造方法及び熱硬化性樹脂シート
JP2014-098068 2014-05-09
PCT/JP2014/083910 WO2015098838A1 (ja) 2013-12-26 2014-12-22 半導体装置の製造方法及び熱硬化性樹脂シート

Publications (1)

Publication Number Publication Date
CN105849879A true CN105849879A (zh) 2016-08-10

Family

ID=53478692

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480070680.2A Pending CN105849879A (zh) 2013-12-26 2014-12-22 半导体装置的制造方法和热固性树脂片

Country Status (4)

Country Link
KR (1) KR20160101962A (ja)
CN (1) CN105849879A (ja)
TW (1) TW201533808A (ja)
WO (1) WO2015098838A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571197A (zh) * 2019-08-07 2019-12-13 广东芯华微电子技术有限公司 一种多芯片嵌入式abf封装结构及其制造方法
CN110581109A (zh) * 2019-08-07 2019-12-17 广东芯华微电子技术有限公司 一种多芯片嵌入式异构封装结构及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107924886A (zh) * 2015-09-02 2018-04-17 日立化成株式会社 树脂组合物、固化物、密封用膜及密封结构体
KR102313698B1 (ko) * 2017-09-01 2021-10-15 매그나칩 반도체 유한회사 유연성 있는 반도체 패키지 및 이의 제조 방법
WO2019065309A1 (ja) * 2017-09-28 2019-04-04 株式会社新川 ボンディングの際の半導体チップの加熱条件設定方法及び非導電性フィルムの粘度測定方法ならびにボンディング装置
WO2022163763A1 (ja) * 2021-02-01 2022-08-04 ナガセケムテックス株式会社 電子部品実装基板の封止方法および熱硬化性シート

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9200920D0 (en) 1992-01-16 1992-03-11 Lucas Ind Plc Method of and an apparatus for misfire and rough road detection
JP5435685B2 (ja) * 2007-02-28 2014-03-05 ナミックス株式会社 封止用樹脂フィルム
JP2010109246A (ja) * 2008-10-31 2010-05-13 Yaskawa Electric Corp 半導体装置および半導体装置の製造方法
JP2010263199A (ja) * 2009-04-07 2010-11-18 Furukawa Electric Co Ltd:The 半導体装置の製造方法および半導体装置
JP2011148959A (ja) * 2010-01-25 2011-08-04 Kyocera Chemical Corp 半導体封止用樹脂シートおよび樹脂封止型半導体装置
JP5334135B2 (ja) * 2010-08-20 2013-11-06 ニチゴー・モートン株式会社 積層装置
JP5349432B2 (ja) * 2010-09-06 2013-11-20 日東電工株式会社 電子部品装置の製法およびそれに用いる電子部品封止用樹脂組成物シート
JP5189194B2 (ja) * 2011-09-05 2013-04-24 ミカドテクノス株式会社 真空加熱接合装置及び真空加熱接合方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571197A (zh) * 2019-08-07 2019-12-13 广东芯华微电子技术有限公司 一种多芯片嵌入式abf封装结构及其制造方法
CN110581109A (zh) * 2019-08-07 2019-12-17 广东芯华微电子技术有限公司 一种多芯片嵌入式异构封装结构及其制造方法

Also Published As

Publication number Publication date
KR20160101962A (ko) 2016-08-26
WO2015098838A1 (ja) 2015-07-02
TW201533808A (zh) 2015-09-01

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WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160810

WD01 Invention patent application deemed withdrawn after publication