CN105706224A - 通过将扩散区设计为钎焊连接部的扩散钎焊方法和带这种钎焊连接部的电子组件 - Google Patents
通过将扩散区设计为钎焊连接部的扩散钎焊方法和带这种钎焊连接部的电子组件 Download PDFInfo
- Publication number
- CN105706224A CN105706224A CN201480053472.1A CN201480053472A CN105706224A CN 105706224 A CN105706224 A CN 105706224A CN 201480053472 A CN201480053472 A CN 201480053472A CN 105706224 A CN105706224 A CN 105706224A
- Authority
- CN
- China
- Prior art keywords
- contact surface
- solder
- installed surface
- substrate
- components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29034—Disposition the layer connector covering only portions of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/3001—Structure
- H01L2224/3003—Layer connectors having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/30104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
- H01L2224/3011—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the layer connectors being bonded to at least one common bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3012—Layout
- H01L2224/3013—Square or rectangular array
- H01L2224/30131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3012—Layout
- H01L2224/3013—Square or rectangular array
- H01L2224/30134—Square or rectangular array covering only portions of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3012—Layout
- H01L2224/30177—Combinations of arrays with different layouts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
- H01L2224/32058—Shape in side view being non uniform along the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
- H01L2224/32059—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32501—Material at the bonding interface
- H01L2224/32503—Material at the bonding interface comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/33104—Disposition relative to the bonding areas, e.g. bond pads
- H01L2224/33106—Disposition relative to the bonding areas, e.g. bond pads the layer connectors being bonded to at least one common bonding area
- H01L2224/33107—Disposition relative to the bonding areas, e.g. bond pads the layer connectors being bonded to at least one common bonding area the layer connectors connecting two common bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8382—Diffusion bonding
- H01L2224/83825—Solid-liquid interdiffusion
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
本发明涉及一种扩散钎焊方法,其中将电子元器件(13)放置在衬底(12)上。在此,接合表面设计成,使得在接合缝(21)的区域内形成空腔(20、27)。这可以例如通过在元器件(13)的安装面(18)中和/或在衬底(12)的接触面(14)中设置凹槽来确保,所述凹槽(27)为碗状或有利地为环绕柱状结构元件(22)的通道(20),所述结构元件(22)的端面形成用于连接的安装面(18)和/或接触面(14)。空腔(20、27)的优点在于,当将元器件(13)放置在衬底(12)的接触面(14)上时焊料(19)会漏到空腔(20、27)中,以达到接合缝(21)的所需宽度。因此接合缝(21)可选成这样窄,使得该接合缝在钎焊时借助桥接接合缝(21)的扩散区(24)形成,该扩散区例如由金属间化合物构成。有利地即使在利用标准焊料的情况下也以这样的方式形成扩散焊连接。本发明进一步涉及一种以所述方法制造的电子组件(11)。
Description
技术领域
本发明涉及一种用于在衬底上扩散钎焊电子元器件的方法。在该方法中,将元器件以其安装面放置在衬底接触面上,其中在衬底与元器件之间施加焊料。随后将焊料加热到引发焊料与元器件之间以及焊料与衬底之间的扩散过程的温度,其中形成钎焊连接部。在此,化学元素从元器件和衬底扩散到所形成的钎焊连接部中,其中在该钎焊连接部中化学成分改变了。严格地说,化学元素从为此提供的金属镀层扩散到钎焊连接部中。元器件和衬底上的这些金属镀层在本发明的意义上被理解为元器件和衬底的一部分。
背景技术
优选液化焊料,因为由此能够极大地加速在焊料中的扩散过程。另外则还存在足够高的温度,从而引发元器件和衬底中的扩散过程。更准确地说,在构成接触面和安装面的接触材料中引发该扩散过程,其中,这些接触材料在本发明的意义中分别要理解为该元器件的部分和该衬底的一部分。
所形成的钎焊连接部具有桥接所述接触面与安装面之间的间隙的扩散区。在此,该扩散区是来自接触材料的材料所扩散入的区域,从而形成与焊料、即原料相比更高熔化温度的材料。当接触材料含铜时,该扩散区可以在含锡的焊料的情况下例如通过铜和锡之间的金属间化合物而形成。该金属间化合物的熔点约420℃,明显高于相应的锡基焊料。
本发明还涉及一种电子组件,该电子组件包含带有接触面的衬底,带有安装面的电子元器件钎焊在该接触面上。钎焊连接部具有桥接所述接触面和安装面之间的间隙的扩散区。该扩散区以上文已经描述的方式形成。例如,该扩散区可以由金属间化合物构成。另外,该钎焊连接部也可具有由凝固的焊料构成的区域。所述由凝固的焊料构成的区域通常与接触面和安装面的距离为,使得接触材料不能从那里进入钎焊连接部的这些部分中。
电子组件和用于在这样的电子组件中形成扩散钎焊连接部的方法例如在DE102012214901A1中得以描述。所建议的是,将所谓的半导体装置如半导体芯片用扩散钎焊层固定在经烧结的银层上。在此由银膏制成经烧结的银层,在该银层上施加焊料。扩散钎焊工艺在于,在所述两个层之间发生材料的扩散,由此形成扩散区。因此,出于形成扩散区的目的,有必要施加不同的材料,其中在所述焊料之间的扩散有助于形成扩散区和因此桥接待钎焊的构件之间的焊接缝。
发明内容
本发明要解决的技术问题在于,提供一种用于扩散钎焊的方法和一种电子组件,该电子组件具有至少一个经扩散钎焊的钎焊连接部,在所述钎焊连接部中所形成的扩散钎焊点能够以低廉的元器件和以大的运行可靠性来制造。
根据本发明,该技术问题通过前述方法解决的方式是,元器件的安装面和/或衬底的接触面设有凹槽,该凹槽在钎焊连接部形成之后位于桥接所述接触面与安装面之间的间隙的扩散区以外。
作为替代方案,该技术问题也可通过前述类型的电子组件解决的方式是,元器件的安装面和/或衬底的接触面设有凹槽,该凹槽位于桥接所述接触面与安装面之间的间隙的扩散区以外。换言之,电子组件是能借助前述方法制造的产品。因此,只要在接下来描述的方法特征中直接涉及所制造的电子组件的结构,这些方法特征就也能够转用到该电子组件上。
根据本发明的使用在接触面和/或安装面中的凹槽具有以下优点,当将元器件放置在衬底上时,该凹槽可用作焊料的缓冲腔。在此必须考虑的是,在形成钎焊连接时在安装面和接触面与焊料的边界面上形成的扩散区保持被限于特定的距离,因为来自接触材料的元素必须以特定浓度存在于焊料中,从而例如通过形成金属间化合物而形成扩散区。然而这意味着当存在太大的间隙时,在钎焊连接部中形成的、分别基于安装面和接触面的扩散区不会碰到上。因此,不会形成桥接间隙的、对于钎焊连接的机械和热稳定性具有重要意义的扩散区。现在如现有技术中所述,应对不会形成这种扩散区的方式是,在焊料的提供用于扩散的材料之间制造具有提供用于扩散的材料的层。然而,这带来根据本发明要解决的技术问题恰恰应当节省的额外制造成本。
另一方面,困难的是,施加到接合配对件上的焊料厚度薄到,使得由所焊料的施加而产生的间隙足够窄,以便能够通过所形成的扩散区来桥接该间隙。在此,制造公差起着作用,所述制造公差导致这样薄的焊料层不会到处都同样厚并且因此在某些区域内不会形成接触。本发明通过设置凹槽来解决不会形成接触这一问题。由此实现了焊料可以以足够的厚度施加,其中在接合配对件(元器件和衬底)靠近时多余的焊料可被挤入凹槽中(这可通过沿元器件的放置方向施加单轴接合力来辅助)。在此,在接触面与安装面之间的凹槽以外的区域中出现可靠的焊料施加。在此,元器件可以这样靠近衬底,使得所产生的接合缝足够窄,从而可以通过钎焊工艺形成桥接所述接合缝(间隙)的扩散区。
所述凹槽是否设于安装面或接触面上或在这两个面上均设置凹槽这一点并不重要。在任何情况下,凹槽均与形成接合缝的间隙邻接并且能够以该方式填充以多余的焊料。与凹槽邻接的安装面或接触面可设计成优选平面。在该情况下能够简单地制造安装面或接触面并且有利地形成具有简单几何结构的间隙。然而也可能的是,安装面和/或接触面是弯曲的。在该情况下向凹槽的过渡也可设计成光滑的。在该情况下,凹槽处于接触面和安装面的间距较大的区域,而形成接合缝的间隙处于安装面和接触面之间的间距被减小到能够通过扩散区桥接该距离的程度的区域。
凹槽能够彼此分开地设置,这导致安装面和/或接触面可以设计成连续的。凹槽例如可为碗状。备选地还可能的是,这些凹槽形成连续的结构,从而安装面和/或接触面单独地以岛状的结构存在。
为了多余的焊料能够可靠地挤入凹槽中,根据本发明的一种设计可以规定,凹槽占元器件的安装面和/或衬底的接触面的面积百分比为50%以上,优选地为70%以上。由结构元件提供的剩余表面选择为,使其仍然足以形成机械稳定的扩散钎焊连接部。凹槽同时提供足以容纳多余焊料的大容积。
根据本发明的一种有利的设计方案规定,凹槽具有通道的形式。这些通道可以是环绕安装面和/或接触面的表面元器件或者还可以是交叉布置的。通道的深度确定了可容纳的焊料的量。要注意的还有,在钎焊过程期间(取决于例如焊料粘合剂的蒸发)所形成的气体可经由通道漏出。尤其有利的是,通道环绕柱状结构元件,其中结构元件的端面形成了用于高熔点连接(扩散区)的安装面或接触面。所述柱不一定必须具有圆形横截面。它们也可以设成椭圆形或矩形横截面。因此,术语“柱”在本发明的意义中要理解为最宽泛的意义。这些通道不必具有同样的宽度。它们可以设成优选线性的,其中这有利地能够实现特别简单的形成通道。然而,这些通道也可以弯曲地延伸或者环绕柱状结构元件。
按照本发明的一种特别的设计方案,焊料以这样的量设于元器件与衬底之间,使得将凹槽完全用焊料填充。在此形成了钎焊连接部,该钎焊连接部仅在接触面和安装面形成了构成接合缝的间隙的区域中形成桥接式扩散区。在完全被焊料填充的这些凹槽的区域中,由焊料形成常规的钎焊连接部。如果这样的复合连接部例如在元器件运行中被加热,则由于具有升高熔点的扩散区即使在较高温度下也确保了钎焊连接部的机械强度。也适用的是,由钎焊合金形成的钎焊连接部的一部分软化并且不再承经受机械要求。然而在这些区域中的焊料能够继续用于传输电流,由此有利地提供了较大的导电横截面。
根据另一种设计方案规定,凹槽占安装面和/或接触面的面积百分比是局部变化的。这是指,在整个表面上观察,存在这样的区域,在该区域中凹槽占那里局部存在的总面积的面积比例大于在其它区域中的情况。由此钎焊连接部可以有利地与特定的元器件的要求相匹配,正如接下来应更详细地阐述的那样。例如,根据本发明的特殊设计方案可能的是,凹槽占安装面和/或接触面的热传递预期升高的区域的面积百分比高于占热传递预期较低的区域的面积百分比。由此可以以结构方式实现,在元器件发热升高的区域中也能够更强地散热。这导致了元器件的更均匀温度曲线,从而一方面降低了元器件的总的热负荷,另一方面导致更均匀的热膨胀性能。由此能够有利地减少由于绝对发热和由于热应力而造成的组成构件的热负荷。
根据本发明的一种特别实施方式存在另一种可能性,即,凹槽占安装面和/或接触面边缘的面积百分比高于占中间的面积百分比。该实施方式有利地实现了,多余的焊料以及在钎焊时产生的气体可更容易从钎焊连接部的中间向外输送。这有利地改善了所形成的钎焊连接部的质量。
附图说明
本发明的进一步的细节接下来借助附图得以描述。相同或对应的附图元件在各图中分别设有相同的附图标记并就此而言只是重复阐述了附图之间的区别。附图中:
图1是根据本发明的电子组件的一个实施例的示意性剖面图;
图2至4是根据本发明的方法的实施例的所选择的制造步骤;
图5是根据本发明的电子组件的另一实施例的钎焊连接部的替代设计方案的示意性剖面图;
图6至10是根据本发明方法或者本发明组件的其它实施例、在接合面和/或接触面上的凹槽的不同分布的俯视图以及;
图11是根据本发明组件的最后一个实施例的钎焊连接部的特殊实施例的剖面图。
具体实施方式
根据图1的电子组件11具有衬底12,电子元器件13固定在衬底12上。为此,衬底12提供由金属涂层15结构化的接触面14。元器件13具有带有金属结构17的安装侧16,其中该金属结构17提供用于钎焊连接的安装面18。在安装面18与接触面14之间设有焊料19。因此,图1示出了在钎焊过程之前的电子组件。
从图1中另外可知,安装面18并非在整个面上与衬底的接触面14形成连接。相反,在安装面18的区域之间设有通道20,通道20并未完全用焊料19填充。虽然该焊料部分地到达通道20中,但是衬底11与元器件13之间的暂时连接仅仅在安装面18的区域内实现,在安装面18的区域内存在间隙21,间隙21应当提供用于形成扩散钎焊连接的接合缝(为此接下来还有更多描述)。
图2中展示出由通道20(如图1中展示)环绕的柱状结构元件22。图2是如图1中所示的布置的局部。在此示出了用于形成钎焊连接的工艺阶段,其中元器件13正好放置在衬底11上。
图3中示出了下一个制造步骤。将安装力F施加到元器件13上,这导致元器件13与衬底11之间的距离减小。在此,在形成所需的接合缝的同时接触面14与安装面18之间的间隙也减小了。焊料19在此从间隙21中被部分挤出并在由通道20提供的容积中形成隆起物。
图4中钎焊的制造步骤已经完成,从而形成了钎焊连接部。可见,该钎焊连接部直接邻接接触面14和安装面18并且具有设计为铜和锡之间的金属间化合物的扩散区24。铜源自于金属涂层15和金属结构17,二者均由铜组成。锡由焊料20提供。焊料20包括含锡的焊料,其中有利地能够使用未特别适合扩散钎焊的标准钎焊合金。该焊料可以例如是焊膏,其中可以是优选无铅的(例如锡银铜基的)钎焊合金作为颗粒供给粘合剂。在形成钎焊连接的过程中,该钎焊合金熔化,并且通过铜从金属涂层和金属结构中扩散到邻接的边缘区域中该钎焊合金的化学成分改变成,使得在扩散区24中形成金属间化合物。间隙21这样窄,使得通过扩散区24至少部分或完全地桥接该间隙21。这里形成了非常热稳定的元器件连接,因为金属间化合物的熔点在400℃以上。在扩散区以外可见,由钎焊合金25形成了加宽的钎焊连接部。这种加宽的钎焊连接部部分地填充了通道20。钎焊合金也可以用来传输电流,因为该钎焊合金增大了柱状结构元件22的横截面。
图5中局部示出了电子组件的另一结构形式。该电子组件也已经被钎焊。区别在于,金属结构17a并非设置在元器件13上,而是设置在衬底12上。与此相应的是,金属涂层设置在元器件13上。虽然未示出、但是能够设想的是这样的结构形式,其中两个接合配对件,确切地说元器件13和衬底12都具有金属结构,该金属结构呈互补式设计。在此,结构元件直接上下重叠地布置以形成间隙。然而,与图1至4中示出的方式类似地,在图5中通过接触面14和安装面18形成间隙。
与图1至4相比较的另一区别在于,所述通道完全用钎焊合金25填充。该完全填充实现的方式是,接合配对件或接合配对件之一设有一定量的焊料(参见图1),该焊料的量足以在施加根据图3的安装力F时使所形成的隆起物23完全填充所述通道。因此在钎焊连接部形成之后提供了更大的用于导引电流的横截面,因为钎焊合金25同样可用来导引电流。通过在间隙21中形成的扩散区24确保钎焊连接的机械稳定性。
图6至9展示出接触面14或安装面18的俯视图。这取决于是根据图1的电子元器件13还是根据图5的衬底12承载金属结构。因为它们在这两种情况下在结构上没有区别,所以针对这两种情况相应使用一张图。
图6中以俯视图示出了根据图1至5的柱状结构元件22。明显可见,由环绕柱状结构元件22的间隙形成通道。
根据图7,通道20设计为V形通道,其中从图7中可见由此形成的边棱。提供了直角交叉的通道20,其中由此产生作为结构元件的平截头棱锥26。平截头棱锥26的各上边界面形成接触面14或安装面18。
图8中示出与图6中类似的柱状结构元件,该柱状结构元件同样具有圆形横截面。如同图6,相应的端面形成接触面14或安装面18。与图6中不同的是,柱状结构元件22的直径大小不同,即设计成,直径朝向结构元件22的组合的边缘而变小。因此在柱间距不变的情况下,环绕结构元件22的通道20的容积朝向边缘变大,由此简化了剩余焊料的排出。因此,这样的结构形式尤其适合根据图5的钎焊连接部,在那里通道20应由钎焊合金25完全填充。
在图9中接触面14或安装面18设计成连续的,其中设有杯状凹槽27。另外从图9中可见,这些杯状凹槽27以不同密度设置。在图9的右上角中,凹槽以双倍密度布置。在此,其为这样的区域,在该区域中仅少的热量通过与所形成的钎焊连接部邻接的构件引入钎焊连接部中。因此,在该区域中更低的散热是有利的,从而该元器件不会因局部不同的加热而变形。
在图10中,可见柱状结构元件22,该柱状结构元件22具有正方形横截面。它们通过具有平的通道底部的通道20彼此分开。从图10中也可见,在图10的右下角中单位面积可供使用的接触面14或安装面18仅有剩余区域中的一半那么大,因为布置有双倍那么多的交叉通道22。另外图10中还可见额外的储库28,在那里未设有柱状结构元件22,从而形成较大的用于容纳焊料的空腔。当安装面18或接触面14特别大使得过量的焊料不会轻易地被输送到所述面的边缘时,尤其可以设置这样的储库。
图11中示出了结构元件29的替代构造,结构元件29是金属结构17的一部分。结构元件29设计成栓丁状,使其不存在限定安装面18的边缘的边棱。安装面18反而通过在桥接了间隙21的区域中的扩散区的尺寸限定。一旦接合配对件之间的距离增大到使得该距离不再能够被扩散区24桥接时,凹槽就在那里开始,钎焊合金25在该凹槽中至少部分地形成。
Claims (10)
1.一种用于在衬底(12)上扩散钎焊电子元器件(13)的方法,其中:
-将所述元器件(13)以其安装面(18)放置在所述衬底(12)的接触面(14)上,其中在所述衬底与所述元器件(13)之间施加焊料,并且
-将所述焊料(19)加热到引发在所述焊料(19)与所述元器件(13)以及所述衬底(12)之间的扩散过程的温度,其中形成钎焊连接部,所述钎焊连接部具有桥接所述接触面(14)与所述安装面(18)之间的间隙(21)的扩散区(24),所述扩散区(24)具有与所述焊料相比升高的熔化温度,
其特征在于,
所述元器件(13)的安装面(18)和/或所述衬底(12)的接触面(14)设有凹槽(20、27),所述凹槽(20、27)在所述钎焊连接部形成之后位于桥接所述接触面(14)与所述安装面(18)之间的间隙(21)的扩散区(24)以外。
2.根据权利要求1所述的方法,其特征在于,所述凹槽(20、27)具有通道(20)的形式。
3.根据权利要求2所述的方法,其特征在于,所述通道(20)环绕柱状的结构元件(22),其中所述结构元件(22)形成所述安装面(18)和/或所述接触面(14)。
4.根据前述权利要求之一所述的方法,其特征在于,在所述元器件(13)与所述衬底(12)之间施加所述焊料的量为,使得所述凹槽完全被所述焊料(19)填充。
5.根据前述权利要求之一所述的方法,其特征在于,所述凹槽(20、27)占所述安装面(18)和/或所述接触面(14)的面积百分比是局部变化的。
6.根据权利要求5所述的方法,其特征在于,所述凹槽(20、27)占所述安装面(18)和/或所述接触面(14)的边缘的面积百分比高于占所述安装面(18)和/或所述接触面(14)的中部的面积百分比。
7.根据权利要求5所述的方法,其特征在于,所述凹槽(20、27)占所述安装面(18)和/或所述接触面(14)的热传递预期较高的区域的面积百分比高于占所述安装面(18)和/或所述接触面(14)的热传递预期较低的区域的面积百分比。
8.根据前述权利要求之一所述的方法,其特征在于,所述凹槽(20、27)占所述元器件(13)的安装面(18)和/或所述衬底(12)的接触面(14)的面积百分比为50%以上,优选为70%以上。
9.一种电子组件(11),其包含带有接触面(14)的衬底(12),电子元器件(13)以安装面(18)钎焊在所述接触面(14)上,其中钎焊连接部具有桥接所述接触面(14)和所述安装面(18)之间的间隙(21)的扩散区(24),所述扩散区(24)具有与焊料相比更高的熔化温度,
其特征在于,
所述元器件(13)的安装面(18)和/或所述衬底(12)的接触面(14)设有凹槽(20、27),所述凹槽(20、27)位于桥接所述接触面(14)与所述安装面(18)之间的间隙(21)的扩散区(24)以外。
10.根据权利要求9所述的电子组件,其特征在于,所述凹槽(20、27)占所述元器件(13)的安装面(18)和/或所述衬底(12)的接触面(14)的面积百分比为50%以上,优选为70%以上。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102013219642.3A DE102013219642A1 (de) | 2013-09-27 | 2013-09-27 | Verfahren zum Diffusionslöten unter Ausbildung einer Diffusionszone als Lötverbindung und elektronische Baugruppe mit einer solchen Lötverbindung |
DE102013219642.3 | 2013-09-27 | ||
PCT/EP2014/069368 WO2015043969A2 (de) | 2013-09-27 | 2014-09-11 | Verfahren zum diffusionslöten unter ausbildung einer diffusionszone als lötverbindung und elektronische baugruppe mit einer solchen lötverbindung |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105706224A true CN105706224A (zh) | 2016-06-22 |
CN105706224B CN105706224B (zh) | 2018-11-02 |
Family
ID=51589272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480053472.1A Active CN105706224B (zh) | 2013-09-27 | 2014-09-11 | 通过将扩散区设计为钎焊连接部的扩散钎焊方法和带这种钎焊连接部的电子组件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10004147B2 (zh) |
EP (1) | EP3036761B1 (zh) |
CN (1) | CN105706224B (zh) |
DE (1) | DE102013219642A1 (zh) |
WO (1) | WO2015043969A2 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109663998A (zh) * | 2018-11-29 | 2019-04-23 | 贵州振华风光半导体有限公司 | 一种功率半导体芯片钎焊溢料控制方法 |
CN111052884A (zh) * | 2017-07-13 | 2020-04-21 | 赛峰电子与防务公司 | 包括焊接在埋入式焊盘上的smd的电子板 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013219642A1 (de) | 2013-09-27 | 2015-04-02 | Siemens Aktiengesellschaft | Verfahren zum Diffusionslöten unter Ausbildung einer Diffusionszone als Lötverbindung und elektronische Baugruppe mit einer solchen Lötverbindung |
US10923454B2 (en) * | 2015-06-09 | 2021-02-16 | Seyed Amir Paknejad | Method and apparatus for creating a bond between objects based on formation of inter-diffusion layers |
DE102017206932A1 (de) | 2017-04-25 | 2018-10-25 | Siemens Aktiengesellschaft | Lotformteil zum Erzeugen einer Diffusionslötverbindung und Verfahren zum Erzeugen eines Lotformteils |
DE102017206930A1 (de) | 2017-04-25 | 2018-10-25 | Siemens Aktiengesellschaft | Lotformteil zum Diffusionslöten, Verfahren zu dessen Herstellung und Verfahren zu dessen Montage |
DE102017206925A1 (de) | 2017-04-25 | 2018-10-25 | Siemens Aktiengesellschaft | Verfahren zum Erzeugen einer Diffusionslötverbindung |
DE102018201974A1 (de) * | 2018-02-08 | 2019-08-08 | Siemens Aktiengesellschaft | Verfahren zum Herstellen einer Baueinheit sowie Verfahren zum Verbinden eines Bauteils mit einer solchen Baueinheit |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6406636B1 (en) * | 1999-06-02 | 2002-06-18 | Megasense, Inc. | Methods for wafer to wafer bonding using microstructures |
US6670222B1 (en) * | 1997-06-14 | 2003-12-30 | Jds Uniphase Corporation | Texturing of a die pad surface for enhancing bonding strength in the surface attachment |
US6673189B2 (en) * | 2000-06-16 | 2004-01-06 | Infineon Technologies Ag | Method for producing a stable bond between two wafers |
EP1498208A1 (de) * | 2003-07-18 | 2005-01-19 | Robert Bosch GmbH | Anordnung zur Befestigung eines Bauelements |
JP2007110001A (ja) * | 2005-10-17 | 2007-04-26 | Fuji Electric Holdings Co Ltd | 半導体装置 |
US20120306087A1 (en) * | 2011-05-31 | 2012-12-06 | Infineon Technologies Ag | Semiconductor device including excess solder |
CN102867804A (zh) * | 2011-07-06 | 2013-01-09 | 英飞凌科技股份有限公司 | 包括具有突出体的接触片的半导体器件及其制造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5968935A (ja) * | 1982-10-13 | 1984-04-19 | Toshiba Corp | 半導体装置の製造方法 |
JPS6164132A (ja) * | 1984-09-05 | 1986-04-02 | Nec Corp | 半導体装置 |
JP3350152B2 (ja) | 1993-06-24 | 2002-11-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH0738208A (ja) * | 1993-07-22 | 1995-02-07 | Nec Corp | 半導体レーザ装置 |
US6399182B1 (en) * | 2000-04-12 | 2002-06-04 | Cmc Wireless Components, Inc. | Die attachment utilizing grooved surfaces |
JP3934565B2 (ja) * | 2003-02-21 | 2007-06-20 | 富士通株式会社 | 半導体装置 |
US20040262781A1 (en) * | 2003-06-27 | 2004-12-30 | Semiconductor Components Industries, Llc | Method for forming an encapsulated device and structure |
KR100555706B1 (ko) * | 2003-12-18 | 2006-03-03 | 삼성전자주식회사 | 미세 솔더볼 구현을 위한 ubm 및 이를 이용한 플립칩패키지 방법 |
KR101131259B1 (ko) * | 2004-03-24 | 2012-03-30 | 스탄레 덴끼 가부시키가이샤 | 발광 장치의 제조방법 및 발광 장치 |
DE102004058878A1 (de) * | 2004-12-06 | 2006-06-14 | Infineon Technologies Ag | Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements |
US7528061B2 (en) * | 2004-12-10 | 2009-05-05 | L-3 Communications Corporation | Systems and methods for solder bonding |
DE102005055280B3 (de) * | 2005-11-17 | 2007-04-12 | Infineon Technologies Ag | Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements |
US20070210037A1 (en) * | 2006-02-24 | 2007-09-13 | Toshifumi Ishida | Cooling block forming electrode |
JP4846515B2 (ja) * | 2006-10-18 | 2011-12-28 | 株式会社東芝 | 光半導体装置及び光半導体装置の製造方法 |
DE102011078582A1 (de) * | 2011-07-04 | 2013-01-10 | Robert Bosch Gmbh | Verfahren zum Herstellen von strukturierten Sinterschichten und Halbleiterbauelement mit strukturierter Sinterschicht |
US8736052B2 (en) | 2011-08-22 | 2014-05-27 | Infineon Technologies Ag | Semiconductor device including diffusion soldered layer on sintered silver layer |
US9437520B2 (en) * | 2013-03-13 | 2016-09-06 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device including a semiconductor element and a fixed member to which the semiconductor element is fixed |
DE102013219642A1 (de) | 2013-09-27 | 2015-04-02 | Siemens Aktiengesellschaft | Verfahren zum Diffusionslöten unter Ausbildung einer Diffusionszone als Lötverbindung und elektronische Baugruppe mit einer solchen Lötverbindung |
-
2013
- 2013-09-27 DE DE102013219642.3A patent/DE102013219642A1/de not_active Withdrawn
-
2014
- 2014-09-11 EP EP14771823.3A patent/EP3036761B1/de active Active
- 2014-09-11 US US15/025,515 patent/US10004147B2/en active Active
- 2014-09-11 WO PCT/EP2014/069368 patent/WO2015043969A2/de active Application Filing
- 2014-09-11 CN CN201480053472.1A patent/CN105706224B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6670222B1 (en) * | 1997-06-14 | 2003-12-30 | Jds Uniphase Corporation | Texturing of a die pad surface for enhancing bonding strength in the surface attachment |
US6406636B1 (en) * | 1999-06-02 | 2002-06-18 | Megasense, Inc. | Methods for wafer to wafer bonding using microstructures |
US6673189B2 (en) * | 2000-06-16 | 2004-01-06 | Infineon Technologies Ag | Method for producing a stable bond between two wafers |
EP1498208A1 (de) * | 2003-07-18 | 2005-01-19 | Robert Bosch GmbH | Anordnung zur Befestigung eines Bauelements |
JP2007110001A (ja) * | 2005-10-17 | 2007-04-26 | Fuji Electric Holdings Co Ltd | 半導体装置 |
US20120306087A1 (en) * | 2011-05-31 | 2012-12-06 | Infineon Technologies Ag | Semiconductor device including excess solder |
CN102867804A (zh) * | 2011-07-06 | 2013-01-09 | 英飞凌科技股份有限公司 | 包括具有突出体的接触片的半导体器件及其制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111052884A (zh) * | 2017-07-13 | 2020-04-21 | 赛峰电子与防务公司 | 包括焊接在埋入式焊盘上的smd的电子板 |
CN109663998A (zh) * | 2018-11-29 | 2019-04-23 | 贵州振华风光半导体有限公司 | 一种功率半导体芯片钎焊溢料控制方法 |
Also Published As
Publication number | Publication date |
---|---|
EP3036761A2 (de) | 2016-06-29 |
CN105706224B (zh) | 2018-11-02 |
WO2015043969A2 (de) | 2015-04-02 |
EP3036761B1 (de) | 2019-07-10 |
US10004147B2 (en) | 2018-06-19 |
WO2015043969A3 (de) | 2015-07-02 |
DE102013219642A1 (de) | 2015-04-02 |
US20160219720A1 (en) | 2016-07-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105706224A (zh) | 通过将扩散区设计为钎焊连接部的扩散钎焊方法和带这种钎焊连接部的电子组件 | |
CN106133895B (zh) | 使用罩盖装配电构件的方法和适合在该方法中使用的罩盖 | |
CN106133892A (zh) | 使用罩盖装配电气构件的方法和适合在该方法中使用的罩盖 | |
US7364063B2 (en) | Thermally coupling an integrated heat spreader to a heat sink base | |
US10357840B2 (en) | Method for forming a bonded joint | |
JP2019104680A5 (zh) | ||
TWI672748B (zh) | 半導體裝置及半導體裝置的製造方法 | |
JP2014097529A (ja) | 発泡金属による接合方法、半導体装置の製造方法、半導体装置 | |
US11569151B2 (en) | Composite assembly of three stacked joining partners | |
CN102800659A (zh) | 树脂密封型电子控制装置及其制造方法 | |
CN110574156A (zh) | 具有安装在两个基体之间的构件的电子组件及其制造方法 | |
CN105633064A (zh) | 半导体组件及其制备方法 | |
US8322403B2 (en) | Fixing assembly for heat-absorbing surfaces of juxtaposed heat pipes and heat sink having the same | |
JP2008141007A (ja) | 多層基板の製造方法 | |
WO2016017012A1 (ja) | 端子接続構造およびその製造方法 | |
CN105722308A (zh) | 制造具有热的金属化通孔的线路装置 | |
KR102409338B1 (ko) | 확산 솔더 연결을 설정하기 위한 솔더 프리폼 및 솔더 프리폼을 생성하기 위한 방법 | |
US7900353B2 (en) | Method for combining axially heated heat pipes and heat-conducting base | |
JP4882570B2 (ja) | モジュールの製造方法と、それにより製造したモジュール | |
JP2016219681A (ja) | 金属配線の接合構造および接合方法 | |
JP5281762B2 (ja) | 電極接合構造体 | |
JP7243584B2 (ja) | 半導体装置の製造方法 | |
JP2009004463A (ja) | 基板の接合方法及び基板接合体 | |
US20100133650A1 (en) | Semiconductor device | |
JP3839891B2 (ja) | 半導体リードフレーム及び半導体パッケージ方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |