JPS5968935A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS5968935A
JPS5968935A JP17837082A JP17837082A JPS5968935A JP S5968935 A JPS5968935 A JP S5968935A JP 17837082 A JP17837082 A JP 17837082A JP 17837082 A JP17837082 A JP 17837082A JP S5968935 A JPS5968935 A JP S5968935A
Authority
JP
Japan
Prior art keywords
solder
area
semiconductor element
solder foil
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17837082A
Other languages
English (en)
Inventor
Osamu Kodan
小段　修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17837082A priority Critical patent/JPS5968935A/ja
Publication of JPS5968935A publication Critical patent/JPS5968935A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置の製造方法にかかシ、特に半導体
素子を素子配設台床にはんだ接合する方法の改良を含む
半導体装置の製造方法を提供する。
〔発明の技術的背景〕
半導体装置で、その半導体素子が素子配役基台にはんだ
接合されるものに例えばパワートランジスタがある。−
例のパワートランジスタで金属封止タイプのものを第１
図に示す。そして、その半導体素子配設部は第２図に示
すように、表面の少くとも半導体素子配設域に設けられ
たニッケルめっき層（１）を有する素子配設基台（２）
に、半導体素子（３）が下面のニッケルめっき層（４）
と前記ニッケルめっき層（１）との間にはんだ層（５）
を介して接合されている。
上記はんだ層（５）は予めはんだ接合に適したはんだ量
に形成された円板状または方形のはんだ箔を素子配設基
台の上面に置き、この上に半導体素子を載せて水素雰囲
気および不活性ガス雰囲気の加熱炉中を通過させてはん
だを溶融し形成されたものである。従来、はんだ箔はそ
の主面面積が半導体ぷ子の主面面積と同等か、５０〜６
０％に形成されたものを用いていた。
〔従来技術の問題点〕
斜上の技術には次にあげる欠点があった。
（Ｉ）、はんだ箔表面の酸化が甚しい場合、あるいはニ
ッケルめっき層の表面酸化が甚しい場合、またははんだ
表面やニッケルめっき層表面に汚染がある場合にはその
組み合わせＫよりはんだとニッケルめっき層とのなじみ
が悪く、第３図に示すようにはんだ層（５）内にボイド
ｔ６１　、　（６）・・・を生じたシ、第４図に示すよ
うに接合の太部（７）　、　ｆ力・・・を生じたりなど
する。
斜上によシ熱抵抗が大きくばらつき放熱特性が低下する
。
（■）、素子配設基台がその接合部表面に凹凸のある例
えば、凹の存在する第５図に示す素子配役基台（２′）
では四部（８）　、　（８’）・・・の空気がはんだに
閉じこめられ、第６図に示すようなボイド（６’）　、
　（６′）・・・になる。
（ｉｉｉ）、はんだ箔に例えば第７図に示すように厚さ
が小であるとはんだ箔（５′）に凹凸を生じ、加熱炉中
で下部の凹部内の空気が閉じこめられてボイド（ｆｆ／
）になる。
斜上のいずれも特に自動組立の場合には加熱時間も短か
く、修理も不能である重大な欠点となる。
ｒ発明の目的〕 この発明は半導体装置の製造方法にかかシ、特に素子配
設台床に半導体素子をはんだにょシ接合する工程の改良
に関する。
〔発明の概要〕
この発明にかかるはんだ接合には、はんだ箔を予めその
主面の面積が半導体素子の主面の面積の２５−以下であ
るように形成し、このはんだ箔によってはんだ接合を施
すことを特徴とする。
〔発明の実施例〕
この発明の１実施例は、素子配設台床上にはんだ箔を載
置した状態を示す第９図、および、前記はんだ箔を溶融
した状態を示す第１０図によって示されるように、はん
だ箔の主面面積を従来のそれよりも著しく小さく形成し
ている。ただし、半導体素子のはんだ接合において、は
んだ量は変えることができないので、その箔の厚さは大
にしている。図に：オイて、（２′）は素子を接合させ
る部位の主面に四部（８１、（８）・・・を有する素子
配設台床、（３）は半導体素子で一例のサイズは４　ｍ
ｍ角になり、半導体素子を接合するだめのはんだ層厚は
０．０４　ｒｎｙｔに設定されている。
はんだ箔のサイズを〔縦×横×厚〕　（単位はいず九も
關）で表わすと、従来の（２，５Ｘ　３．２　Ｘ　Ｏ，
０８）のものを本発明では（１，８Ｘ２．ＯＸｏ、２］
にした。そして、はんだ箔の主面面積に対する半導体素
子の主面面積の比を求めると下記の如くなる。
本発明の半導体装置：　”Ｘ　１００（ト）＝２３（鋤
６ 本願にかかるはんだ箔と半導体素子との主面面積比を１
つの品種につき社々に変え、ボイドの発生を熱抵抗値に
置き換えて良好なる範囲を求めたのが第１１図に示す分
布図である。す々わち、この１実施例の結果を実線で示
し、従来の主面面積比が２５％を超えるものを破線で示
すように、両者の間には明確な差が認められる。
上述の結果にもとづき多くの品種につきはんだ箔と半導
体素子との主面面積比と熱抵抗値との相間を調査した結
果を第１２図に示す。これによると面積比が２５％以下
において明確に良好な値が示されている。
〔発明の効果〕
この発明によれば、はんだ箔と半導体素子との主面面積
比を２５％以下に選定されるので、第１２図に示される
ように熱抵抗値を低減できる。また、工程における熱抵
抗値不良発生率が従来の５％から０．２％（供試数１０
．０００個）に低減した。これをさらに一部につきボイ
ド面積を１ｌｌｌｊ定したところ、従来のものは実施例
の２．５倍であることが判明した。
この発明は実施が容易である上に著効を示し工程の自動
化に顕著な効果を示すものである。
【図面の簡単な説明】
第１図は金属封止タイプの半導体装置の斜視図第２図な
いし第８図は従来のはんだ接合工程を説明するためのい
ず７′［も断面図、第９図および第１０図は１実施例の
はんだ接合工程を説明するためのいずれも断面図、第１
１図および第１２図はいずれも本発明および効果を説明
するだめの線図である。 １．４　　　　　ニッケルめっき層 ２．２′　　　　　素子配設台床 ３　　　　　　半導体素子 ５．５’、５“　　はんだ ８　　　　　　　素子配役台床の凹部 第　　１　　図 第　　２　　図 第　　３　　図 第５図 第　６　図 第７図 第　　８　　図

Claims (1)

    【特許請求の範囲】
  1. 半導体素子を素子配設基台にはんだ箔を介して載置し、
    加熱を施してはんだ箔を溶融し両者をはんだ接合させる
    半導体装置の製造忙おいて、社んだ箔を予めその主面の
    面積が半導体素子の主面の面積の２５％以下であるよう
    に形成し、このはんだ箔によってはんだ接合を施すこと
    を特徴とする半導体装置の製造方法。
JP17837082A 1982-10-13 1982-10-13 半導体装置の製造方法 Pending JPS5968935A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17837082A JPS5968935A (ja) 1982-10-13 1982-10-13 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17837082A JPS5968935A (ja) 1982-10-13 1982-10-13 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS5968935A true JPS5968935A (ja) 1984-04-19

Family

ID=16047303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17837082A Pending JPS5968935A (ja) 1982-10-13 1982-10-13 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5968935A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006060981A1 (de) * 2004-12-06 2006-06-15 Infineon Technologies Ag Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements
DE102013219642A1 (de) * 2013-09-27 2015-04-02 Siemens Aktiengesellschaft Verfahren zum Diffusionslöten unter Ausbildung einer Diffusionszone als Lötverbindung und elektronische Baugruppe mit einer solchen Lötverbindung

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006060981A1 (de) * 2004-12-06 2006-06-15 Infineon Technologies Ag Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements
DE102013219642A1 (de) * 2013-09-27 2015-04-02 Siemens Aktiengesellschaft Verfahren zum Diffusionslöten unter Ausbildung einer Diffusionszone als Lötverbindung und elektronische Baugruppe mit einer solchen Lötverbindung
US10004147B2 (en) 2013-09-27 2018-06-19 Siemens Aktiengesellschaft Method for the diffusion soldering of an electronic component to a substrate

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