WO2006060981A1 - Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements - Google Patents
Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements Download PDFInfo
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- WO2006060981A1 WO2006060981A1 PCT/DE2005/002109 DE2005002109W WO2006060981A1 WO 2006060981 A1 WO2006060981 A1 WO 2006060981A1 DE 2005002109 W DE2005002109 W DE 2005002109W WO 2006060981 A1 WO2006060981 A1 WO 2006060981A1
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/495—Lead-frames or other flat leads
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Definitions
- the present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
- the process takes place under formation gas atmosphere at temperatures around 300 - 400 0 C and under application of high contact pressures
- the low-melting solder is completely converted during the diffusion soldering process, that is, it completely dissolves in the metallic phase.
- the resulting compound consists of intermetallic phases, which usually have a much higher melting point than the actual "soldering temperature" at which they were formed, and therefore can withstand operating temperatures that are higher than the production temperature, with the difference between manufacturing - and operating temperature can be up to 400 - 600 0 C depending on the material system. Therefore, the use of the diffusion soldering process even brings some advantages of soldering, such. As the low production temperature, but at the same time allows the advantage of high operating temperature.
- a disadvantage resulting from the use of the diffusion soldering process is the formation of voids along the die-substrate bond line due to uncontrolled process flows and inappropriate choice of materials. Due to the above-mentioned high contact pressure when depositing the chip on the chip carrier or the substrate, solder metal phases with melting temperatures below the process temperature, the so-called low-melting phases, are forced out of the solder gap.
- a semiconductor component is provided with at least one chip and one substrate, wherein the chip has a backside, which is connected to a first surface of the substrate by means of diffusion soldering, wherein depressions are formed in the first surface of the substrate, which contain intermetallic phases which during of the diffusion soldering are formed.
- the molten metal resulting from the action of temperature flows into the depressions, whereby a lateral extrusion of the low-melting solder metal is inhibited.
- the lateral solder extrusion is inhibited, which in turn reduces the unwanted voids formation, which in turn improves the quality of the chip connection on the substrate.
- the depressions are formed in the form of channels.
- the channels are further formed continuously on the substrate.
- the depressions are formed in a first direction and in a second direction are and when the first and the second direction are perpendicular to each other, so that a grid-like structure is formed.
- the chip preferably has a solder metal on the rear side which comprises Sn or an Ag / Sn, Au / Sn, Ag / In or Cu / Sn alloy.
- a solder metal on the rear side which comprises Sn or an Ag / Sn, Au / Sn, Ag / In or Cu / Sn alloy.
- any metal or metal alloy suitable for diffusion soldering is also usable.
- the first surface of the substrate comprises Ni, Ag, Au, Pd, Cu, Pt or Fe or alloys of these metals.
- any metal or metal alloy suitable for diffusion soldering can be used.
- the depressions have a width in the range of 0.1 to 2 mm and a depth in the range of 0.05 to 1 mm.
- the islands are 0.1 to 2 mm long and 0.1 to 2 mm wide.
- the substrate is a leadframe.
- a method for producing a semiconductor component comprises the steps of: coating a rear side of a chip with a solder metal which is suitable for diffusion soldering; Preparing a substrate having a first surface made of a material suitable for diffusion soldering; Forming recesses in the first surface of the substrate; and bonding the back side of the chip to the first surface of the substrate by diffusion soldering.
- the depressions are formed in the form of channels passing over the substrate.
- the recesses are formed in a first direction and in a second direction.
- first direction and the second direction are formed perpendicular to one another, so that a rectangular lattice-like structure of channels and islands arises on the first substrate surface.
- the depressions are formed with a width in the range of 0.1 to 2 mm. Furthermore, the recesses are preferably formed with a width in the range of 0.05 to 1 mm.
- the islands are formed with a length and a width in the range of 0.1 to 2 mm.
- Figure 1 is a plan view of a carrier with semiconductor chips, which have been soldered according to the prior art
- FIG. 2 shows a schematic cross section through a semiconductor component
- FIG. 3 shows a substrate in an oblique view for a semiconductor component according to the invention
- FIG. 1 shows a plan view of a carrier 1 on which a multiplicity of chips 2 are arranged.
- the chips 2 were soldered on a planar substrate according to the prior art. Therefore, an undesirable formation of defects 3 is visible.
- FIG. 2 shows a schematic cross section through a semiconductor component 4.
- the semiconductor component 4 has a chip 2 with a front side 5 and a rear side 6. Furthermore, the semiconductor component 4 comprises a substrate 7 with a first surface 8 and a second surface 9.
- the chip 2 is soldered with its rear side 6 on the first surface 8 of the substrate 7. Furthermore, it is shown in FIG. 2 that the chip 2 is connected to the substrate 7 via lines 10.
- substrate 7 a substrate according to the invention having recesses 11 (not shown) was used, as shown in FIG.
- FIG. 3 shows a substrate 7 with the recesses 11 according to the invention.
- the depressions 11 are in the form of channels which extend in two mutually perpendicular directions continuously and with uniform distances from each other over the entire first surface 8 of the substrate 7, so that the first surface 8 of the substrate 7 has a grid-like topology.
- the molten metal flows into the depressions 11, whereby the lateral extrusion of the low-melting solder metal is inhibited. This in turn reduces the unwanted voids formation and achieves an improved connection between the substrate 7 and the chip 2.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102004058878A DE102004058878A1 (de) | 2004-12-06 | 2004-12-06 | Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements |
DE102004058878.3 | 2004-12-06 |
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Publication Number | Publication Date |
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WO2006060981A1 true WO2006060981A1 (de) | 2006-06-15 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/DE2005/002109 WO2006060981A1 (de) | 2004-12-06 | 2005-11-23 | Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements |
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DE (1) | DE102004058878A1 (de) |
WO (1) | WO2006060981A1 (de) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7874475B2 (en) | 2005-12-07 | 2011-01-25 | Infineon Technologies Ag | Method for the planar joining of components of semiconductor devices and a diffusion joining structure |
US8283756B2 (en) | 2007-08-20 | 2012-10-09 | Infineon Technologies Ag | Electronic component with buffer layer |
WO2015043969A3 (de) * | 2013-09-27 | 2015-07-02 | Siemens Aktiengesellschaft | Verfahren zum diffusionslöten unter ausbildung einer diffusionszone als lötverbindung und elektronische baugruppe mit einer solchen lötverbindung |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102012201935A1 (de) | 2012-02-09 | 2013-08-14 | Robert Bosch Gmbh | Verbindungsanordnung eines elektrischen und/oder elektronischen Bauelements |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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DE3128123A1 (de) * | 1980-07-23 | 1982-03-18 | RCA Corp., 10020 New York, N.Y. | "halbleiterbauelement" |
JPS5968935A (ja) * | 1982-10-13 | 1984-04-19 | Toshiba Corp | 半導体装置の製造方法 |
DE19531158A1 (de) * | 1995-08-24 | 1997-02-27 | Daimler Benz Ag | Verfahren zur Erzeugung einer temperaturstabilen Verbindung |
US6399182B1 (en) * | 2000-04-12 | 2002-06-04 | Cmc Wireless Components, Inc. | Die attachment utilizing grooved surfaces |
Family Cites Families (3)
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JPS6164132A (ja) * | 1984-09-05 | 1986-04-02 | Nec Corp | 半導体装置 |
US6670222B1 (en) * | 1997-06-14 | 2003-12-30 | Jds Uniphase Corporation | Texturing of a die pad surface for enhancing bonding strength in the surface attachment |
US6727587B2 (en) * | 2002-04-30 | 2004-04-27 | Infineon Technologies Ag | Connection device and method for producing the same |
-
2004
- 2004-12-06 DE DE102004058878A patent/DE102004058878A1/de not_active Withdrawn
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2005
- 2005-11-23 WO PCT/DE2005/002109 patent/WO2006060981A1/de active Application Filing
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DE3128123A1 (de) * | 1980-07-23 | 1982-03-18 | RCA Corp., 10020 New York, N.Y. | "halbleiterbauelement" |
JPS5968935A (ja) * | 1982-10-13 | 1984-04-19 | Toshiba Corp | 半導体装置の製造方法 |
DE19531158A1 (de) * | 1995-08-24 | 1997-02-27 | Daimler Benz Ag | Verfahren zur Erzeugung einer temperaturstabilen Verbindung |
US6399182B1 (en) * | 2000-04-12 | 2002-06-04 | Cmc Wireless Components, Inc. | Die attachment utilizing grooved surfaces |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7874475B2 (en) | 2005-12-07 | 2011-01-25 | Infineon Technologies Ag | Method for the planar joining of components of semiconductor devices and a diffusion joining structure |
US8283756B2 (en) | 2007-08-20 | 2012-10-09 | Infineon Technologies Ag | Electronic component with buffer layer |
WO2015043969A3 (de) * | 2013-09-27 | 2015-07-02 | Siemens Aktiengesellschaft | Verfahren zum diffusionslöten unter ausbildung einer diffusionszone als lötverbindung und elektronische baugruppe mit einer solchen lötverbindung |
US10004147B2 (en) | 2013-09-27 | 2018-06-19 | Siemens Aktiengesellschaft | Method for the diffusion soldering of an electronic component to a substrate |
Also Published As
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DE102004058878A1 (de) | 2006-06-14 |
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