CN105453251B - 在基板上从不同材料形成鳍的方法 - Google Patents

在基板上从不同材料形成鳍的方法 Download PDF

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Publication number
CN105453251B
CN105453251B CN201480043551.4A CN201480043551A CN105453251B CN 105453251 B CN105453251 B CN 105453251B CN 201480043551 A CN201480043551 A CN 201480043551A CN 105453251 B CN105453251 B CN 105453251B
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China
Prior art keywords
layer
coating
oxide skin
substrate
top surface
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Expired - Fee Related
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CN201480043551.4A
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English (en)
Chinese (zh)
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CN105453251A (zh
Inventor
S·S·宋
Z·王
C·F·耶普
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Qualcomm Inc
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Qualcomm Inc
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213Channel regions of field-effect devices
    • H10D62/221Channel regions of field-effect devices of FETs
    • H10D62/235Channel regions of field-effect devices of FETs of IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213Channel regions of field-effect devices
    • H10D62/221Channel regions of field-effect devices of FETs
    • H10D62/235Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292Non-planar channels of IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/08Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/011Manufacture or treatment comprising FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201480043551.4A 2013-08-01 2014-07-25 在基板上从不同材料形成鳍的方法 Expired - Fee Related CN105453251B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/956,398 2013-08-01
US13/956,398 US9396931B2 (en) 2013-08-01 2013-08-01 Method of forming fins from different materials on a substrate
PCT/US2014/048270 WO2015017283A1 (en) 2013-08-01 2014-07-25 Method of forming fins from different materials on a substrate

Publications (2)

Publication Number Publication Date
CN105453251A CN105453251A (zh) 2016-03-30
CN105453251B true CN105453251B (zh) 2019-05-28

Family

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Family Applications (1)

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CN201480043551.4A Expired - Fee Related CN105453251B (zh) 2013-08-01 2014-07-25 在基板上从不同材料形成鳍的方法

Country Status (6)

Country Link
US (2) US9396931B2 (https=)
EP (1) EP3028301A1 (https=)
JP (1) JP2016529708A (https=)
KR (1) KR20160038031A (https=)
CN (1) CN105453251B (https=)
WO (1) WO2015017283A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9129863B2 (en) 2014-02-11 2015-09-08 International Business Machines Corporation Method to form dual channel group III-V and Si/Ge FINFET CMOS
US9123585B1 (en) * 2014-02-11 2015-09-01 International Business Machines Corporation Method to form group III-V and Si/Ge FINFET on insulator
US9564518B2 (en) * 2014-09-24 2017-02-07 Qualcomm Incorporated Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
US9524987B2 (en) 2014-10-21 2016-12-20 United Microelectronics Corp. Fin-shaped structure and method thereof
US20160358827A1 (en) * 2014-10-21 2016-12-08 United Microelectronics Corp. Method of forming fin-shaped structure
US9633908B2 (en) 2015-06-16 2017-04-25 International Business Machines Corporation Method for forming a semiconductor structure containing high mobility semiconductor channel materials
CN107660310B (zh) * 2015-06-26 2022-03-08 英特尔公司 异质外延n型晶体管与p型晶体管的基于阱的集成
US9679899B2 (en) * 2015-08-24 2017-06-13 Stmicroelectronics, Inc. Co-integration of tensile silicon and compressive silicon germanium
CN109155994B (zh) 2016-05-17 2021-08-03 华为技术有限公司 一种用户面资源管理方法、用户面网元及控制面网元

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1681124A (zh) * 2004-03-31 2005-10-12 国际商业机器公司 集成电路结构及其形成方法
CN1826690A (zh) * 2003-07-21 2006-08-30 国际商业机器公司 沿多个表面具有应变晶格结构的fet沟道
CN101065840A (zh) * 2004-12-08 2007-10-31 先进微装置公司 半导体装置以及制造包括多堆栈混合定向层之半导体装置之方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129424A (ja) * 1992-04-01 1993-05-25 Ricoh Co Ltd 半導体装置とその製造方法
US6864581B1 (en) * 2002-08-15 2005-03-08 National Semiconductor Corporation Etched metal trace with reduced RF impendance resulting from the skin effect
US6762448B1 (en) 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
JP2006012995A (ja) * 2004-06-23 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
JP2008505488A (ja) * 2004-06-30 2008-02-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 特徴の異なる結晶性半導体領域を有する基板の形成技術
DE102004057764B4 (de) 2004-11-30 2013-05-16 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Substrats mit kristallinen Halbleitergebieten mit unterschiedlichen Eigenschaften, die über einem kristallinen Vollsubstrat angeordnet sind und damit hergestelltes Halbleiterbauelement
US6972478B1 (en) * 2005-03-07 2005-12-06 Advanced Micro Devices, Inc. Integrated circuit and method for its manufacture
US7803670B2 (en) 2006-07-20 2010-09-28 Freescale Semiconductor, Inc. Twisted dual-substrate orientation (DSO) substrates
JP2008108999A (ja) * 2006-10-27 2008-05-08 Sony Corp 半導体装置および半導体装置の製造方法
JP2008227026A (ja) * 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
US8241970B2 (en) 2008-08-25 2012-08-14 International Business Machines Corporation CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
US8258602B2 (en) 2009-01-28 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bipolar junction transistors having a fin
JP2011035064A (ja) * 2009-07-30 2011-02-17 Renesas Electronics Corp 半導体装置、半導体基板、及び半導体基板の処理方法
EP2315239A1 (en) 2009-10-23 2011-04-27 Imec A method of forming monocrystalline germanium or silicon germanium
US8513723B2 (en) 2010-01-19 2013-08-20 International Business Machines Corporation Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip
US8618556B2 (en) 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
KR20130054010A (ko) 2011-11-16 2013-05-24 삼성전자주식회사 Iii-v족 물질을 이용한 반도체 소자 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1826690A (zh) * 2003-07-21 2006-08-30 国际商业机器公司 沿多个表面具有应变晶格结构的fet沟道
CN1681124A (zh) * 2004-03-31 2005-10-12 国际商业机器公司 集成电路结构及其形成方法
CN101065840A (zh) * 2004-12-08 2007-10-31 先进微装置公司 半导体装置以及制造包括多堆栈混合定向层之半导体装置之方法

Also Published As

Publication number Publication date
KR20160038031A (ko) 2016-04-06
WO2015017283A1 (en) 2015-02-05
US20160322391A1 (en) 2016-11-03
CN105453251A (zh) 2016-03-30
US9396931B2 (en) 2016-07-19
US20150035019A1 (en) 2015-02-05
JP2016529708A (ja) 2016-09-23
EP3028301A1 (en) 2016-06-08

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Granted publication date: 20190528

Termination date: 20210725