US20150380257A1 - Method of forming finfet having fins of different height - Google Patents

Method of forming finfet having fins of different height Download PDF

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US20150380257A1
US20150380257A1 US14/849,506 US201514849506A US2015380257A1 US 20150380257 A1 US20150380257 A1 US 20150380257A1 US 201514849506 A US201514849506 A US 201514849506A US 2015380257 A1 US2015380257 A1 US 2015380257A1
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wafer
forming
fins
oxide layer
depression
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Stanley Seungchul Song
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present disclosure is directed to a method of forming a finned field effect transistor (finFET) having fins of different height and toward a finFET formed thereby, and, more specifically, toward a method of forming a finFET on a silicon-on-insulator (SOI) substrate which method includes etching a depression in a surface of the SOI substrate and forming an oxide layer in the etched depression and toward a finFET formed thereby.
  • finFET finned field effect transistor
  • a finned field effect transistor is a FET that includes a fin-shaped channel region.
  • a gate structure intersects the channel region, and the ends of the fin structure receive source and drain doping.
  • the dimensions of the fin affect the operation of a finFET. For example, the length of the fin under the gate, measured in the direction from source to drain, determines the effective channel length of the device. It is desirable to form fins having a consistent height, and forming a finFET on a silicon-on-insulator (SOI) wafer provides improved fin height uniformity. This improved uniformity may be important as fin height scales.
  • SOI silicon-on-insulator
  • finFETs For various applications, including system on chip (SOC) operation, it is useful to make finFETs with fins having at least two different heights.
  • fin height can be controlled by removing different amounts of the shallow trench isolation (STI) oxide layer around different groups of fins. Essentially, all fins have the same height when measured from the underlying silicon layer, but different amounts of the STI oxide region are left around different fins so that different heights of the fins are left projecting from the STI layer.
  • STI shallow trench isolation
  • the thickness of the silicon layer is predetermined, and the conventional method cannot be used without modification to achieve different fin heights.
  • STI layer on the SOI active silicon layer, mask the area over a fin that is to be a shorter fin and selectively etch the STI layer around another fin to form a taller fin, which is similar to the method used in bulk substrate and that undermines the intended benefit of finFET on SOI substrate.
  • FIG. 1 illustrates a conventional SOI wafer 100 that includes a substrate 102 , a bottom oxide (BOX) layer 104 and an active silicon layer 106 having a top surface 108 .
  • a hardmask 202 which may comprise silicon nitride, for example, is formed on the top surface 108 , and a patterned resist 204 is formed on the hardmask so that a first portion 206 of the SOI wafer 100 is masked and a second portion 208 of the SOI wafer 100 is not masked.
  • FIG. 1 illustrates a conventional SOI wafer 100 that includes a substrate 102 , a bottom oxide (BOX) layer 104 and an active silicon layer 106 having a top surface 108 .
  • a hardmask 202 which may comprise silicon nitride, for example, is formed on the top surface 108
  • a patterned resist 204 is formed on the hardmask so that a first portion 206 of the SOI wafer 100 is masked and a
  • the portion of the hardmask 202 that is not protected by the resist 204 is etched down to the top surface 108 .
  • the top surface 108 With the top surface 108 exposed and the first portion 206 of the SOI wafer 100 protected, the top surface 108 is oxidized to form a depression 402 filled with a top oxide layer 404 as illustrated in FIG. 4 .
  • the oxidation process produces a generally symmetric oxide layer 404 which projects upwardly beyond the top surface 108 of the active silicon layer 106 about as far as it projects downwardly into the active silicon layer 106 .
  • FIG. 5 shows the SOI wafer 100 after the hardmask 202 and patterned resist 204 have been removed at which time a first plurality of masks 502 are formed in the first portion 206 of the SOI wafer 100 and a second plurality of masks 504 are formed in the second portion 208 of the SOI wafer 100 on the top oxide layer 404 .
  • the silicon not protected by the first plurality of masks 502 in the first portion 206 and the silicon and oxide not protected by the second plurality of masks 504 in the second portion 208 are etched away to produce a plurality of fins.
  • FIG. 6 illustrates a first plurality of fins 602 in the first portion 206 of the SOI wafer 100 that are taller than a second plurality of fins 604 in the second portion 208 of the SOI wafer 100 . While this method may produce fins for a finFET that are acceptable for some applications, the uneven top surface created by the top oxide layer 404 protruding from the top surface 108 of the active silicon layer 106 may make it difficult to apply masks for later forming the first and second plurality of fins.
  • a first exemplary embodiment of the invention comprises an SOI wafer having a silicon layer having a top surface, the SOI wafer having a first portion and a second portion.
  • the second portion includes an etched depression having an oxidized bottom and an oxide layer in the etched depression having an oxide layer top surface, where the oxide layer top surface is substantially even with the silicon layer top surface.
  • the device also includes a plurality of mask portions on the silicon layer top surface and on the oxide layer top surface for defining a first plurality of fins at the first SOI wafer portion and a second plurality of fins at the second SOI wafer portion.
  • a further exemplary embodiment comprises a non-transient computer readable medium containing instructions that, when executed by a computer processor cause a device controlled by the computer processor to perform actions on an silicon SOI wafer comprising a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, the active silicon layer having a surface opposite the bottom oxide layer.
  • the actions include forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask and forming fins at the first and second portions of the wafer.
  • FIGS. 1-6 are schematic side elevational views of a silicon-on-insulator (SOI) wafer as various conventional processes are performed thereon to form fins having different heights.
  • SOI silicon-on-insulator
  • FIGS. 7-12 are schematic side elevational views of an SOI wafer as various processes according to an embodiment of the disclosure are performed thereon to form fins having different heights.
  • FIG. 13 is a flow chart illustrating a method according to an embodiment.
  • FIG. 14 is a schematic diagram of an exemplary wireless communication system in which embodiments of the disclosure may be used.
  • FIG. 7 illustrates an SOI wafer 700 that includes a substrate 702 , a bottom oxide layer 704 and an active silicon layer 706 having a top surface 708 .
  • a hardmask 802 which may comprise silicon nitride, is formed on the top surface 708
  • a patterned resist 804 is formed on the hardmask 802 so that a first portion 806 of the SOI wafer 700 is masked and a second portion 808 of the SOI wafer 700 is not masked.
  • An etching process which may comprise a dry etching process using, for example, an etchant gas containing F, Br, or Cl such as SF 6 , HBr, and Cl 2 , or a wet etching process, for example, using EDP (EthyleneDiamine Pyrocatechol), KOH, TMAH (Tetramethyl ammonium hydroxide), or mixture of HF+HNO 3 +CH 3 COOH, or a dry etch followed by a wet etch, is then performed. This etches away the exposed hardmask 802 in the second portion 808 of the wafer and, in addition, as illustrated in FIG.
  • an etchant gas containing F, Br, or Cl such as SF 6 , HBr, and Cl 2
  • a wet etching process for example, using EDP (EthyleneDiamine Pyrocatechol), KOH, TMAH (Tetramethyl ammonium hydroxide), or mixture of HF+HNO 3 +CH 3 COOH, or
  • This etching process is not an oxidation process, but rather a process of physically or chemically removing a portion of the active silicon layer 706 in the second portion 808 of the SOI wafer 700 in preparation for a subsequent oxidation process discussed below.
  • the bottom 904 of the depression 902 is oxidized as illustrated in FIG. 10 with an oxidation process that forms a thermal oxide layer 1002 and which process deepens the depression 902 , forming a new bottom 1004 of the depression 902 closer to the bottom oxide layer 704 .
  • the bottom 904 of the depression 902 as it existed before the oxidation process is illustrated in FIG. 10 with dashed lines.
  • the oxidation process produces a generally symmetric thermal oxide layer 1002 , and the thermal oxide layer 1002 grows upwardly at about the same rate as the depth of the depression 902 increases.
  • the oxidation process is stopped when the top surface 1006 of the thermal oxide layer 1002 is generally even with the top surface 708 of the active silicon layer 706 and when the depression 902 is substantially filled with the thermal oxide layer 1002 .
  • the patterned resist 804 is removed, for example, by an oxygen based ashing process or wet cleaning such as SPM (Sulfuric Peroxide Mixture) or mixture of both ashing and wet clean, and the hardmask 802 is removed, for example, by hot phosphorous acid. This exposes the top surface 708 of the active silicon layer 706 and the top surface 1006 of the thermal oxide layer 1002 which together provide a substantially level surface for the subsequent formation of additional masks for forming fins.
  • SPM sulfuric Peroxide Mixture
  • FIG. 11 illustrates a plurality of first masks 1102 formed on the top surface 708 of the active silicon layer 706 in the first portion 806 of the SOI wafer 700 and a plurality of second masks 1104 formed on the top surface 1106 of the thermal oxide layer 1002 .
  • These first and second masks 1102 , 1104 define the locations and desired widths of a plurality of fins that will be formed beneath each of the masks 1102 , 1104 during a further processing step in which the portions of the active silicon layer 706 that are not beneath a first mask 1102 or a second mask 1104 and the portions of the thermal oxide layer 1002 that are not beneath a second mask 1104 are removed. The result, as illustrated in FIG.
  • first fins 1202 beneath each of the plurality of first masks 1102 and a plurality of second fins 1204 beneath each of the plurality of second masks 1104 which second fins 1204 are shorter than the plurality of first fins 1202 .
  • a finFET is formed from these different-height fins in a conventional manner.
  • the foregoing method produces a substantially level surface, comprising the top surface 708 of the active silicon region and the top surface 1006 of the thermal oxide layer 1002 , on which the first and second plurality of masks 1102 and 1104 can then be formed.
  • This smooth surface may lead to more accurate mask placement and better consistency in the heights of the first plurality of fins 1202 and in the heights of the second plurality of fins 1204 .
  • aligned fin height makes process integration such as gate etch and spacer etch easier due to one single aspect ratio of the fins themselves (including thermal oxide layer 1002 ) and also fin-to-fin space aspect ratio.
  • FIG. 13 illustrates a method according to an embodiment that includes a block 1302 of providing a silicon-on-insulator (SOI) wafer comprising a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer.
  • the method also includes a block 1304 of forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, and a block 1306 of etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom.
  • the method includes a block 1308 of forming a thermal oxide layer substantially filling the depression, a block 1310 of removing the first mask, and a block 1312 of forming fins at the first and second portions of the wafer.
  • FIG. 14 illustrates an exemplary wireless communication system 1400 in which one or more embodiments of the disclosure may be advantageously employed.
  • FIG. 14 shows three remote units 1420 , 1430 , and 1450 and two base stations 1440 . It will be recognized that conventional wireless communication systems may have many more remote units and base stations.
  • the remote units 1420 , 1430 , and 1450 include integrated circuit or other semiconductor devices 1425 , 1435 and 1455 (including finFET's with fins of different height as disclosed herein), which are among embodiments of the disclosure as discussed further below.
  • FIG. 14 shows forward link signals 1480 from the base stations 1440 and the remote units 1420 , 1430 , and 1450 and reverse link signals 1490 from the remote units 1420 , 1430 , and 1450 to the base stations 1440 .
  • the remote unit 1420 is shown as a mobile telephone
  • the remote unit 1430 is shown as a portable computer
  • the remote unit 1450 is shown as a fixed location remote unit in a wireless local loop system.
  • the remote units may be any one or combination of a mobile phone, hand-held personal communication system (PCS) unit, portable data unit such as a personal digital or data assistant (PDA), navigation device (such as GPS enabled devices), set top box, music player, video player, entertainment unit, fixed location data unit such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
  • FIG. 14 illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the disclosure may be suitably employed in any device having active integrated circuitry including memory and on-chip circuitry for test and characterization.
  • a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • an embodiment of the invention can include a computer readable media embodying a method for forming a finFET having fins with different heights. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.

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Abstract

A device is fabricated on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. A first mask is formed over the surface at a first portion of the wafer, leaving a second portion of the wafer unmasked. The wafer is etched at the unmasked second portion of the wafer to form a depression in the active silicon layer. A thermal oxide layer is formed to substantially fill the depression, the first mask is removed, and fins are formed at the first and second portions of the wafer.

Description

    CLAIM OF PRIORITY UNDER 35 USC §120
  • The present Application for Patent is a divisional application of and claims priority to application Ser. No. 13/784,867, entitled “METHOD OF FORMING FINFET HAVING FINS OF DIFFERENT HEIGHT,” filed Mar. 5, 2013, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
    • FIELD OF THE DISCLOSURE
  • The present disclosure is directed to a method of forming a finned field effect transistor (finFET) having fins of different height and toward a finFET formed thereby, and, more specifically, toward a method of forming a finFET on a silicon-on-insulator (SOI) substrate which method includes etching a depression in a surface of the SOI substrate and forming an oxide layer in the etched depression and toward a finFET formed thereby.
    • BACKGROUND
  • A finned field effect transistor (finFET) is a FET that includes a fin-shaped channel region. A gate structure intersects the channel region, and the ends of the fin structure receive source and drain doping. The dimensions of the fin affect the operation of a finFET. For example, the length of the fin under the gate, measured in the direction from source to drain, determines the effective channel length of the device. It is desirable to form fins having a consistent height, and forming a finFET on a silicon-on-insulator (SOI) wafer provides improved fin height uniformity. This improved uniformity may be important as fin height scales.
  • For various applications, including system on chip (SOC) operation, it is useful to make finFETs with fins having at least two different heights. When bulk silicon is used, fin height can be controlled by removing different amounts of the shallow trench isolation (STI) oxide layer around different groups of fins. Essentially, all fins have the same height when measured from the underlying silicon layer, but different amounts of the STI oxide region are left around different fins so that different heights of the fins are left projecting from the STI layer. However, when an SOI wafer is used, the thickness of the silicon layer is predetermined, and the conventional method cannot be used without modification to achieve different fin heights. Instead, it may be necessary to form an STI layer on the SOI active silicon layer, mask the area over a fin that is to be a shorter fin and selectively etch the STI layer around another fin to form a taller fin, which is similar to the method used in bulk substrate and that undermines the intended benefit of finFET on SOI substrate.
  • Another known method for forming a finFET on an SOI wafer with fins having different heights is illustrated in FIGS. 1-6. FIG. 1 illustrates a conventional SOI wafer 100 that includes a substrate 102, a bottom oxide (BOX) layer 104 and an active silicon layer 106 having a top surface 108. In FIG. 2, a hardmask 202, which may comprise silicon nitride, for example, is formed on the top surface 108, and a patterned resist 204 is formed on the hardmask so that a first portion 206 of the SOI wafer 100 is masked and a second portion 208 of the SOI wafer 100 is not masked. In FIG. 3, the portion of the hardmask 202 that is not protected by the resist 204 is etched down to the top surface 108. With the top surface 108 exposed and the first portion 206 of the SOI wafer 100 protected, the top surface 108 is oxidized to form a depression 402 filled with a top oxide layer 404 as illustrated in FIG. 4. The oxidation process produces a generally symmetric oxide layer 404 which projects upwardly beyond the top surface 108 of the active silicon layer 106 about as far as it projects downwardly into the active silicon layer 106.
  • FIG. 5 shows the SOI wafer 100 after the hardmask 202 and patterned resist 204 have been removed at which time a first plurality of masks 502 are formed in the first portion 206 of the SOI wafer 100 and a second plurality of masks 504 are formed in the second portion 208 of the SOI wafer 100 on the top oxide layer 404. The silicon not protected by the first plurality of masks 502 in the first portion 206 and the silicon and oxide not protected by the second plurality of masks 504 in the second portion 208 are etched away to produce a plurality of fins. FIG. 6 illustrates a first plurality of fins 602 in the first portion 206 of the SOI wafer 100 that are taller than a second plurality of fins 604 in the second portion 208 of the SOI wafer 100. While this method may produce fins for a finFET that are acceptable for some applications, the uneven top surface created by the top oxide layer 404 protruding from the top surface 108 of the active silicon layer 106 may make it difficult to apply masks for later forming the first and second plurality of fins.
  • It would therefore be desirable to provide a method of forming fins on an SOI wafer that have different heights in a manner that does not require the addition of an STI layer to the SOI wafer and that provides a substantially even surface on which to form a mask for forming the different height fins.
    • SUMMARY
  • A first exemplary embodiment of the invention comprises an SOI wafer having a silicon layer having a top surface, the SOI wafer having a first portion and a second portion. The second portion includes an etched depression having an oxidized bottom and an oxide layer in the etched depression having an oxide layer top surface, where the oxide layer top surface is substantially even with the silicon layer top surface. The device also includes a plurality of mask portions on the silicon layer top surface and on the oxide layer top surface for defining a first plurality of fins at the first SOI wafer portion and a second plurality of fins at the second SOI wafer portion.
  • A further exemplary embodiment comprises a non-transient computer readable medium containing instructions that, when executed by a computer processor cause a device controlled by the computer processor to perform actions on an silicon SOI wafer comprising a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, the active silicon layer having a surface opposite the bottom oxide layer. The actions include forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask and forming fins at the first and second portions of the wafer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.
  • FIGS. 1-6 are schematic side elevational views of a silicon-on-insulator (SOI) wafer as various conventional processes are performed thereon to form fins having different heights.
  • FIGS. 7-12 are schematic side elevational views of an SOI wafer as various processes according to an embodiment of the disclosure are performed thereon to form fins having different heights.
  • FIG. 13 is a flow chart illustrating a method according to an embodiment.
  • FIG. 14 is a schematic diagram of an exemplary wireless communication system in which embodiments of the disclosure may be used.
    •  DETAILED DESCRIPTION
  • Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.
  • The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments of the invention” does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
  • Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, “logic configured to” perform the described action.
  • FIG. 7 illustrates an SOI wafer 700 that includes a substrate 702, a bottom oxide layer 704 and an active silicon layer 706 having a top surface 708. In FIG. 8, a hardmask 802, which may comprise silicon nitride, is formed on the top surface 708, and a patterned resist 804 is formed on the hardmask 802 so that a first portion 806 of the SOI wafer 700 is masked and a second portion 808 of the SOI wafer 700 is not masked. An etching process, which may comprise a dry etching process using, for example, an etchant gas containing F, Br, or Cl such as SF6, HBr, and Cl2, or a wet etching process, for example, using EDP (EthyleneDiamine Pyrocatechol), KOH, TMAH (Tetramethyl ammonium hydroxide), or mixture of HF+HNO3+CH3COOH, or a dry etch followed by a wet etch, is then performed. This etches away the exposed hardmask 802 in the second portion 808 of the wafer and, in addition, as illustrated in FIG. 9, etches a depression 902 having a bottom 904 in the top surface 708 of the active silicon layer 706 of the SOI wafer 700. This etching process is not an oxidation process, but rather a process of physically or chemically removing a portion of the active silicon layer 706 in the second portion 808 of the SOI wafer 700 in preparation for a subsequent oxidation process discussed below.
  • After the aforementioned etching process, the bottom 904 of the depression 902 is oxidized as illustrated in FIG. 10 with an oxidation process that forms a thermal oxide layer 1002 and which process deepens the depression 902, forming a new bottom 1004 of the depression 902 closer to the bottom oxide layer 704. The bottom 904 of the depression 902 as it existed before the oxidation process is illustrated in FIG. 10 with dashed lines. The oxidation process produces a generally symmetric thermal oxide layer 1002, and the thermal oxide layer 1002 grows upwardly at about the same rate as the depth of the depression 902 increases. The oxidation process is stopped when the top surface 1006 of the thermal oxide layer 1002 is generally even with the top surface 708 of the active silicon layer 706 and when the depression 902 is substantially filled with the thermal oxide layer 1002. Next the patterned resist 804 is removed, for example, by an oxygen based ashing process or wet cleaning such as SPM (Sulfuric Peroxide Mixture) or mixture of both ashing and wet clean, and the hardmask 802 is removed, for example, by hot phosphorous acid. This exposes the top surface 708 of the active silicon layer 706 and the top surface 1006 of the thermal oxide layer 1002 which together provide a substantially level surface for the subsequent formation of additional masks for forming fins.
  • FIG. 11 illustrates a plurality of first masks 1102 formed on the top surface 708 of the active silicon layer 706 in the first portion 806 of the SOI wafer 700 and a plurality of second masks 1104 formed on the top surface 1106 of the thermal oxide layer 1002. These first and second masks 1102, 1104 define the locations and desired widths of a plurality of fins that will be formed beneath each of the masks 1102, 1104 during a further processing step in which the portions of the active silicon layer 706 that are not beneath a first mask 1102 or a second mask 1104 and the portions of the thermal oxide layer 1002 that are not beneath a second mask 1104 are removed. The result, as illustrated in FIG. 12, is a plurality of first fins 1202 beneath each of the plurality of first masks 1102 and a plurality of second fins 1204 beneath each of the plurality of second masks 1104 which second fins 1204 are shorter than the plurality of first fins 1202. A finFET is formed from these different-height fins in a conventional manner. Beneficially, the foregoing method produces a substantially level surface, comprising the top surface 708 of the active silicon region and the top surface 1006 of the thermal oxide layer 1002, on which the first and second plurality of masks 1102 and 1104 can then be formed. This smooth surface may lead to more accurate mask placement and better consistency in the heights of the first plurality of fins 1202 and in the heights of the second plurality of fins 1204. For example, considering a process integration flow that maintains the thermal oxide layer 1002 on top of the short fins 1204 in a downstream process, aligned fin height makes process integration such as gate etch and spacer etch easier due to one single aspect ratio of the fins themselves (including thermal oxide layer 1002) and also fin-to-fin space aspect ratio.
  • FIG. 13 illustrates a method according to an embodiment that includes a block 1302 of providing a silicon-on-insulator (SOI) wafer comprising a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method also includes a block 1304 of forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, and a block 1306 of etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom. In addition, the method includes a block 1308 of forming a thermal oxide layer substantially filling the depression, a block 1310 of removing the first mask, and a block 1312 of forming fins at the first and second portions of the wafer.
  • FIG. 14 illustrates an exemplary wireless communication system 1400 in which one or more embodiments of the disclosure may be advantageously employed. For purposes of illustration, FIG. 14 shows three remote units 1420, 1430, and 1450 and two base stations 1440. It will be recognized that conventional wireless communication systems may have many more remote units and base stations. The remote units 1420, 1430, and 1450 include integrated circuit or other semiconductor devices 1425, 1435 and 1455 (including finFET's with fins of different height as disclosed herein), which are among embodiments of the disclosure as discussed further below. FIG. 14 shows forward link signals 1480 from the base stations 1440 and the remote units 1420, 1430, and 1450 and reverse link signals 1490 from the remote units 1420, 1430, and 1450 to the base stations 1440.
  • In FIG. 14, the remote unit 1420 is shown as a mobile telephone, the remote unit 1430 is shown as a portable computer, and the remote unit 1450 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be any one or combination of a mobile phone, hand-held personal communication system (PCS) unit, portable data unit such as a personal digital or data assistant (PDA), navigation device (such as GPS enabled devices), set top box, music player, video player, entertainment unit, fixed location data unit such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. Although FIG. 14 illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the disclosure may be suitably employed in any device having active integrated circuitry including memory and on-chip circuitry for test and characterization.
  • Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
  • Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
  • The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • Accordingly, an embodiment of the invention can include a computer readable media embodying a method for forming a finFET having fins with different heights. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.
  • While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims (14)

What is claimed is:
1. A device comprising:
an SOI wafer having a silicon layer having a top surface, the SOI wafer having a first portion and a second portion, the second portion including an etched depression having an oxidized bottom;
an oxide layer in the etched depression having an oxide layer top surface, the oxide layer top surface being substantially even with the silicon layer top surface; and
a plurality of mask portions on the silicon layer top surface and on the oxide layer top surface for defining a first plurality of fins at the first SOI wafer portion and a second plurality of fins at the second SOI wafer portion.
2. The device of claim 1, including a first plurality of silicon fins beneath each of the plurality of mask portions and a second plurality of silicon fins beneath each of the plurality of second mask portions.
3. The device of claim 2, wherein a height of the first plurality of fins is greater than a height of the second plurality of fins.
4. The device of claim 3 incorporated into at least one semiconductor die.
5. The device of claim 1, wherein the device is selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
6. A non-transient computer readable medium containing instructions that, when executed by a computer processor cause a device controlled by the computer processor to perform actions on an SOI wafer comprising a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, the active silicon layer having a surface opposite the bottom oxide layer, the actions including:
forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked;
etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom;
forming a thermal oxide layer substantially filling the depression;
removing the first mask; and
forming fins at the first and second portions of the wafer.
7. The non-transient computer readable medium of claim 6, the actions further including, before forming the first mask, forming a hardmask over the surface and wherein etching the wafer at the unmasked second portion comprises etching through the hardmask and into the active silicon layer.
8. The non-transient computer readable medium of claim 6, wherein forming a thermal oxide layer substantially filling the depression comprises forming a thermal oxide layer filling the depression to a level substantially even with the surface.
9. The non-transient computer readable medium of claim 6, wherein forming fins comprises forming a first plurality of second masks on the surface at the first portion of the wafer, forming a second plurality of second masks on the thermal oxide layer and patterning the wafer to remove portions of the silicon layer not protected by the first plurality of second masks or the second plurality of second masks.
10. The non-transient computer readable medium of claim 6, wherein forming a thermal oxide layer comprises oxidizing the bottom of the depression.
11. The non-transient computer readable medium of claim 6, the actions further including, before forming the first mask, forming a hardmask over the surface, and wherein etching the wafer at the unmasked second portion comprises etching through the hardmask and into the active silicon layer, wherein forming a thermal oxide layer comprises oxidizing the bottom of the depression until a thermal oxide layer on the bottom of the depression is substantially even with the surface and wherein forming fins comprises forming a first plurality of second masks on the surface at the first portion of the wafer, forming a second plurality of second masks on the thermal oxide layer and patterning the SOI wafer to remove portions of the silicon layer not protected by the first plurality of second masks or the second plurality of second masks.
7. The non-transient computer readable medium of claim 6, wherein forming fins at the first and second portions of the wafer comprises forming fins having a first height at the first portion of the wafer and forming fins having a second height, less than the first height, at the second portion of the wafer.
8. The non-transient computer readable medium of claim 6, wherein etching the surface comprises performing a wet etch or performing a dry etch or performing both a wet etch and a dry etch.
9. The non-transient computer readable medium of claim 6, the actions further including forming a finFET device using the fins.
US14/849,506 2013-03-05 2015-09-09 Method of forming finfet having fins of different height Abandoned US20150380257A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150132910A1 (en) * 2013-03-11 2015-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET Device Structure and Methods of Making Same
US10068902B1 (en) 2017-09-26 2018-09-04 Globalfoundries Inc. Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385023B1 (en) * 2015-05-14 2016-07-05 Globalfoundries Inc. Method and structure to make fins with different fin heights and no topography
US11017999B2 (en) 2016-10-05 2021-05-25 International Business Machines Corporation Method and structure for forming bulk FinFET with uniform channel height
US10134760B2 (en) 2017-01-10 2018-11-20 International Business Machines Corporation FinFETs with various fin height
US10096524B1 (en) 2017-10-18 2018-10-09 International Business Machines Corporation Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors
US11374126B2 (en) * 2018-09-27 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET structure with fin top hard mask and method of forming the same

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965221A (en) 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions
JPH07245306A (en) 1994-01-17 1995-09-19 Sony Corp Method for flattening film of semiconductor device
WO1997017729A1 (en) 1995-11-10 1997-05-15 Advanced Micro Devices, Inc. Silicon dioxide spacer for locos or recessed locos
KR100209367B1 (en) 1996-04-22 1999-07-15 김영환 Insulating film forming method of semiconductor device
US5834360A (en) 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US6118167A (en) 1997-11-13 2000-09-12 National Semiconductor Corporation Polysilicon coated nitride-lined shallow trench
JP2004214379A (en) * 2002-12-27 2004-07-29 Toshiba Corp Semiconductor device, method for manufacturing the same dynamic type semiconductor storage device,
US6909147B2 (en) 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6977194B2 (en) * 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US6970372B1 (en) * 2004-06-29 2005-11-29 International Business Machines Corporation Dual gated finfet gain cell
US7638381B2 (en) * 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
US7709303B2 (en) 2006-01-10 2010-05-04 Freescale Semiconductor, Inc. Process for forming an electronic device including a fin-type structure
GB0605096D0 (en) 2006-03-14 2006-04-26 Bmg Designs Ltd Improvements in and relating to rf welding
US20070257319A1 (en) 2006-05-05 2007-11-08 Texas Instruments Incorporated Integrating high performance and low power multi-gate devices
US7544994B2 (en) 2006-11-06 2009-06-09 International Business Machines Corporation Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure
US7470570B2 (en) * 2006-11-14 2008-12-30 International Business Machines Corporation Process for fabrication of FinFETs
US7560785B2 (en) * 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
US20090057846A1 (en) 2007-08-30 2009-03-05 Doyle Brian S Method to fabricate adjacent silicon fins of differing heights
US7994020B2 (en) * 2008-07-21 2011-08-09 Advanced Micro Devices, Inc. Method of forming finned semiconductor devices with trench isolation
US8039326B2 (en) * 2009-08-20 2011-10-18 Globalfoundries Inc. Methods for fabricating bulk FinFET devices having deep trench isolation
US8211772B2 (en) * 2009-12-23 2012-07-03 Intel Corporation Two-dimensional condensation for uniaxially strained semiconductor fins
US8492839B2 (en) 2010-08-24 2013-07-23 International Business Machines Corporation Same-chip multicharacteristic semiconductor structures
US8497198B2 (en) * 2011-09-23 2013-07-30 United Microelectronics Corp. Semiconductor process
US9117877B2 (en) * 2012-01-16 2015-08-25 Globalfoundries Inc. Methods of forming a dielectric cap layer on a metal gate structure
US8361894B1 (en) 2012-04-04 2013-01-29 Globalfoundries Inc. Methods of forming FinFET semiconductor devices with different fin heights
US8697515B2 (en) * 2012-06-06 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US8927432B2 (en) 2012-06-14 2015-01-06 International Business Machines Corporation Continuously scalable width and height semiconductor fins

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150132910A1 (en) * 2013-03-11 2015-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET Device Structure and Methods of Making Same
US9379220B2 (en) * 2013-03-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device structure and methods of making same
US10068902B1 (en) 2017-09-26 2018-09-04 Globalfoundries Inc. Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method

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US9159576B2 (en) 2015-10-13
US20140252474A1 (en) 2014-09-11

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