TW201721757A - Semiconductor devices including a recessed isolation fill, and methods of making the same - Google Patents

Abstract

Technologies for manufacturing semiconductor devices including isolation structures having a recessed isolation fill are disclosed. In some embodiments the technologies include methods for forming a recessed isolation fill within an isolation trench that electrically isolate at least two active transistor gates from one another. In further embodiments, methods for forming local interconnects in the isolation trench are also disclosed. Semiconductor devices including active transistors isolated by a recessed isolation fill and systems including such devices are also described.

Description

Semiconductor device including recessed isolation filling and method of fabricating the same

The present disclosure is generally related to semiconductor devices and, more specifically, to semiconductor devices including recessed isolation fills. Methods of making such devices are also set forth.

In the past few decades, feature scaling has become the driving force behind the production of integrated circuits in the semiconductor industry. Shrinking features to smaller and smaller sizes enables the production of devices to include a larger number of functional units within the limited wafer area of the semiconductor wafer. For example, reducing the size of the transistor may allow an increased number of memory devices to be placed within a given area of the semiconductor wafer, resulting in the production of a memory device with increased storage capabilities. However, shrinking feature sizes can also lead to challenges during manufacturing that are difficult to solve in some situations.

In the manufacture of integrated circuit devices, as gate sizes continue to shrink, multi-gate transistors such as three-gate transistors have become more widely used. In some processes, the so-called "replacement gate" can be used. Processing to form a single and multiple gate transistors (such as a three-gate transistor) in which a dielectric material is used to form a dummy gate during the relatively early stages of manufacturing integrated circuit processing Dummy gate. In many instances, the imitation gate acts as a placeholder for later active or inactive gate structures, and in some cases, can also act during various etches or other processing periods. A mask that is executed to form other features of a device. In any event, the imitation gate is typically removed at some point during the manufacturing process and replaced with an active or inactive gate structure as desired. For example, the imitation gate can be removed and replaced with a conductive material to form an active gate channel for a triple gate and/or other fin transistor.

While replacement gate processing has proven to be an effective technique for forming single and multiple gated crystal systems, there are a number of challenges as the device configuration continues to evolve. Aspects of the present disclosure are directed to addressing at least some of these challenges.

100‧‧‧ method

101‧‧‧ squares

103‧‧‧ square

105‧‧‧ square

107‧‧‧ squares

109‧‧‧ square

111‧‧‧ squares

113‧‧‧ squares

117‧‧‧ square

119‧‧‧ square

121‧‧‧ square

123‧‧‧ square

125‧‧‧ square

127‧‧‧ squares

129‧‧‧ square

131‧‧‧ square

200‧‧‧ starting structure

202‧‧‧Substrate

204‧‧‧Fin

2041~204z‧‧‧Fin

206‧‧‧Isolated dielectric layer

208‧‧‧

2101~210n‧‧‧Imitation gate

212y‧‧‧Source/Bungee Trench

214‧‧‧ source/bungee area

216‧‧‧ spacer

218‧‧‧etch stop layer

220‧‧‧Source/bungee contacts

250‧‧‧Workpieces

301 ₁ ~ 301 _n ‧‧ ‧ gate trench

305‧‧‧Used gate trench

310‧‧‧Isolation trench (inactive gate trench)

315‧‧‧ first hard mask

320‧‧‧Second hard mask (inactive gate trench)

325‧‧‧ photoresist layer

330‧‧‧Isolated area

335‧‧‧ cushion

340‧‧‧Isolation materials

341‧‧‧Isolated dielectric

345‧‧‧ surface

350‧‧‧Work function material

355‧‧‧Dielectric filling

400‧‧‧Semiconductor device

500‧‧‧ computing device

501‧‧‧Multi-gate transistor (current transistor)

502‧‧‧ Motherboard

503‧‧‧Local interconnection

504‧‧‧ processor

506‧‧‧Communication Circuits (COMMS)

A‧‧‧ plane

B‧‧‧ District

C‧‧‧ District

The features and advantages of the embodiments of the present invention will be apparent from the following detailed description and the drawings.

1 is a flow diagram of operations consistent with an exemplary embodiment of a method of forming a semiconductor device including recessed isolation fill consistent with the present disclosure.

2A-2I illustrate, step by step, the formation of work consistent with embodiments of the present disclosure Perspective and cross-sectional views of various operations in the method of the piece.

3A-3N illustrate, in a step-by-step manner, cross-sectional views of various operations in a method of forming a semiconductor device including recessed isolation fills consistent with the present disclosure.

4 is a top plan view showing an example of a layout of a plurality of fin transistors in an integrated circuit device in accordance with an embodiment of the present disclosure.

5 is a block diagram of a computing device consistent with embodiments of the present disclosure.

SUMMARY OF THE INVENTION AND EMBODIMENTS

As mentioned in the prior art, at some point, a replacement gate process is used to produce, for example, single and multiple gate transistors (eg, three gate transistors), fin field effect transistors (FINFETS), combinations thereof And similar semiconductor devices. In such a process, a dielectric material is deposited and patterned in a relatively early stage of production of the device to produce a mimetic gate. In addition, the imitation gate can act as a placeholder for the transistor gate formed at a later stage of the process. For example, after forming a gate, it may be replaced with an active gate structure. The use of this technique can limit or avoid damage to the active gate structure, which can be adversely affected by the processing steps performed prior to forming the imitation gate and prior to forming the active gate structure.

As device sizes continue to shrink and device configurations continue to evolve, interest in mass production of FINFETS and other semiconductor devices using replacement gate technology has also grown. In view of this, a process of forming one or a plurality of long fin portions (hereinafter referred to as "main fin portion" or "multiple main fin portions") from a substrate has been developed. Each of the main fins may include (or may be processed to include) a plurality of source, drain and channel regions such that a plurality of active transistors are formable From the same main fin.

Before or after the source, drain and channel regions are formed, a layer of dielectric material can be deposited on the main fins in large quantities and patterned to form one or more trenches in the dielectric material (eg, , the source bungee trenches are separated by a plurality of imitation gates. A source/drain contact can then be formed in the trench. For example, the formation of the source/drain contacts can be accomplished by initially forming a spacer layer and an etch stop layer on the sidewalls of the trench in the dielectric material of the gate-like. Source/drain contacts (eg, metal or other conductive contacts) may then be formed in the trenches (eg, on the etch stop layer and/or the spacer layer).

After formation of the source/drain contacts, a subsequent operation can be performed to process the complex gates to form isolation regions between one or more active gates and/or active gates. In view of the latter, as noted above, one of the features described above is that it allows the active complex transistors to be formed on the common main fin. Because all or a portion of the main fin material may be electrically conductive, it is desirable to electrically isolate adjacent (or nearby) active transistors on the common main fin from each other, for example, to limit and/or Or avoid potential electrical shorts between such devices.

In several alternative gate treatments, electrical isolation between active transistors on a common main fin can be accomplished by removing individual or relatively small amounts of imitation gates; etching removal at (one or more) A portion of the underlying fin of the imitation gate has been removed; and the resulting structure is filled with an insulating (dielectric) material. For example, by masking the imitation gate to be retained and subjecting the imitation gate to be removed to dry etching chemistry, the selection of the imitation gate can be completed. In addition, dry etch chemistry is designed to remove the dielectric material of the target-like gate and to remove a portion of the fin material that is the exposed target-like gate. The result of such etching may correspond to the formation of an isolation trench of one of the removed imitation gates (also referred to herein as a target imitation gate), and is located under the target imitation gate. The formation of an isolation region in a portion of the fin. After dry etching, a dielectric material such as nitride may be deposited to fill the isolation region and the isolation trench. Thereafter, the remaining imitation gate can be removed to form a corresponding active gate trench, and an operation or the like can be performed to form an active gate therein.

While the above described processes are effective for forming semiconductor devices including a plurality of active transistors that are electrically isolated from each other along a common main fin, their use may present several challenges. For example, the dry etch chemistry used to remove the selected (ie, target) imitation gate and form an isolation region in one of the fins under such imitation gate may not be the source used for the device. The spacers and/or etch stop layers of the pole/drain contact regions are highly selective and may be similar (eg, adjacent) to the target imitation gate. In fact, in some examples, the dry etch chemistry can remove at least a portion of the spacer and/or etch stop layer that is close to the source/drain contacts, which can negatively impact device operation. In some cases, this lack of selectivity may be reflected by the "flaring" of the isolation trench (eg, near a surface thereof), and the corresponding flaring of the dielectric (eg, nitride) fill It is formed in succession.

Additionally, as noted above, a number of imitation gate treatments may completely fill the isolation regions and isolation trenches with dielectric material prior to the removal of the remaining imitation gates and subsequent execution of the source/drain junction formation operations. Result in Forming local interconnects in isolation trenches formed in previous processes is difficult and/or impractical. As such, local interconnects are receiving attention, which may be considered a material limitation for many alternative gate processes such as the replacement gate processing described above.

With only the foregoing, one aspect of the present disclosure relates to a method of forming a semiconductor device including one or more single or multiple gate transistors, wherein such devices include isolation trenches including recessed isolation fills. It will be apparent from the following discussion that the techniques discussed herein can enable the production of semiconductor devices including one or more interconnects (hereinafter referred to as "local interconnects") in isolation trenches. As such, the methods described herein can facilitate or otherwise enable the production of semiconductor devices including such local interconnects.

Reference is therefore made to Fig. 1, which is a flow diagram of an exemplary operation in accordance with an embodiment of the present disclosure. For convenience and understanding, it should be noted that the specific operation of the method of FIG. 1 will be described in conjunction with FIGS. 2A-2I, which are shown in steps, and other specific operations of FIG. 1 will be described in conjunction with FIGS. 3A-3N. . More specifically, reference will be made to Figures 2A-2I for a step-by-step production of an example of a work piece that can be used in accordance with the present disclosure. Rather, reference is made to Figures 3A-3N for a step-by-step production of an example of a semiconductor device consistent with the present disclosure, starting with the workpiece shown in Figure 2I.

It should be understood that FIGS. 2A-2I and 3A-3N are merely illustrative, and the geometry, size, and/or general configuration of the semiconductor device shown in FIG. 2I and the semiconductor device shown in FIG. 3N are merely exemplary. The purpose. As can be appreciated by those of ordinary skill in the art, the methods described herein are not limited to a particular workpiece structure (or method of producing the same), or are not limited to a particular semiconductor device structure. . In addition, should The elements of FIGS. 2A-2I and 3A-3N are not to scale, and are presented in a ratio that is intended to facilitate the understanding of the particular structure of the particular work and semiconductor device in accordance with the present disclosure.

Returning to Figure 1, method 100 can begin with block 101. The method continues to optional block 103, according to which a work piece (e.g., device precursor) can be provided. As used herein, the terms "workpiece" and "device precursor" are used interchangeably to refer to a structure that can be processed to form a semiconductor device, such as, but not limited to, one or more single or multiple gates. A semiconductor device of a transistor (eg, one or more FINFETS). In several embodiments and as will be explained below, the methods described herein may form or otherwise use a work piece consistent with the structure of Figure 2I, which will be described later. As noted above, the methods of the present disclosure are not limited to the use of work pieces consistent with FIG. 2I, and can be used with and/or with any suitable work piece. Without limitation, in several embodiments, the work piece can be used to form a plurality of single or multiple gate transistors along a common main fin (eg, via a replacement gate process).

It is also emphasized that the method of the present disclosure is not conditioned on any particular method of providing a work piece. As such, it should be understood that block 103 is optional and that the work piece can be provided in any suitable manner. For example, the present disclosure contemplates embodiments in which appropriate work pieces are obtained in some other manner (eg, from different manufacturing processes, via purchases from third parties, etc.). In such cases, the operation of block 103 can be omitted and the method can proceed directly from block 101 to block 105. However, for the benefit of completeness and to facilitate understanding of the techniques described herein, this disclosure will Continuing with an example of a work piece that can be used, reference is made to Figures 2A-2I.

In view of the above, the operation of optional block 103 may begin with the provision of a starting structure that may be suitable for forming one or a plurality of fin-type semiconductor devices, such as one or a plurality of FINFETs. As an example of such a structure, reference is made to Figure 2A which depicts the starting structure 200. As generally shown in the illustrated embodiment, the starting structure 200 includes fins 204 (eg, three-dimensional semiconductor bodies) formed over the substrate 202. For ease of understanding, the starting structure 200 is shown to include a single fin 204, although it should be understood that a plurality of fins can be included. In any event, the starting structure 200 further includes an isolating dielectric layer 206 that can serve as the isolation fin 204, for example, with a phase that can be included or otherwise formed in/on the starting structure 200. The adjacent fins or other structures are isolated.

In various embodiments and as generally shown in FIG. 2A, substrate 202 can be a bulk semiconductor substrate and fins 204 can be formed therefrom. In view of this, the substrate 202 (and thus the fins 204) can be formed of any suitable material for the substrate and/or fins of the semiconductor device, and is particularly suitable for use as, for example, FINFETs and/or other single or multiple gates. A non-planar transistor of a crystal. Thus, non-limiting examples of suitable materials that can be used as the substrate 202 and the fins 204 include germanium (Si), germanium (Ge), germanium (SiGe), tantalum carbide (SiC), sapphire, III-V compounds. Semiconductors, silicon-on-insulator (SOI) substrates, combinations thereof, and the like. Without limitation, in several embodiments, substrate 202 and fins 204 are formed from or include single crystal germanium, which may or may not be strengthened.

The fins 204 can have any suitable size, and in several embodiments It can be normalized so that a plurality of semiconductor devices such as FINFETs can be formed thereon. That is, the fins 204 can be relatively long main fins such that they can support a plurality of single or multiple gate transistors. In such cases, some or all of the plurality of semiconductor devices may be electrically isolated from one another, for example, electrically isolated in a manner consistent with the present disclosure.

The isolation dielectric layer 206 may be comprised of a material suitable for electrically isolating or helping to isolate the semiconductor device formed on the fin 204, and in particular, a permanent gate structure to be formed on the fin 204. The underlying portion of the substrate 202 is isolated. Non-limiting examples of suitable materials that can be used or used to isolate dielectric layer 206 thus include such as cerium oxide, cerium nitride, cerium oxynitride, carbon doped cerium nitride, combinations thereof, and the like. Electrical material.

The isolating dielectric layer 206 can be formed in any suitable manner. For example, the isolation dielectric layer 206 can be formed by depositing a bulk layer of one of the dielectric materials; the dielectric layer is then recessed to expose at least a portion of the fins 204. Rather, other methods of forming the isolation dielectric layer 206 can also be used and contemplated by the present disclosure.

Referring to FIGS. 2B-2D, operation of the optional block 103 can continue to the fabrication of a plurality of dummy gate structures orthogonal to the fins 204 and disposed over at least a portion of the isolation dielectric layer 206. Most preferably shown in Figure 2B, the formation of a dummy gate structure can be initiated by a plurality of layers 208 of deposited dielectric material. Following such a large amount of deposition and best shown in Figure 2C, layer 208 can be patterned (e.g., via lithography or another suitable method) to form a plurality of imitation gates 210 _{1 -} 210 _n , where n An integer greater than or equal to two. In some cases, n is at least greater than or equal to three. In such cases, it should be understood that at least three imitation gates are provided.

For purposes of illustration, the present disclosure is directed to embodiments in which layer 208 and imitation gates 210 _{1 -} 210 _n are formed from polysilicon, although it should be understood that other materials may be used. For example, in several embodiments layer 208 and imitation gates 210 _{1 -} 210 _n are comprised of any material suitable for removal by replacement gate and/or isolation trench formation operations, as described in more detail below. In view of this, exemplary materials that can be used to form the imitation gates 210 _{1 -} 210 _n include polycrystalline germanium, amorphous germanium, germanium dioxide, tantalum nitride, or a combination thereof. Without limitation, in some embodiments, layer 208 and imitation gates 210 _{1 -} 210 _{n are} each formed of polysilicon.

Referring now to Figure 2D, there is shown a cross-sectional view of Figure 2C extending vertically through plane F along plane A and in region B, i.e., the cross-sectional view having imitation gates 210 _{1 -} 210 _n extending into and out of the page. As shown, patterned layer 208 may result in a plurality of source / drain trench 212 of the production of _y, where y is an integer equal to or greater than the line 1. At this stage, doped tips and/or source/drain regions 214 may be formed in or on the fins 104, for example, using the dummy gates 210 _{1 -} 210 _n as a mask. Alternatively, the source/drain regions 214 may be formed in the fins 104 at another time, for example, prior to deposition of the dielectric material layer 208.

In several embodiments, parts of the production work may proceed to the source / drain trench 212 _y of forming a gate spacer structure. In general, the gate spacer structure can be configured or facilitate to electrically isolate or connect the permanent gate structure (eg, its replaceable gates 210 _{1 -} 210 _n ) to adjacent gate contacts ( For example, it may be formed in a source / drain trench 212 _y) is isolated. Additionally, the gate spacer structure can isolate the gate contact to the source/drain regions on or in the fins 104. Furthermore, all or a portion of the gate spacer structure can serve as an etch stop for protecting a particular component (eg, a later formed source/drain junction) during an etch operation that can be performed later in the process.

For purposes of illustration, the present disclosure will focus on the formation of a gate spacer structure that includes multiple layers (ie, spacer layer 216 and etch stop layer 218). However, it should be understood that the use of a multilayer spacer is not required and any suitable gate spacer structure can be used. The present disclosure contemplates embodiments in which a gate spacer structure comprising one, two or more layers is used, wherein at least one of the layers is electrically insulating.

Turning now to Figure 2E, in the illustrated embodiment, the production of the gate spacers can begin by depositing a spacer layer 216 over the structure of Figure 2D. In general, the spacer layer 216 can be configured to separate post-formed gate contacts from other components of the device, such as one or more source drain regions. In view of this, the spacer layer 216 can be formed from any suitable processing and materials. Non-limiting examples of suitable materials that can be used to form spacer layer 216 include, for example, but not limited to, carbides, nitrides of tantalum carbide, tantalum nitride, tantalum oxide, carbon doped tantalum nitride, combinations thereof, and the like. And oxides. Without limitation, the spacer layer 216 is carbon doped tantalum nitride (SiCN) in some embodiments.

After its deposition, an etch or other selective removal process (eg, lithography) may be performed to remove the spacer layer 216 from the horizontal surface of FIG. 2E. This concept is shown in FIG. 2F, which describes sidewall spacer layer 216 of electrode 210 _n extending along the simulated brake down, but it is removed over a surface electrode lines 210 ₁ -210 _n fin 204 and gate simulation. For example, this can be accomplished by exposing the structure of FIG. 2E to wet or dry etch chemistry that non-homogeneously etches the spacer layer 216, but with respect to the imitation gates 210 _{1 -} 210 _n and the source/deuterium The material of the polar region 214 is selective.

At this point in time, the production of the gate spacer structure can continue until an etch stop layer is formed over the structure of FIG. 2F. In view of this, referring to FIGS. 2G and 2H, the formation of the etch stop layer 218 is shown step by step. Independently or in conjunction with spacer layer 216, the etch stop layer 218 may act to the source / drain terminals (which may be formed later on the source / drain trench 212 _y) is replaced with a simulation may be used for the gate The conductive material in the active gate structure of one or more of the poles 210 _{1 -} 210 _n is electrically isolated. In addition, the etch stop layer 218 can include or be formed from a material that is unaffected or substantially unaffected by the etch chemistry that will be used later, for example, in accordance with the formation of a semiconductor that includes a recessed isolation including the recesses consistent with the present disclosure. The device is processed to remove the imitation gates 210 _{1 -} 210 _n .

Non-limiting examples of materials that may be used or included in the etch stop layer 218 include, for example, but are not limited to, tantalum carbide, tantalum nitride, hafnium oxynitride, carbon doped tantalum nitride (SiCN), combinations thereof, and the like. Metal carbides, nitrides and oxynitrides. In some embodiments, etch stop layer 218 and spacer layer 216 are formed from the same or different dielectric materials. Unrestricted, in some cases the etch stop layer 218 is formed from a second dielectric material; the spacer layer 216 is formed from the first dielectric material; and the first and second dielectric materials are the same or each other different. For example, in some cases the interval Layer 216 is tantalum nitride or carbon doped tantalum nitride (SiCN), and etch stop layer 218 is carbon doped tantalum nitride (SiCN) or other dielectric material.

As shown in FIG. 2G, the formation of the etch stop layer 218 can deposit a large amount of material of the etch stop layer 218 over the structure of FIG. 2F, such as via chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, and the like. Come start. After such deposition, polishing or other suitable processing may be used to remove portions of etch stop layer 218 and spacer layer 216 on the upper surface of imitation gates 210 _{1 -} 210 _n . For example, in some cases, the structure of FIG. 2G can undergo chemical mechanical planarization to remove etch stop layer 218 and spacer layer 216 from the upper surface of imitation gates 210 _{1 -} 210 _n , which results in FIG. 2H The structure shown.

At this stage, the production of the workpiece can continue until a source/drain junction 220 is formed between the gates 210 _{1 -} 210 _n and the etch stop layer 218. The location and structure of the contacts 220 may be layout dependent. In some cases, the source/drain contacts 220 may be formed by deposition and planarization of a conductive material such as a metal, a metal alloy, and/or a metal semiconductor alloy. Alternatively or additionally, one or more of the source/drain contacts 220 may be a dummy junction, which is comprised of a dummy dielectric material that will later be replaced with a conductive material.

In any event, the result of such an operation may be the production of work piece 250, which may have the structure shown in Figure 2I. More specifically and shown in the embodiment of FIG. 2I, the workpiece 250 can include one or more fins 204, each of which can include a plurality of source drain regions 214, a plurality of source/drain contacts 220, and a plurality of imitation gates 210, wherein each of the source/drain contacts 220 is formed on each of the plurality of source/gate regions 214, and at least two of the source/gate contacts 220 are patterned by imitation At least one of the gates 210 _{1 -} 210 _n is separated. Further, further shown in the embodiment of FIG. 2I, the source/drain contact 220 may have a top surface, a bottom surface, and first and second sidewalls (not labeled), and the workpiece 250 may further include the first and An etch stop layer 218 between each of the second sidewalls and a corresponding sidewall of the gate. In some embodiments and further shown, in some embodiments at least a portion of the etch stop layer 218 may also be present at the bottom surface of the source/drain junction and the fin 204 (or more specifically, the source/ The bungee region 214) is between the upper surfaces. Finally, and as shown, the workpiece 250 in some embodiments can include a spacer layer 216 between the etch stop layer 218 and one or more sidewalls of the gate.

Returning to Figure 1, the operation of the optional block 103 can be considered complete when a work piece such as work piece 250 is provided. Successively, as described below, operations can be performed to form a semiconductor device including recessed isolation fill. It should be noted that for purposes of illustration, the present disclosure will continue to describe an exemplary method in which operation is performed from the workpiece 250 of FIG. 2I to form a semiconductor device consistent with the present disclosure. Again, the use of work piece 250 is not required, and the techniques, and particularly the methods described herein, can be suitably applied to produce semiconductor devices having recessed isolation fills from work pieces having different configurations.

Method 100 may continue from block 103 to block 105 following the supply of work piece 250 or another suitable work piece. According to block 105, operations can be performed to remove the imitation gates 210 _{1 -} 210 _n . Such removal may be performed in any suitable manner, such as via etching or other suitable processing that selectively removes the material of the gates 210 _{1 -} 210 _n while leaving the remaining components of the workpiece 250 substantially unaffected. For example, in the case where the dummy gates 210 _{1 -} 210 _{n are} formed from the polysilicon or in the case where the dummy gates comprise polysilicon, the etching can be selectively performed by the material of the spacer layer 216 and the fin 204. The polysilicon is etched chemically or heterogeneously to complete the removal of the imitation gates 210 _{1 -} 210 _n in a large amount. For example, dry chloride (CL ₂ ) or hydrogen bromide dry etching can be performed initially, followed by wet etching with tetramethylhydrogen peroxide (TMAH) to remove the material of the imitation gates 210 _{1 -} 210 _n . Understandably, this is different from several other alternative gate methods in which the selected imitation gate is removed only by, for example, dry etching. That is, the operation of block 105 can be understood to result in the removal of all or substantially all of the imitation gates 210 _{1 -} 210 _n compared to one or relatively less imitations as performed in other alternative gate processes. Selective removal of the gate.

It should also be appreciated that in some embodiments, the use of wet chemical etching can impart a highly selective removal of polysilicon (or other materials of the gates 210 _{1 -} 210 _n ) without removal or substantial removal. Or does not otherwise affect other materials in the structure. For example, the use of highly selective wet etching at this stage can enable substantial removal of the imitation gate 210 _{1 -} 210 _n material without affecting or substantially affecting the spacer layer 216 , the etch stop layer 218 , or The quality and/or structure of the combination. This may be evidenced by the lack of or relatively lacking of the spacer layer 216, the etch stop layer 218, or a combination thereof (eg, near the surface of the source/drain junction 220).

In any event, removal of the imitation gates 210 _{1 -} 210 _n may result in the production of a plurality of gate trenches 301 _{1 -} 301 _n (as shown in FIG. 3A), where n is an integer greater than or equal to two. In the present embodiment, the gate trenches 301 _{1 -} 301 _n may expose the upper surface (not labeled) of the fin 204.

Returning to Figure 1, after the above operation, the method can continue from block 105 to block 107, according to which a mask can be deposited on the structure of Figure 3A. One use of the mask is to protect the active gate trench region (i.e., it can completely support a portion of the active gate of the active gate of the single or multiple gate transistors) during other processing steps. With this in mind, the mask can include one or more layers. For example, shown in FIG. 3B (which may be an enlarged view of area C of FIG. 3A), in some embodiments, operation of block 107 may include forming a first hard mask 315, second on the exposed surface of the structure of FIG. 3A. A hard mask 320 and a photoresist layer 325.

As will be apparent from the following description, one of the first hard masks 315 functions to protect the active gate trenches 305 while performing other operations on the inactive gate trenches 310, which may be adjacent to each other. Or otherwise close to each other. For purposes of illustration, various figures are shown and the disclosure focuses on embodiments in which the active gate trench 305 is adjacent to the inactive gate trench 320. It should be appreciated that such a configuration is not required, and the configuration of the inactive gate trench region 320 and the active gate trench region 315 may be layout dependent.

In any event, the first hard mask 315 can be formed from any suitable hard mask material. In some embodiments, the first hard mask 315 can be a metal hard mask, such as comprising or from tantalum, niobium, tungsten, tantalum, molybdenum, niobium, nitrides thereof, carbides thereof, oxides thereof, or combinations thereof The hard mask formed by the etc. Alternatively or additionally, in some embodiments, the first hard mask 315 is carbon Hard mask (CHM). Without limitation, in several embodiments, the first hard mask 315 is a CHM, such as a CHM that can be removed via plasma ashing (eg, chlorine or oxygen plasma ashing).

The first hard mask 315 can be deposited, for example, by any suitable means, such as spin-on deposition, sputtering, chemical vapor deposition, atomic layer deposition, combinations thereof, and the like. Without limitation, in some embodiments, the first hard mask 315 is a carbon hard mask deposited by spin-on deposition.

The second hard mask layer 320 can also be formed from any suitable hard mask material such as, but not limited to, a material suitable for the first hard mask 315. For example, in some cases, the second hard mask layer 320 can be formed from a second hard mask material, and the first hard mask 315 can be formed from the first hard mask material, wherein the first and second hard masks The materials may be the same or different. Without limitation, in some embodiments, the second hard mask layer 320 is formed from a hard mask material different from the first hard mask 315. For example, the first hard mask 315 can be a carbon hard mask, and the second hard mask 320 can be a hard mask (eg, anti-reflective coating (SiARC)), a nitride hard mask (eg, , tantalum nitride), combinations thereof, and the like.

It should also be understood that although FIG. 3B depicts the second hard mask layer 320 as a single layer of material, a plurality of second hard mask layers may be deposited on the first hard mask 315. The present disclosure contemplates embodiments in which the second hard mask layer 320 includes multiple layers of hard mask layers. For example, in some embodiments, the second hard mask layer 320 can include a nitride hard mask and a hard mask (eg, SiARC) formed on the upper surface of the first hard mask 315. In such cases, the nitride hard mask layer can be formed directly in some embodiments On the surface of the first hard mask 315, the germanium hard mask layer may be formed on the nitride hard mask layer. Alternatively, the tantalum hard mask layer may be formed directly on the surface of the first hard mask 315, and the nitride hard mask layer may be formed on the tantalum hard mask layer. Regardless of the structure of the second hard mask layer 320, the photoresist layer 325 may be deposited on the upper surface thereof.

In any event, operation of block 107 may result in the production of the structure shown in Figure 3B. As generally shown in the illustrated embodiment, the first hard mask 315 can extend beyond the upper surface of the source/drain junction 220 and into the gate trenches 301 ₁ -301 _n down to the fins 204 surface. The second hard mask layer 320 in this embodiment is deposited on the upper surface of the first hard mask 315. Finally, the photoresist layer 325 in this embodiment is formed on the upper surface of the second hard mask layer 320. As can be understood in the present embodiment, the first hard mask 315, the second hard mask layer 320, and the photoresist layer 325 are arranged in three layers, which can be used, for example, during the formation of the isolation regions in the isolation trenches. Protect specific areas of the work piece.

Returning to Figure 1, method 100 can continue from block 107 to block 109, according to which the photoresist layer and other mask layers can be patterned to expose one or more of the inactive gate trenches. In view of this, as noted previously, the full removal of the imitation gate 210 _{1 -} 210 _n material may result in the formation of a plurality of corresponding gate trenches 301 _{1 -} 301 _n , any of which may be used later as Trench for the active gate structure or trench for the isolation structure, which may be present between the active semiconductor devices on the same main fin. For clarity purposes, the gate trenches 301 _{1 -} 301 _n used to support the active gate are referred to herein as "active gate trenches", however those that are to be used to support the isolation structure are referred to herein. It is "Isolation trench". With only the above concepts, as shown in Figures 3B-3N, the present disclosure will focus on embodiments in which the active trenches 305 are placed in close proximity (e.g., adjacent) to the isolation trenches. It is to be understood that such discussion and description is for illustrative purposes, and other configurations are possible and contemplated by the present disclosure.

As shown in FIG. 3C, patterning of the photoresist layer 325 may begin in accordance with the operations of block 109 in some embodiments. For example, light development or other suitable processing may be performed to remove at least a portion of the photoresist layer 325 disposed over the isolation trench 310. This concept is best shown in Figure 3C, which shows the photoresist layer 325 being patterned such that at least a portion thereof has been removed from the area above the isolation trench 310.

3D and 3E, operation of block 109 may continue to selectively remove portions of second hard mask layer 320 from first hard mask 315 from regions above and/or in isolation trench 310. This may be done in a stepwise manner in some embodiments such that at least a portion of the second hard mask layer 320 over the isolation trench 310 is removed while leaving the first hard mask 315 unaffected or Substantially unaffected, the above is shown in Figure 3D. For example, it can be accomplished by exposing the structure of FIG. 3C to an etch chemistry that removes the material of the second hard mask layer 320, but to the photoresist layer 325 and the first hard mask 315 Selective. For example, in the case where the second hard mask layer 320 is a germanium-containing layer such as SiARC, the second hard mask layer can be etched by exposing the structure of FIG. 3C to a carbon tetrafluoride (CF ₄ ). The film is removed. In this case, the CF ₄ may also remove a portion of the photoresist layer 325, but the photoresist layer 325 may be thick enough that at least a portion thereof is retained, for example, over the active gate region 305. The remaining portion of the photoresist layer 325 can be used as a mask for selectively removing a portion of the second hard mask layer 320, and the first hard mask 315 can be used as an etch stop.

To continue the quarantine exposure of the isolation trenches 310, the method can continue to selectively remove the material of the first hard mask 315 from the isolation trenches 310. This concept is best shown in FIG. 3E, which shows an example in which the first hard mask 315 is selectively removed from the isolation trenches 310. For example, such removal can be accomplished by exposing the structure of FIG. 3D to wet or dry etch chemistry that removes the material of the first hard mask 315 (and in this case, the photoresist layer) 325), but it is selective to the material of the second hard mask 320 and the spacer layer 216. For example, when the first hard mask is a carbon mask (CHM), it can be removed by subjecting the structure of FIG. 3D to dry plasma etching, such as to remove the CHM while at the same time making the second hard mask The material of the membrane remains substantially unaffected by the oxygen plasma. In this way, the second hard mask 320 can serve as a mask for the underlying portion of the first hard mask 315, and the spacer layer 216 can function as an etch stop, resulting in the structure of FIG. 3E.

It should be understood that while the above discussion has focused on embodiments in which the photoresist layer 325, the second hard mask layer 320, and the first hard mask 315 are patterned in a stepwise manner to expose the isolation trench 310, such processing is Not necessarily and the patterning of such layers can be accomplished in any similar manner. For example, the present disclosure contemplates embodiments in which two or more such layers are simultaneously patterned. In any case, the result may be the production of a structure consistent with Figure 3E, that is, A structure in which the isolation trench 310 is exposed to the upper surface of the fin 204, but the remaining mask material (in this case, the remaining second hard mask layer 320 and the first hard mask 315) A plug is present on and/or in the active gate trench 305.

Returning to Figure 1, method 100 can continue from block 109 to block 111, according to which at least a portion of its fin 204 can be removed to form an isolation region therein. More specifically, operation according to block 111 may include selectively removing a portion of the fin 204 that is adjacent to the bottom of the isolation trench 310 that is exposed such that the isolation region 330 is formed therein, as best shown above in FIG. 3F. In view of this, selective removal of a portion of the fin 204 can be accomplished in any suitable manner. For example, in some embodiments, the structure of FIG. 3E can be exposed to wet or dry etch chemistry that is selective to the material of the second hard mask layer 320 and the spacer layer 216, but can be removed The material of the fins 204 is (eg, etched). In some embodiments, it may be by chlorides (Cl ₂₎ or hydrogen bromide (HBr) chemical etching to etch the structure of FIG. 3E is done, so that the selectively removed portion 204 of the fin material.

In any event, operation of block 111 may result in selective removal of fin 204 material (e.g., near the bottom of isolation trench 310), resulting in the formation of isolation region 330 as shown in Figure 3F. It will be appreciated that the depth of the isolation region 330 varies widely, and that it may form an active gate structure (eg, to be formed in the active gate trench 305) and others formed on the fins for the isolation structure to be formed therein. The extent to which 204 is electrically isolated from components or devices formed by fins 204 (e.g., adjacent or nearby transistors) is affected. Thus, in some embodiments, the isolation region has from about 40 to about The depth in the range of 200 nanometers (nm), such as from about 50 to about 200 nm, or even from about 70 nm to about 200 nm. Without limitation, in some embodiments, the isolation region has a depth that extends at least to a portion of the fin 204 and below the bottom of the active portion of the fin 204 (eg, below the source/drain region 214).

Returning to Figure 1, after operation of block 111, the method can continue to block 113, according to which a liner can be deposited on the structure of Figure 3F, for example, prior to removal of the second hard mask layer 320 or after that. For purposes of illustration, the present disclosure focuses on embodiments in which a liner is deposited after removal of the second hard mask layer 320. Thus, referring to FIG. 3G, an embodiment in which the spacer 335 is deposited on the first hard mask 315, the source/drain contact 220, the exposed surface of the spacer layer 216, and the surface of the isolation region 330 is illustrated. .

Generally, during the recess of the dielectric material, the liner 335 is configured to function as an etch stop, which may be deposited in the isolation trench 310 at a later stage of the processing described herein. That is, the liner 335 can be configured to provide a selective etch that is related to the material(s) that will be used to fill the isolation trench 310. For example, in some embodiments, the liner 335 can be formed from or include a material that is unreactive or substantially non-reactive to the etch chemistry that can be applied to remove the deposition that will be deposited on the isolation trench 310 Medium (eg, porous) dielectric material. In view of this, the liner 335 can be formed from or include any suitable etch stop material including, but not limited to, various metal oxides, nitrides, carbides, and combinations thereof (eg, cerium oxide, aluminum oxide (Al) ₂ O ₃ ), hafnium oxide (HfO ₂ ), carbon doped tantalum nitride, tantalum nitride, aluminum nitride, etc.). Without limitation, the liner 335 may be formed from aluminum oxide (Al ₂ O ₃ ) in some embodiments. In any event, the liner 335 can be deposited, for example, by any suitable means, such as various chemical deposition, physical vapor deposition, sputtering, atomic layer deposition, combinations thereof, and the like.

Returning to Figure 1, after operation of block 113, the method can continue to block 117, according to which an isolation material can be deposited on the structure of Figure 3G. Thus, referring to FIG. 3H, an illustrative embodiment in which spacer material 340 is deposited on the exposed surface of liner 335 is depicted. As shown in the illustrated embodiment, deposition of the isolation material 340 can be performed such that the isolation material 340 fills the isolation trenches 310 and the isolation regions 330 in the fins 204.

In general, the isolation trench 340 is a non-conductive (ie, insulating/dielectric) fill that acts or contributes to the active gate trench 305 (and the active gate structure that will be formed therein) One or more additional active gates are formed on the fins 204 or formed with the fins 204. Thus, the isolation material 340 can be or include any suitable non-conductive (dielectric material) such as, but not limited to, dielectric oxides, nitrides, and carbides. Without limitation, in some embodiments, the isolation material 340 can be or include a porous dielectric material such as, but not limited to, porous yttria (SiO), porous cerium oxide (SiO ₂ ), porous carbon doped nitriding. Bismuth (SiCN), porous niobium oxynitride, combinations thereof, and the like.

As used herein, the term "porous dielectric material" refers to a dielectric material having a deposition density of less than about 95% of the full density of the constituent materials. For example, the full density of both cerium oxide (SiO) and cerium oxide is about 2.65 grams per cubic centimeter (g/cm ³ ). Thus, for example, where the isolation material 340 is porous ruthenium oxide or porous ruthenium dioxide, the (eg, deposited) density of the isolation material 340 may be less than about 95% of about 2.65 g/cm ³ , ie, less than Or equal to about 2.52 g/cm ³ . In some cases, porous cerium oxide is used as the insulating material 340. As can be appreciated, in some embodiments, the porous dielectric may be capable of increasing density (eg, by annealing or other processing), such as increasing its density to greater than 95% of the full density of the constituent materials, resulting in an isolated dielectric. Formation.

Deposition of the isolation material 340 can be performed in any suitable manner. For example, where the isolation material 340 is porous ruthenium oxide or porous ruthenium dioxide, deposition of the isolation material 340 can be performed via conformal or non-conformal ruthenium deposition, as understood in the art. In any event, the result of such operation may be the formation of the structure shown in FIG. 3H, that is, wherein the isolation material extends at least from the bottom of isolation region 330 to a point near the opening of isolation trench 310.

At this point the resulting article can be optionally polished (eg, via chemical mechanical planarization or other suitable technique) to remove excess isolation material 340, such that the upper surface of isolation material 340 above isolation trench 310 is substantially The surface of the liner 335 above the gate trench 305 is now coplanar. Such polishing is not necessary, and the present disclosure will continue to be described with respect to embodiments in which such polishing is not performed for the sake of clarity.

Returning to FIG. 1, after operation of block 117, the method can continue to block 119, according to which the isolation material 340 can be recessed into the isolation trench 310. This concept is best shown in Figure 3I, which depicts being recessed The spacer material 340 is such that its upper surface is below the aperture (not shown) of the isolation trench 310.

In some embodiments, the isolation material 340 is recessed such that it has a depth d among the isolation trenches 310, wherein the depth d is defined as the distance between the upper surface of the isolation material 340 and the lowest point of the isolation region 330 . As can be appreciated from the discussion below, the depth of the isolation material 340 within the isolation trench 310 may affect the location of the local interconnect, which may be formed in the isolation trench 310. It is therefore desirable to recess the isolation material 340 such that it has a suitable depth d. For example, in several embodiments, the isolation material 340 can be recessed such that its upper surface is coplanar or substantially coplanar with the upper surface of the fin 204. This can be accomplished, for example, by recessing the isolation material 340 until it has a depth that is about 5% to about 15% greater than the depth of the isolation region 330. Thus, for example, where isolation region 330 has a depth of from about 40 to about 200 nm, isolation material 330 may have a depth (d) of from about 42 to about 220 nm, such as from about 45 to about 210 nm.

The depression of the isolation material 340 can be performed in any suitable manner, such as by etching or other selective removal processes. For example, in some embodiments, the isolating dielectric is or includes porous yttria or porous yttria, and by subjecting the structure of FIG. 3H to selectivity to the liner 335 but capable of removing the isolation material 340 Or dry etch chemistry to recess it in the isolation trench 310. In a non-limiting embodiment, the structure of FIG. 3H is exposed to a dry etch chemistry that is selective to pad 335 but non-homogenously etched to isolation material 340. Alternatively, the structure of FIG. 3H can be subjected to wetness that can remove the isolation material 340 but is selective to the liner 335 in a non-homogeneous or homogeneous manner. Etching chemistry.

Returning to Figure 1, after operation at block 119, the method can continue to block 121, according to which the liner 335 can be removed from the upper surface of the structure of Figure 3I and recessed into the isolation trench 310. This concept is best shown in FIG. 3J, which depicts the second isolation being removed from the upper surface of the first hard mask 315 and the source/gate contact 220 and recessed in the isolation trench 310. Layer 320. As shown in the illustrated embodiment, the liner 335 can be recessed into the isolation trench 310 such that its upper surface is substantially coextensive with the upper surface of the isolation material 340. Alternatively, in some embodiments, the liner 335 can be recessed into the isolation trench 310 such that its upper surface is over the upper surface of the isolation material 340. As can be appreciated, this avoids the need to further recess the isolation material 340 (or the isolation dielectric 340') at a later stage of the process, for example to facilitate deposition of the first work function material.

The depression of the liner 335 can be performed in any suitable manner. For example, in some embodiments, the recess of the liner 335 can be accomplished by exposing the structure of FIG. 3I to an etch chemistry that is selective to the first hard mask 315 and the spacer layer 216, but The material of the liner 335 is removed (eg, etched). For example, where spacer layer 216 is nitride and pad 335 is aluminum oxide, pad 335 can be formed in isolation trench 310 by exposing the structure of FIG. 3I to hydrofluoric acid etch chemistry. Depression. The use of hydrofluoric acid etching is not necessary, and other methods can be used to recess the liner 335 in the isolation trench 310.

Returning to Figure 1, after operation of block 121, the method can continue from block 121 to block 123, depending on which it can be used to expose the active gate trench. The operation of the slot. More specifically, an operation to remove all or a portion of the first hard mask 315 plug may be performed to expose the surface of the fin 204 at the bottom of the active gate trench 305. This concept is best shown in FIG. 3K, which shows an embodiment in which the first hard mask 315 is selectively removed to expose the surface 204 of the fin 204 near a portion of the bottom of the active gate trench 305. .

Removal of the first hard mask 315 can be accomplished in any suitable manner, such as via an etch process, an ion milling process, a plasma ashing process, combinations thereof, and the like. Without limitation, in some embodiments, the first hard mask 315 is a carbon hard mask (or other suitable material), and the operation of block 123 includes performing a plasma ashing process (eg, an oxygen plasma ashing process) The carbon hard mask is removed to expose the surface of the fins 204 in the active gate trenches 305.

After operation of block 123, the method can continue to optional block 125, according to which the density of the isolation material 340 can be selectively increased by, for example, annealing or other suitable processing. For example, in the case where the isolation material 340 is porous ruthenium oxide or porous ruthenium dioxide, an annealing treatment may be performed to increase the density of the porous oxidation/cerium oxide to more than 95% of its full density, resulting in the isolation dielectric 341. Formation.

After operation of block 125 (or if such operations are not required), method 100 may continue to block 127, according to which one or more local interconnects may be formed in isolation trench 310. As used herein, the term "local interconnect" refers to a conductive path that may extend between at least two isolation trenches in an integrated circuit device such that such trenches and/or other components of the energizable device Electrical connection. In view of this, refer to Figures 3L-3N, which follow the steps An example of a method of forming local interconnects in isolation trenches consistent with the present disclosure is shown.

As shown in FIG. 3L, in some embodiments, the formation of local interconnects can begin by isolating further recesses of isolation material 340 (or isolation dielectric 341) in trench 310. Alternatively, in the case where the upper surface of the spacer 335 is recessed in the isolation trench 310 such that the upper surface of the spacer 335 is over the upper surface of the isolation material/dielectric 340/341, the isolation material/dielectric Further depression of the mass 340/341 can be omitted. In either case, the result can be the formation of a cup in the isolation trench 310, wherein the cup includes sidewalls at least partially defined by the liner 335, and at least partially separated by a dielectric/dielectric The bottom of 340/341 is defined as shown in Figure 3L. Alternatively, in some embodiments, the formation of such a cup is not necessary and may be omitted.

After further recessing of the isolating material/dielectric 340/341 (or if such a recess is omitted), the formation of the local interconnect may continue until the working function material 350 is deposited in the cup (described above) Or deposited on the upper surface of the spacer 335 and the spacer/dielectric 340/341, for example, as shown in FIG. 3M. At the same time, the work function material can be deposited on the surface of the fin 204 of the inactive gate trench 305. As such, all or a portion of the active gate structure can be formed in the active gate trench 305, and a conductive material can be deposited in the inactive active gate trench 310 and used to form a local interconnect, such as Discussed.

The deposition of work function material 350 can be accomplished in any suitable manner. For example, the work function material 350 can be deposited in a large amount in the structure of FIG. 3L. The exposed surface. Successively, at least a portion of the plurality of deposited first work function materials 350 can be removed (eg, via etching) while at least a portion thereof remains in the active gate trench 305 and the inactive gate trench 310, As shown in Figure 3M.

Work function material 350 can be any suitable material for forming local interconnects and/or conductive gates in a semiconductor device. Non-limiting examples of such materials include, for example, metals (eg, titanium, tungsten, aluminum, tantalum, cobalt, copper), metal nitrides (eg, titanium nitride, tantalum nitride, etc.), metal carbides (eg, Titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), combinations thereof, and the like.

As shown in FIG. 3M, in some embodiments, the surface of the work function material 350 in the isolation trench 310 may be coplanar or substantially coplanar with the upper surface of the liner 335. In any case, the work function material 350 can be configured such that it can form a partial interconnection with a work function material in an adjacent or other nearby isolation or active gate trench, or form a local interconnect to the semiconductor. Among several other components of the device (for example, a gate voltage controller (VCG)).

In any event, after deposition of the first work function material 350, the method 100 may continue from block 127 to block 129, filling the active trench 305 with the isolation trench 310 according to its dielectric fill. This concept is illustrated in FIG. 3N, in which dielectric fill 355 is shown as being formed in active trench 305 and isolation trench 310 and is shown to have a surface with source/drain junction 220. Plane or substantially coplanar surface. This can be done in any suitable way, such as a large number of sinks The dielectric fills the material of 355 and selectively removes the first dielectric filled material present over the upper surface of the source/drain junction 220.

In any event, dielectric fill 355 can be formed from any suitable dielectric material such as, but not limited to, dielectric oxides, nitrides, carbides, combinations thereof, and the like. Non-limiting examples of such materials include tantalum nitride, carbon doped tantalum nitride (SiCN), niobium oxynitride, and hafnium oxide.

At this stage, the operations of method 100 can be considered completed, and the method can continue from block 129 to block 131 and end.

Another aspect of the present disclosure is directed to a semiconductor device including one or more single or multiple gate transistor elements having the structure shown in FIG. 3N. Without limitation, in some embodiments, a semiconductor device as described herein includes a main fin 204 including at least first and second active transistors formed thereon, wherein the first and second active transistors are Each includes an active gate trench including a gate structure and at least first and second gate contacts, the gate contacts being formed in the main fins corresponding to the first and second source/drain regions on.

Furthermore, the semiconductor device described herein can include an isolation structure formed on the main fin and between the first and second active transistors, wherein the isolation structure is used to electrically isolate the first active transistor from The second active transistor. In some embodiments, the isolation structure can include an isolation trench formed between the third and fourth gate contacts, wherein the isolation trench extends to an isolation region formed in the main fin. As noted above, in some embodiments, the isolation trench can be partially filled by recessing the isolation material. The upper surface of the recessed isolation material may be recessed below the aperture of the isolation trench.

In some embodiments, the isolation structure further includes an etch stop layer that is formed between the recess isolation material and the surface of the main fin, and also exists in the recess isolation material and the third and fourth source/drain electrodes Between the side walls of the point, as described above. Further as previously described, the first work function material may be present in the isolation trench (eg, in one of the cups defined by the etch stop layer and the upper surface of the recessed dielectric material). In some cases, the first work function material can be configured to function as a local interconnect, for example, between nearby transistors and/or other components of the semiconductor device. In a further embodiment, the isolation trench can also be filled with a first dielectric fill, for example, extending from the upper surface of the first working function metal to a region of the aperture proximate the isolation trench.

In an additional embodiment, the gate structure of each active transistor can include a second work function material that can be the same or different than the first work function material. Further in some embodiments, the gate structure can include a second dielectric fill formed over the upper surface of the second work function material. In some embodiments, the second dielectric fills at least a region that extends to a hole that is adjacent to the active gate trench. In some embodiments, the second dielectric fill is the same or different than the first dielectric fill, as noted above. Without limitation, in some embodiments, the second dielectric fill is formed from or includes a high-k dielectric.

Referring now to Figure 4, an example of a semiconductor device consistent with the present disclosure is described. As shown, the semiconductor device 400 includes a plurality of fins 204 _{1 -} 204 _z , where z is an integer greater than two. Each of the fins 204 _{1 -} 204 _z may be a main fin that includes or otherwise supports a plurality of active single or multiple gate transistors 501 , wherein at least two of the active transistors 501 are consistent with the present disclosure The isolation structure 502 is separated. That is, each of the active transistors 501 can include first and second source/drain contacts, and an active gate trench including an active gate structure, wherein the first and second sources/汲The pole contacts are formed over the individual source/drain regions of one of the fins 204 _{1 -} 204 _z as previously described. Similarly, each isolation structure 502 can include isolation trenches between the third and fourth source/drain contacts and the other, the isolation trenches including the isolation material/dielectric recessed therein, and formed in isolation The first work function material 350 on the material/dielectric is as described above. As shown in the embodiment of FIG. 4, a first work function material 350 can be used in some embodiments to form a local interconnect 503 that can electrically connect the active transistor 501 to, for example, a voltage gate control. (VGC) One or more additional components of the source. As can be appreciated, the use of local interconnect 503 can enable the active transistor 501 to traverse the connection of the nearby isolation structure to the VCG, which is not possible with previous lift gate techniques.

Another aspect of the present disclosure is related to a computing device including a semiconductor device consistent with the present disclosure. In view of this, reference is made to FIG. 5, which shows a computing device 500 in accordance with various embodiments of the present disclosure. As shown, computing device 500 includes a motherboard 502 that may include various components such as, but not limited to, processor 504, communication circuitry (COMMS) 506, any or all of which may be physically or electrically coupled to motherboard 502.

Depending on the application, computing device 500 may also include other components such as, but not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processors, digital Signal processor, cryptographic processor, chipset, antenna, display, touch screen controller, battery, various codecs, various sensors (eg, global positioning system (GPS), accelerometer, gyroscope, etc.), One or more speakers, cameras, and/or mass storage devices.

The COMMS 406 can be configured to enable wired or wireless communication for transferring data to the computing device 400. In some embodiments, the COMMS 406 can be configured to enable wireless communication via any of a number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX ( IEEE 802.16 family), IEEE 802.20, Long Range Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and others designated as 3G, 4G , 5G and any other wireless protocols after that.

Semiconductor devices such as those previously described may be included in integrated circuit dies that may be present in various components of computing device 500. For example, in some embodiments, processor 504 can include integrated circuit dies including a plurality of active single or multiple gate transistors formed on a common main fin, and using the isolation structure previously described, A plurality of active single or multiple gate electromorphic systems are electrically isolated from one another. Similarly, COMMS 406 can include integrated circuit dies that include one or more semiconductor devices consistent with the present disclosure. Moreover, various other memories of computing device 500 (eg, DRAM, ROM, mass storage, etc.) may be comprised of or include semiconductor devices consistent with the present disclosure.

Computing device 500 can be any of a wide variety of computing devices, Including but not limited to, laptop, easy network, notebook, ultra-note, smart phone, tablet, personal digital assistant (PDA), ultra-polar mobile PC, mobile phone, desktop computer, servo , printers, scanners, displays, set-top boxes, entertainment control units, digital cameras, portable music players, or digital video recorders, combinations thereof, and the like. Such devices are intended to be listed for purposes of illustration only, and computing device 500 can be any suitable type of action or fixed electronic device.

Additional embodiment

The following examples represent additional, non-limiting embodiments of the present disclosure.

Example 1: According to the present example, a method of forming a semiconductor device includes: removing the plurality of gates from a workpiece including a substrate, a main fin, and a plurality of imitation gates formed on the main fin. Forming a plurality of trenches; forming at least a first active gate trench, a second active gate trench, and an isolation trench from the plurality of trenches, the isolation trenches in the first and second active gates Between the trenches, wherein: forming the isolation trench includes forming an isolation region in the fin portion near a bottom of at least one of the plurality of trenches, and forming a recess isolation in the isolation trench and the isolation region a dielectric material; the isolation trench includes a hole; and the surface of the recess isolation dielectric is below the hole.

Example 2: This example includes any or all of the features of Example 1, and further includes forming a local interconnect among the isolation trenches.

Example 3: This example includes any or all of the features of Example 2, wherein the local interconnect includes a work function material.

Example 4: This example includes any or all of the features of Example 2, wherein the local interconnect has an upper surface below the aperture, and the method further includes filling the isolation trench with a dielectric fill.

Example 5: This example includes any or all of the features of Example 1, and further includes forming a liner between the isolation trench and the isolation region prior to forming the recessed isolation dielectric.

Example 6: This example includes any or all of the features of Example 5, wherein the liner comprises a metal oxide, a metal nitride, a metal carbide, or a combination thereof.

Example 7: This example includes any or all of the features of Example 2, and further includes forming an active gate structure in at least one of the first and second active gate trenches.

Example 8: This example includes any or all of the features of Example 7, wherein the active gate structure comprises a work function material.

Example 9: This example includes any or all of the features of any of Examples 7 and 8, wherein the upper surface of the active gate structure is below the aperture of the first or second active gate trench.

Example 10: This example includes any or all of the features of Example 9, further comprising filling the first or second active gate trench with a dielectric fill.

Example 11: This example includes any or all of the features of any of Examples 1 to 10, wherein the workpiece further comprises a plurality of source/drain contacts, wherein at least one of the source/drain contacts Between the first active gate trench and the isolation trench, and at least the source/drain contact One is between the second active gate trench and the isolation trench.

Example 12: This example includes any or all of the features of Example 11, wherein the workpiece further comprises a plurality of source/drain regions, wherein at least one source is formed under each of the plurality of source/drain contacts Polar/bungee area.

Example 13: This example includes any or all of the features of any of Examples 1 to 10, wherein: the workpiece further comprises a plurality of source/drain contacts and under the plurality of source/drain contacts Forming a plurality of source/drain regions; and forming the first active gate trench, the second active gate trench, and the isolation trench include: forming a mask in the plurality of trenches; and removing One portion of the mask is exposed to at least one of the plurality of trenches that will become the isolation trench, and the remaining portion of the mask protects the plurality of trenches of the first and second active gate trenches At least two of the grooves.

Example 14: This example includes any or all of the features of Example 13, wherein forming the mask comprises: depositing a first hard mask in the plurality of trenches; and depositing a second hard mask on the first hard mask .

Example 15: This example includes any or all of the features of Example 14, wherein the first hard mask is a carbon hard mask and the second hard mask is a hard mask.

Example 16: This example includes any or all of the features of Example 15, wherein the second hard mask is an anti-reflective coating.

Example 17: This example includes any or all of the features of any of Examples 13-16, wherein the workpiece further comprises a spacer formed on a sidewall of the plurality of source/drain contacts.

Example 18: This example includes any or all of the features of any of Examples 1 to 18, wherein forming the recessed isolation dielectric in the isolation trench and the isolation region comprises: the isolation trench and the isolation region Depositing an isolation material; and recessing the isolation material in the isolation trench to define the recess isolation dielectric.

Example 19: This example includes any or all of the features of Example 18, wherein the isolating material is a porous dielectric material.

Example 20: This example includes any or all of the features of Example 19, wherein the porous dielectric material is selected from the group consisting of porous yttria, porous cerium oxide, porous carbon doped lanthanum nitride (SiCN) , porous bismuth oxynitride, or a combination thereof.

Example 21: This example includes any or all of the features of any of Examples 19 to 20, wherein forming the recessed isolation dielectric further comprises annealing the porous dielectric material.

Example 22: This example includes any or all of the features of Example 22, wherein the annealing is performed after the isolation material in the isolation trench is recessed.

Example 23: This example includes any or all of the features of any of Examples 21 to 22, wherein the annealing increases the density of the porous dielectric material.

Example 24: According to this example, an integrated circuit device is provided, comprising: a main fin having a first active transistor, a second active transistor, and an isolation structure formed thereon; wherein: the isolation structure is Between the first and second active transistors, and for electrically isolating the first active transistor to the second active transistor; the isolation structure includes an isolation trench, the phase An isolation region formed in the fin portion near the bottom of the isolation trench, and a recess isolation dielectric in the isolation trench and the isolation region; the isolation trench has a hole; and the recess isolation dielectric The upper surface of the mass is below the hole.

Example 25: This example includes any or all of the features of Example 24, and further includes a local interconnect formed at least partially within the isolation trench.

Example 26: This example includes any or all of the features of Example 25, wherein the local interconnect comprises a work function material formed on the upper surface of the recessed isolation dielectric.

Example 27: This example includes any or all of the features of any of Examples 24-26, further comprising dielectric fill on the recessed isolation dielectric and in the isolation trench.

Example 28: This example includes any or all of the features of any of Examples 24 to 27, further comprising a liner in the isolation trench and the isolation region, at least a portion of the spacer is in the recess isolation dielectric Between the main fin and the main fin.

Example 29: This example includes any or all of the features of Example 29, wherein the liner comprises a metal oxide, a metal nitride, a metal carbide, or a combination thereof.

Example 30: This example includes any or all of the features of Example 24, wherein the first and second active transistors individually comprise first and second active gate trenches, wherein the first active gate trench is present A first active gate structure and a second active gate structure in the second active gate trench.

Example 31: This example includes any or all of the features of Example 30, The first and second active gate structures each comprise a work function material.

Example 32: This example includes any or all of the features of any of Examples 30 and 31, wherein: the first and second active gate structures individually have first and second upper surfaces; and the first and second active gates The pole trenches have respective first and second active gate trench holes; and the first and second upper surfaces are individually below the first and second active gate trenches.

Example 33: This example includes any or all of the features of Example 32, further comprising dielectric filling in the first and second active gate structures and in the first and second active gate trenches.

Example 34: This example includes any or all of the features of any one of Examples 24 to 33, wherein the first and second active transistors each further comprise a plurality of source/drain contacts, wherein the plurality of sources At least one source drain region is formed under each of the pole/drain contacts.

Example 35: This example includes any or all of the features of Example 34, further comprising spacers formed on sidewalls of the plurality of source/drain contacts.

Example 36: This example includes any or all of the features of any of Examples 24 to 35, wherein the isolating dielectric comprises a porous dielectric material having an increased density.

Example 37: This example includes any or all of the features of Example 28, wherein the upper surface of the recessed isolation dielectric is below the upper surface of the liner to isolate the upper surface of the dielectric by the recess And the liner to define a cup in the isolation trench.

Example 38: This example includes any or all of the features of Example 37. A step includes a local interconnect in the isolation trench, wherein at least a portion of the local interconnect is formed in the cup.

Example 39: This example includes any or all of the features of Example 38, wherein the local interconnect includes a work function material.

Example 40: This example includes any or all of the features of any of Examples 38 and 39, wherein the top surface of the local interconnect is below the upper surface of the liner or substantially opposite the upper surface of the liner The total plane.

Example 41: This example includes any or all of the features of any of Examples 25, 26, 38, and 39, wherein the local interconnect is coupled to a voltage gate control source.

The terms "above", "below", "between", and "upper" are used herein to refer to the relative position of a layer or component of a material relative to other layers or components. For example, a layer disposed on another layer (eg, above or above) or below (below) may be in direct contact with the other layer, or may have one or more interposers. Furthermore, a layer disposed between two other layers may be in direct contact with the two other layers or may be separated by one or more of the other layers, for example, by one or more intervening layers. Similarly, a feature adjacent to another feature may be in direct contact with the adjacent feature, or may be separated from the adjacent feature by one or more intervening features, unless explicitly indicated to the contrary. Conversely, the terms "directly above" or "directly below" are used to indicate that a layer of material is in direct contact with the upper or lower surface of another layer of material. Similarly, the term "directly adjacent" means that two features are in direct contact with each other.

The terms and vocabulary used herein are used to describe The terminology is not intended to be limiting, and is not intended to be used to exclude the equivalents (or parts thereof) of the features shown and described, and it should be understood that Within the scope of the application. Accordingly, the scope of the patent application is intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. It will be appreciated by those skilled in the art that such features, aspects, and embodiments may be combined with each other as well as variations and modifications. Accordingly, the present disclosure should be considered to include such combinations, changes, and modifications.

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Claims (25)

A method of forming a semiconductor device, comprising: removing a plurality of gates from a workpiece including a substrate, a main fin, and a plurality of imitation gates formed on the main fin, thereby forming a plurality of trenches; Forming at least a first active gate trench, a second active gate trench, and an isolation trench from the plurality of trenches, the isolation trench being between the first and second active gate trenches, wherein: Forming the isolation trench includes forming an isolation region in the fin portion near a bottom of at least one of the plurality of trenches, and forming a recess isolation dielectric in the isolation trench and the isolation region; the isolation trench The trench includes a hole; and the surface of the recessed isolation dielectric is below the hole. The method of claim 1, further comprising forming a local interconnect in the isolation trench. The method of claim 2, wherein the local interconnect has an upper surface below the aperture, and the method further comprises filling the isolation trench with a dielectric fill. The method of claim 1, further comprising forming a liner in the isolation trench and the isolation region prior to forming the recessed isolation dielectric. The method of claim 4, wherein the liner comprises a metal oxide, a metal nitride, a metal carbide, or a combination thereof. The method of claim 2, further comprising forming an active gate structure in at least one of the first and second active gate trenches. The method of claim 6, wherein the upper surface of the active gate structure is below the aperture of the first or second active gate trench. The method of claim 7, further comprising filling the first or second active gate trench with a dielectric fill. The method of claim 1, wherein the working member further comprises a plurality of source/drain contacts, wherein at least one of the source/drain contacts is in the first active gate trench and At least one of the isolation trenches and the source/drain contacts are between the second active gate trench and the isolation trench. The method of claim 9, wherein the working member further comprises a plurality of source/drain regions, wherein at least one source drain region is formed under each of the plurality of source/drain contacts . The method of claim 1, wherein the working member further comprises a plurality of source/drain contacts and a plurality of source/drain regions formed under the plurality of source/drain contacts And forming the first active gate trench, the second active gate trench, and the isolation trench include: forming a mask in the plurality of trenches; and removing a portion of the mask to expose it to become The at least one of the plurality of trenches of the isolation trench, the remaining portion of the mask protecting at least two of the plurality of trenches of the first and second active gate trenches. The method of claim 11, wherein the forming the mask comprises: depositing a first hard mask in the plurality of trenches; and depositing a second hard mask on the first hard mask. The method of claim 12, wherein the first hard mask is a carbon hard mask, and the second hard mask is a tantalum hard mask. The method of claim 1, wherein forming the recessed isolation dielectric in the isolation trench and the isolation region comprises: depositing an isolation material in the isolation trench and the isolation region; and in the isolation trench The isolation material is recessed to define the recessed isolation dielectric. An integrated circuit device comprising: a first active transistor, a second active transistor, and a main fin formed on the isolation structure; wherein: the isolation structure is in the first and second active Between the transistors, and for electrically isolating the first active transistor to the second active transistor; the isolation structure includes an isolation trench at the bottom of the isolation trench An isolation region formed therein, and a recessed isolation dielectric in the isolation trench and the isolation region; the isolation trench has a hole; and the recess isolation dielectric upper surface is below the hole. Such as the integrated circuit device of claim 15 of the patent scope, further A local interconnect formed at least partially in the isolation trench is included. The integrated circuit device of claim 16, wherein the local interconnect comprises a work function material formed on the upper surface of the recessed isolation dielectric. The integrated circuit device of claim 15 further comprising a dielectric fill on the recessed isolation dielectric and in the isolation trench. The integrated circuit device of claim 15 further comprising a spacer in the isolation trench and the isolation region, at least a portion of the spacer being between the recess isolation dielectric and the main fin . The integrated circuit device of claim 15, wherein the first and second active transistors individually comprise first and second active gate trenches, wherein the first active gate trench has a first A current gate structure, and a second active gate structure in the second active gate trench. The integrated circuit device of claim 20, wherein: the first and second active gate structures individually have first and second upper surfaces; and the first and second active gate trenches individually have a first And a second active gate trench hole; and the first and second upper surfaces are respectively below the first and second active gate trench holes. The integrated circuit device of claim 15, wherein the first and second active transistors each further comprise a plurality of source/drain electrodes a point wherein at least one source drain region is formed under each of the plurality of source/drain contacts. The integrated circuit device of claim 19, wherein the upper surface of the recessed isolation dielectric is below the upper surface of the spacer to isolate the upper surface of the dielectric by the recess and The liner defines a cup in the isolation trench; the device further includes a local interconnect in the isolation trench, wherein at least a portion of the local interconnect is formed in the cup. The integrated circuit device of claim 16, wherein the local interconnect is coupled to a voltage gate control source. The integrated circuit device of claim 22, further comprising a spacer formed on a sidewall of each of the plurality of source/drain contacts.