WO1997017729A1 - Silicon dioxide spacer for locos or recessed locos - Google Patents

Silicon dioxide spacer for locos or recessed locos Download PDF

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Publication number
WO1997017729A1
WO1997017729A1 PCT/US1996/014933 US9614933W WO9717729A1 WO 1997017729 A1 WO1997017729 A1 WO 1997017729A1 US 9614933 W US9614933 W US 9614933W WO 9717729 A1 WO9717729 A1 WO 9717729A1
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Prior art keywords
layer
substrate
forming
silicon dioxide
portions
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Application number
PCT/US1996/014933
Other languages
French (fr)
Inventor
Allan R. Acker
Nicholas H. Tripsas
Robert B. Ogle
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Advanced Micro Devices, Inc.
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Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1997017729A1 publication Critical patent/WO1997017729A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Definitions

  • the invention relates to local oxidation of silicon (LOCOS) processes, more particularly to the use of spacers during a LOCOS process.
  • LOCOS local oxidation of silicon
  • LOCOS local oxidation of silicon
  • Fig. 1 typically through a local oxidation of silicon (LOCOS) process.
  • LOCOS processes generally involve growing silicon dioxide by heating an exposed area of silicon (or silicon covered with a thin layer of silicon dioxide) in an oxygen or steam containing ambient.
  • the wafer construct Prior to LOCOS growth, the wafer construct is covered with an inert layer of material, such as silicon nitride (Si 3 N 4 ) , and the inert material layer patterned to expose the area selected for oxide formation.
  • a LOCOS process begins with a monocrystaline silicon substrate 10 having a predetermined concentration of p or n type impurities.
  • a thin layer of silicon dioxide 20, is grown on the surface of the silicon wafer. This layer is generally provided by heating the substrate and exposing it to an ambient oxidant for a given period of time which depends upon the thickness of the layer desired.
  • a layer of silicon nitride 30 is deposited over the oxide layer. The silicon nitride layer will be used to control where the substrate and oxide layer are oxidized.
  • a conventional photoresist process is utilized to pattern the silicon nitride layer.
  • a photoresist layer (not shown) is deposited over the silicon nitride, a masking step is performed to expose the photoresist layer, and, depending on the type of photoresist, the exposed or unexposed portions of the photoresist are removed.
  • the silicon nitride layer 30 is then patterned using, for example, a reactive ion etch to expose the underlying oxide layer 20.
  • the silicon nitride layer 30 is completely removed in the exposed area and at least part of the underlying oxide layer in the exposed area is also removed.
  • the photoresist layer is then removed, leaving the silicon nitride layer 30 as the uppermost layer on the substrate.
  • the resulting structure is shown in Fig. 2A.
  • a localized region of isolation oxide (also called field oxide) 40 is then grown in the exposed area. In general, this step is performed at very high temperatures in the range of 800-l200°C. Following the growth of the field oxide 40, the nitride layer is removed. Gate structures are then formed and doping implants are made to form the active regions of the device.
  • Recessed LOCOS processes are similar to conventional LOCOS processes except that part of the silicon substrate is removed to form trench 60 as shown in Fig. 3A. After oxidation a recessed LOCOS process serves to eliminate the field oxide region from reaching a height above the upper surface of nitride layer 30, thus improving the surface planarity of the wafer construct, shown in Fig. 3B. However, such trenching will increase lateral encroachment ( ⁇ w) .
  • One proposed solution to the problem of encroachment is to position a nitride spacer against the wall 35 (see Figs. 2A and 3A) formed by the nitride and oxide layers once those layers have been patterned.
  • Such nitride spacers serve to aid blocking oxidation of the substrate directly below each spacer.
  • use of such spacers has its own set of problems. These spacers must be removed at some point, but such removal becomes difficult when the nitride spacers are partially positioned below nitride region 30, i.e., against oxide region 20 or within trench 60, because the nitride spacers will become embedded in the field oxide region and may snap off.
  • the present invention is directed to LOCOS processes and field oxide growth. It is desirable to reduce encroachment of the field oxide region from that experienced with conventional and recessed LOCOS processes and to do so without using spacers which must later be removed.
  • the process according to the invention is initiated by the formation of barrier oxide and masking layers on a silicon substrate. Portions of the masking layer are removed to form windows in the masking layer having sidewalls. Silicon dioxide (Si0 2 ) spacers are formed along the sidewalls and the structure is exposed to an ambient oxidant. The silicon dioxide spacers effectively slow oxidation of the underlying substrate thereby reducing lateral encroachment.
  • Fig. 1 is a cross-sectional view of a wafer after doping and gate formation showing the use of isolation regions
  • Fig. 2A is a cross-sectional view of a conventional silicon wafer construct prior to oxidation
  • Fig. 2B is a cross-sectional view of a conventional silicon wafer construct following field oxida ion
  • Fig. 2C is a cross-sectional view of a conventional silicon wafer construct following field oxidation showing characteristic nitride lift
  • Fig. 3A is a cross-sectional view of a wafer construct prior to oxidation to be used in a conventional recessed LOCOS process
  • Fig. 3B is a cross-sectional view of a wafer construct following oxidation which utilized a conventional recessed LOCOS process
  • Fig. 4A is a cross-sectional view of a wafer construct using the process of one embodiment of the invention immediately prior to oxidation;
  • Fig. 4B is a cross-sectional view of the resulting wafer construct using the process of one embodiment of to the present invention.
  • encroachment ⁇ w causes isolation regions to become larger than desired, thus decreasing the packing density of devices per wafer, it is desirable to reduce the encroachment ⁇ w of isolation regions.
  • silicon dioxide spacers are positioned along the sidewalls of the windows. Oxidation rates slow as oxide thickness increases.
  • the silicon dioxide spacers effectively slow the oxidation of the silicon substrate underlying these spacers and, therefore, inhibit oxide growth.
  • the silicon dioxide spacers essentially become a part of the field oxide region, eliminating any necessity for removal.
  • a silicon substrate 110 is provided, upon which is grown a thin layer of silicon dioxide 120, having a thickness typically in a range of lOoA to 50 ⁇ A.
  • This layer is generally provided by heating the substrate and exposing it to a dry ambient oxidant, although a wet oxide is also suitable, at a temperature in the range of 800-1000°C, for a given period of time depending upon the thickness of the layer desired.
  • a layer of silicon nitride or other inert material is then deposited using, for example, conventional chemical vapor deposition (CVD) techniques to a thickness in a range of about lOOoA to 250 ⁇ A, and preferably approximately 170 ⁇ A.
  • CVD chemical vapor deposition
  • a conventional photoresist process is then utilized to pattern the silicon nitride layer.
  • a photoresist layer (not shown) is deposited over the silicon nitride, a masking step is performed to expose the photoresist layer, and, depending on the type of photoresist (typically a positive acting resist) the exposed or unexposed portions of the photoresist layer are removed.
  • the silicon nitride layer 130 is then patterned using, for example, a reactive ion etch, and portions of the nitride layer are completely removed to expose the underlying oxide layer forming a "window" in the nitride layer having sidewalls 135.
  • Underlying portions of the oxide layer 120 may also be removed in one embodiment of the invention and portions of silicon substrate 110 may additionally be removed in another embodiment to form a trench 160. While Fig. 4A only shows one sidewall 135, it is to be understood that a second sidewall is also formed when the "window" is formed and that only half of the "window” is shown.
  • a silicon dioxide layer of IOOA-IOOOA is deposited over the entire surface of the wafer construct using CVD or other methods well known in the art. The silicon dioxide layer is then patterned and etched anisotropically to form spacers 175 which abut sidewalls 135.
  • Fig. 4A shows the resulting wafer construction prior to oxidation.
  • the oxide layer 120, as well as the nitride layer 130 and the silicon dioxide layer may vary in thickness.
  • different embodiments of the invention may have variations in spacer recession R, measured from the top of the nitride layer 130.
  • an ambient oxidant which in one embodiment of the invention is a dry oxide, composed of approximately 0.05-1% HCl and 99-99.95% 0 2 , at temperatures in the range of 1000°C- 1250°C, and typically at 1125°C, for 4-10 hours.
  • a dry oxide composed of approximately 0.05-1% HCl and 99-99.95% 0 2 , at temperatures in the range of 1000°C- 1250°C, and typically at 1125°C, for 4-10 hours.
  • This oxidation process are described in Liu et al . , U.S. Patent No. 5,151,381, incorporated by reference herein. Note that other embodiments of the invention may use other oxidation processes such as wet oxidation processes or other dry oxidation processes.
  • encroachment ⁇ w is significantly reduced, as shown in Fig. 4B, which shows a cross-section of the wafer construction at the end of the oxidation cycle.
  • field oxide region 146 has a thickness of t ranging from lOOoA to 600 ⁇ A.
  • Field oxide region 140 also results in a "bird's head" structure 180 having a height h measured from the top of field oxide thickness t. If the bird's head height h is too high relative to the substrate under the nitride layer 130, the resulting structure will have to be planarized by either a chemical- mechanical polish (CMP) , spin-on glass (SOG) deposit and etch-back methods, or other well-known methods in order to smooth the profile.
  • CMP chemical- mechanical polish
  • SOG spin-on glass

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

A local oxidation of silicon process directed toward reducing lateral encroachment by use of silicon dioxide spacers. A barrier oxide (120) is formed on a silicon substrate (110) and a masking layer (130) is formed over the barrier oxide layer (120). The masking layers are removed to form windows in the masking layer having sidewalls (135) against which silicon dioxide sidewall spacers (175) are formed. The structure is exposed to an ambient oxidant to form fieldoxide regions (140). The silicon dioxide sidewall spacers (175) effectively slow the oxidation of the underlying substrate thereby reducing encroachment.

Description

SILICON DIOXIDE SPACER FOR LOCOS OR RECESSED LOCOS
BACKGROUND OF THE INVENTION
Field of Invention
The invention relates to local oxidation of silicon (LOCOS) processes, more particularly to the use of spacers during a LOCOS process.
Description of Related Art
Generally, in integrated circuit devices, active devices are formed on a semiconductor substrate. In many integrated circuits, these active devices must be electrically isolated from each other. One way to isolate the devices is to grow a field oxide region between devices, shown in Fig. 1, typically through a local oxidation of silicon (LOCOS) process. LOCOS processes generally involve growing silicon dioxide by heating an exposed area of silicon (or silicon covered with a thin layer of silicon dioxide) in an oxygen or steam containing ambient. Prior to LOCOS growth, the wafer construct is covered with an inert layer of material, such as silicon nitride (Si3N4) , and the inert material layer patterned to expose the area selected for oxide formation.
More specifically, referring to the cross-section of Fig. 2A, a LOCOS process begins with a monocrystaline silicon substrate 10 having a predetermined concentration of p or n type impurities. A thin layer of silicon dioxide 20, is grown on the surface of the silicon wafer. This layer is generally provided by heating the substrate and exposing it to an ambient oxidant for a given period of time which depends upon the thickness of the layer desired. A layer of silicon nitride 30 is deposited over the oxide layer. The silicon nitride layer will be used to control where the substrate and oxide layer are oxidized. A conventional photoresist process is utilized to pattern the silicon nitride layer. A photoresist layer (not shown) is deposited over the silicon nitride, a masking step is performed to expose the photoresist layer, and, depending on the type of photoresist, the exposed or unexposed portions of the photoresist are removed. The silicon nitride layer 30 is then patterned using, for example, a reactive ion etch to expose the underlying oxide layer 20. The silicon nitride layer 30 is completely removed in the exposed area and at least part of the underlying oxide layer in the exposed area is also removed. The photoresist layer is then removed, leaving the silicon nitride layer 30 as the uppermost layer on the substrate. The resulting structure is shown in Fig. 2A. A localized region of isolation oxide (also called field oxide) 40 is then grown in the exposed area. In general, this step is performed at very high temperatures in the range of 800-l200°C. Following the growth of the field oxide 40, the nitride layer is removed. Gate structures are then formed and doping implants are made to form the active regions of the device.
Referring to Fig. 2B, with conventional LOCOS processes, results are generally less than ideal. As the exposed substrate is oxidized, it not only expands horizontally, but it also expands laterally, underneath nitride 30, causing encroachment (Δ ) . The width of the isolation region thereby increases causing less packing density per wafer than is desired. In addition, and more characteristically, as the LOCOS oxide grows above the surface of the silicon substrate 10, it forces the edges of the silicon nitride layer 30 upward, resulting in the "bird's beak" effect 50, shown in Fig. 2C. An alternative to conventional LOCOS processes is "recessed LOCOS" processes. Recessed LOCOS processes are similar to conventional LOCOS processes except that part of the silicon substrate is removed to form trench 60 as shown in Fig. 3A. After oxidation a recessed LOCOS process serves to eliminate the field oxide region from reaching a height above the upper surface of nitride layer 30, thus improving the surface planarity of the wafer construct, shown in Fig. 3B. However, such trenching will increase lateral encroachment (Δw) . One proposed solution to the problem of encroachment is to position a nitride spacer against the wall 35 (see Figs. 2A and 3A) formed by the nitride and oxide layers once those layers have been patterned. Such nitride spacers, like the nitride layer 30, serve to aid blocking oxidation of the substrate directly below each spacer. However, use of such spacers has its own set of problems. These spacers must be removed at some point, but such removal becomes difficult when the nitride spacers are partially positioned below nitride region 30, i.e., against oxide region 20 or within trench 60, because the nitride spacers will become embedded in the field oxide region and may snap off.
Therefore, in both recessed and conventional LOCOS processes, there is a need to reduce lateral encroachment (Δw) of an isolation region without having to use spacers during the process that must be later removed.
SUMMARY OF THE INVENTION The present invention, roughly described, is directed to LOCOS processes and field oxide growth. It is desirable to reduce encroachment of the field oxide region from that experienced with conventional and recessed LOCOS processes and to do so without using spacers which must later be removed.
To reduce encroachment of the LOCOS region, the process according to the invention, roughly described, is initiated by the formation of barrier oxide and masking layers on a silicon substrate. Portions of the masking layer are removed to form windows in the masking layer having sidewalls. Silicon dioxide (Si02) spacers are formed along the sidewalls and the structure is exposed to an ambient oxidant. The silicon dioxide spacers effectively slow oxidation of the underlying substrate thereby reducing lateral encroachment.
The process in accordance with the invention is further advantageous in that it utilizes spacers that do not become embedded in the field oxide region and snap off, but rather the spacers utilized by the invention become part of the field oxide region itself. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with respect to particular embodiments thereof, and reference will be made to the drawings, in which:
Fig. 1 is a cross-sectional view of a wafer after doping and gate formation showing the use of isolation regions; Fig. 2A is a cross-sectional view of a conventional silicon wafer construct prior to oxidation;
Fig. 2B is a cross-sectional view of a conventional silicon wafer construct following field oxida ion;
Fig. 2C is a cross-sectional view of a conventional silicon wafer construct following field oxidation showing characteristic nitride lift;
Fig. 3A is a cross-sectional view of a wafer construct prior to oxidation to be used in a conventional recessed LOCOS process;
Fig. 3B is a cross-sectional view of a wafer construct following oxidation which utilized a conventional recessed LOCOS process; Fig. 4A is a cross-sectional view of a wafer construct using the process of one embodiment of the invention immediately prior to oxidation;
Fig. 4B is a cross-sectional view of the resulting wafer construct using the process of one embodiment of to the present invention.
DETAILED DESCRIPTION Because encroachment Δw causes isolation regions to become larger than desired, thus decreasing the packing density of devices per wafer, it is desirable to reduce the encroachment Δw of isolation regions. Thus, in accordance with the invention, after the formation of barrier oxide and masking layers on the substrate, and after patterning the masking layer to form "windows" exposing the substrate or the barrier oxide layer, silicon dioxide spacers are positioned along the sidewalls of the windows. Oxidation rates slow as oxide thickness increases. Thus, when the wafer construct is then exposed to an ambient oxidant, the silicon dioxide spacers effectively slow the oxidation of the silicon substrate underlying these spacers and, therefore, inhibit oxide growth. As a result, not only is encroachment Δw decreased, but the silicon dioxide spacers essentially become a part of the field oxide region, eliminating any necessity for removal.
More specifically, with reference to Figs. 4A and 4B, a silicon substrate 110 is provided, upon which is grown a thin layer of silicon dioxide 120, having a thickness typically in a range of lOoA to 50θA. This layer is generally provided by heating the substrate and exposing it to a dry ambient oxidant, although a wet oxide is also suitable, at a temperature in the range of 800-1000°C, for a given period of time depending upon the thickness of the layer desired. A layer of silicon nitride or other inert material is then deposited using, for example, conventional chemical vapor deposition (CVD) techniques to a thickness in a range of about lOOoA to 250θA, and preferably approximately 170θA.
A conventional photoresist process is then utilized to pattern the silicon nitride layer. A photoresist layer (not shown) is deposited over the silicon nitride, a masking step is performed to expose the photoresist layer, and, depending on the type of photoresist (typically a positive acting resist) the exposed or unexposed portions of the photoresist layer are removed. The silicon nitride layer 130 is then patterned using, for example, a reactive ion etch, and portions of the nitride layer are completely removed to expose the underlying oxide layer forming a "window" in the nitride layer having sidewalls 135. Underlying portions of the oxide layer 120 may also be removed in one embodiment of the invention and portions of silicon substrate 110 may additionally be removed in another embodiment to form a trench 160. While Fig. 4A only shows one sidewall 135, it is to be understood that a second sidewall is also formed when the "window" is formed and that only half of the "window" is shown. Next, a silicon dioxide layer of IOOA-IOOOA is deposited over the entire surface of the wafer construct using CVD or other methods well known in the art. The silicon dioxide layer is then patterned and etched anisotropically to form spacers 175 which abut sidewalls 135.
Fig. 4A shows the resulting wafer construction prior to oxidation. Note that in different embodiments of the invention the oxide layer 120, as well as the nitride layer 130 and the silicon dioxide layer (not shown) may vary in thickness. Further, different embodiments of the invention may have variations in spacer recession R, measured from the top of the nitride layer 130.
Following the formation of the structure of Fig. 4A, the structure is exposed to an ambient oxidant, which in one embodiment of the invention is a dry oxide, composed of approximately 0.05-1% HCl and 99-99.95% 02, at temperatures in the range of 1000°C- 1250°C, and typically at 1125°C, for 4-10 hours. Complete details of this oxidation process are described in Liu et al . , U.S. Patent No. 5,151,381, incorporated by reference herein. Note that other embodiments of the invention may use other oxidation processes such as wet oxidation processes or other dry oxidation processes. During the ambient oxidant exposure, because oxidation rate slows as the oxide thickens, the silicon dioxide spacer 175 reduces substrate 110 oxidation beneath spacer 175. Thus, encroachment Δw is significantly reduced, as shown in Fig. 4B, which shows a cross-section of the wafer construction at the end of the oxidation cycle.
Subsequent to the oxidation cycle, field oxide region 146 has a thickness of t ranging from lOOoA to 600θA. Field oxide region 140 also results in a "bird's head" structure 180 having a height h measured from the top of field oxide thickness t. If the bird's head height h is too high relative to the substrate under the nitride layer 130, the resulting structure will have to be planarized by either a chemical- mechanical polish (CMP) , spin-on glass (SOG) deposit and etch-back methods, or other well-known methods in order to smooth the profile.
The invention has been described with respect to particular embodiments thereof, and it will be understood that numerous modifications are possible within the scope of the invention as set forth in the claims.

Claims

CLAIMS What is claimed is:
1. A method of forming a field oxide region in a semiconductor substrate, comprising the steps of: forming a barrier oxide layer over said substrate; forming a masking layer over said barrier oxide layer; removing a portion of said masking layer, thereby forming a patterned surface having a sidewall; forming a silicon dioxide spacer in proximity to said sidewall; and exposing said patterned surface with said spacer to an ambient oxidant.
2. The method of claim 1, wherein said step of removing further includes removing a portion of said barrier oxide layer underlying said portion of said masking layer, exposing a first area of said substrate.
3. The method of claim 2, wherein said step of removing further includes removing a portion of said substrate underlying said portions of said masking layer and said barrier oxide layer, thereby exposing a second area of said substrate.
4. The method of claim 1, wherein said step of forming a silicon dioxide spacer comprises the steps of: forming a silicon dioxide layer over said patterned surface, said silicon dioxide layer having first, second, and third portions; removing said first portion of said silicon dioxide layer exposing said masking layer; removing said second portion of said silicon dioxide layer such that said third portion of said silicon dioxide layer remains in proximity to said sidewall.
5. The method of claim 1, wherein said step of exposing said patterned surface and said spacer results in said patterned surface having an oxide region, further comprising the step of planarizing said patterned surface such that said oxide region is smoothed.
6. The method of claim 5, wherein said step of planarizing said patterned surface includes a chemical-mechanical polish.
7. The method of claim 5, wherein said step of planarizing said patterned surface includes the steps of: forming a glass layer over said patterned surface; and etching and removing at least said glass layer to form a smooth planar surface.
8. A method of forming field oxide regions in a semiconductor substrate, comprising the steps of: forming a barrier oxide layer over said substrate; forming a nitride layer over said barrier oxide layer; removing a portion of said nitride layer, a portion of said barrier oxide layer underlying said portion of said nitride layer, thereby exposing a first portion of said substrate and forming a patterned surface having a sidewall extending from said exposed first portion of said substrate; forming a silicon dioxide spacer abutting said sidewall and said exposed first portion of said substrate; exposing said patterned surface with said silicon dioxide spacer to an ambient oxidant.
9. The method of claim 8, wherein said step of removing includes removing said first portion of said substrate underlying said portions of said nitride layer and said barrier oxide layer, thereby exposing a second portion of said substrate.
10. The method of claim 8, wherein said step of forming a silicon dioxide spacer comprises the steps of: forming a silicon dioxide layer over said patterned surface, said silicon dioxide layer having first, second, and third portions; removing said first portion of said silicon dioxide layer exposing said nitride layer; and removing said second portion of said silicon dioxide layer such that said third portion of said silicon dioxide layer remains abutting said sidewall.
11. The method of claim 8, wherein said step of exposing said patterned surface with said silicon dioxide spacer results in said patterned surface having an oxide region, further comprising the step of planarizing said patterned surface such that said oxide region is smoothed.
12. The method of claim 11, wherein said step of planarizing said patterned surface includes a chemical-mechanical polish.
13. The method of claim ll, wherein said step of planarizing said patterned surface includes the steps of: forming a glass layer over said patterned surface; and etching and removing at least said glass layer to form a smooth planar surface.
14. A method of forming a field oxide region in a semiconductor substrate, comprising the steps of: growing a barrier oxide layer over said substrate; depositing a nitride layer, having an uppermost part, over said barrier oxide layer; etching said nitride layer and said barrier oxide layer to pattern said nitride layer and said barrier oxide layer such that portions of said nitride layer and portions of said barrier oxide layer underlying said portions of said nitride layer are removed, thereby exposing first portions of said substrate and forming an etched surface having sidewalls extending from said exposed first portions of said substrate to said uppermost part of said nitride layer; depositing a spacer forming layer composed of silicon dioxide over said etched surface, said spacer forming layer having first, second and third portions; etching said spacer forming layer to pattern said spacer forming layer such that said first portions of said spacer forming layer are removed to expose said nitride layer, and said second portions of said spacer forming layer are removed to expose parts of said second portions of said substrate such that said third portions of said spacer forming layer remain to form spacers abutting said sidewalls and said substrate; and exposing said etched surface and said spacers to an oxide ambient oxidant at a temperature of approximately 800°C to 1200°C.
15. The method of claim 14, wherein said step of etching said nitride layer and said barrier oxide layer includes etching said substrate such that said first portions of said substrate are removed exposing second portions of said substrate.
16. The method of claim 14, wherein said step of exposing said etched surface and said spacer results in said etched surface having an oxide region, further comprising the step of planarizing said etched surface such that said oxide region is smoothed.
17. The method of claim 16, wherein said step of planarizing said etched surface includes a chemical-mechanical polish.
18. The method of claim 16, wherein said step of planarizing said etched surface includes the steps of: forming a glass layer over said etched surface; and etching and removing at least said glass layer to form a smooth planar surface.
19. A structure, comprising: a substrate having a first part and a second part; a barrier oxide layer, having an end, overlying at least said first part of said substrate; a nitride layer, having an end, overlying said barrier oxide layer, said ends of said barrier oxide layer and said nitride layer forming a sidewall extending up from said substrate; a field oxide region extending within said second part of said substrate, said field oxide region further extending above said substrate at a first elevation and having a bulbous member protruding up from said first elevation and abutting said sidewall.
PCT/US1996/014933 1995-11-10 1996-09-18 Silicon dioxide spacer for locos or recessed locos WO1997017729A1 (en)

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Cited By (1)

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WO2014138116A3 (en) * 2013-03-05 2014-11-06 Qualcomm Incorporated Method of forming finfet having fins of different height

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