CN105393355A - 抑制多tft器件中的泄漏电流 - Google Patents

抑制多tft器件中的泄漏电流 Download PDF

Info

Publication number
CN105393355A
CN105393355A CN201480037535.4A CN201480037535A CN105393355A CN 105393355 A CN105393355 A CN 105393355A CN 201480037535 A CN201480037535 A CN 201480037535A CN 105393355 A CN105393355 A CN 105393355A
Authority
CN
China
Prior art keywords
electrode circuit
patterning
semiconductor channel
source electrode
drain electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480037535.4A
Other languages
English (en)
Other versions
CN105393355B (zh
Inventor
S·里德尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Not Rec Yin Ai Greensboro Co Ltd
Original Assignee
Not Rec Yin Ai Greensboro Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Not Rec Yin Ai Greensboro Co Ltd filed Critical Not Rec Yin Ai Greensboro Co Ltd
Publication of CN105393355A publication Critical patent/CN105393355A/zh
Application granted granted Critical
Publication of CN105393355B publication Critical patent/CN105393355B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Abstract

一种操作器件的技术，所述器件包括：图案化的导体层，界定多个晶体管的源电极电路和漏电极电路；半导体层，设置每个晶体管的在所述源电极电路和所述漏电极电路之间的相应的半导体沟道；以及栅电极电路，与多个晶体管器件的所述半导体沟道重叠，用于使所述半导体沟道在两个或更多个电导级之间切换；其中所述技术包括使用独立于所述栅电极电路的一个或更多个其它导体以电容性地引起所述半导体沟道外的所述半导体层的一个或更多个区域的导电性的降低。

Description

抑制多TFT器件中的泄漏电流
包括多个TFT的器件通常包括：界定多个TFT的源电极电路和漏电极电路的图案化的导体层，以及设置每个TFT的在源电极和漏电极的相应的组合之间的相应的半导体沟道的半导体层。与半导体层电容性耦合的栅电极电路用于使半导体沟道在两个或更多个电导级之间切换。
减小栅电极电路的区域外的区域中的源电极电路和漏电极电路之间的泄漏电流是所期望的。
用于减小这样的泄漏电流的一个技术包括在全部多个晶体管的源电极电路/漏电极电路之上沉积半导体材料的覆盖层，并然后在半导体沟道外的一个或更多个区域中通过例如激光烧蚀移除半导体层的部分。
用于减小这样的泄漏电流的另一个技术包括将半导体层沉积为多个岛，每个岛设置相应的TFT的半导体沟道但在半导体层内不与任何其它岛相连接。
已经确定了提供用于减小泄漏电流的新技术的挑战。
本文提供一种操作器件的方法，所述器件包括：图案化的导体层，界定多个晶体管的源电极电路和漏电极电路；半导体层，设置每个晶体管的在源电极电路和漏电极电路之间的相应的半导体沟道；以及栅电极电路，与多个晶体管器件的半导体沟道重叠，用于使半导体沟道在两个或更多个电导级之间切换；其中所述方法包括使用独立于所述栅电极电路的一个或更多个其它导体以电容性地引起所述半导体沟道外的所述半导体层的一个或更多个区域的导电性的降低。
在一个实施例中，半导体层的所述一个或更多个区域包括栅电极电路的区域外的一个或更多个区域。
在一个实施例中，所述一个或更多个区域包括栅电极电路的区域外的其中源电极电路和漏电极电路彼此最接近的一个或更多个区域。
在一个实施例中，所述方法还包括：电容性地引起所述半导体层的所述一个或更多个区域的导电性的降低，同时使用所述栅电极电路以电容性地引起一个或更多所述半导体沟道的导电性的改变。
在一个实施例中，所述一个或更多个其它导体设置在图案化的导体层的与栅电极电路相反的一侧。
在一个实施例中，所述一个或更多个其它导体包括在多个晶体管的源电极电路和漏电极电路之间的除了半导体沟道以外的基本上所有区域上延伸的导体层。
本文还提供一种控制器件，包括：第一图案化的导体层，界定多个晶体管器件的源电极电路和漏电极电路；半导体层，设置在每个晶体管器件的源电极电路和漏电极电路之间的相同的晶体管器件的相应的半导体沟道；第二图案化的导体层，界定用于与多个晶体管器件的半导体沟道电容性耦合并且使半导体沟道在两个或更多个电导级之间切换的栅电极电路；其中所述半导体层延伸超过所述半导体沟道到达位于所述源电极电路和所述漏电极电路之间的其它区域；并且其中所述器件还包括布置在半导体层的与第二图案化的导体层相反的一侧的第三图案化的导体层，其中所述第三图案化的导体层在多个晶体管的源电极电路和漏电极电路之间的除了半导体沟道以外的基本上整个区域上延伸。
下面参照附图，仅通过示例的方式说明本发明的实施例，所述附图中：
图1是根据本发明的第一实施例的器件的平面图；以及
图2和图3是图1的器件分别在线A和B处的剖面图。
图1是根据本发明的实施例的TFT阵列的一部分的平面图。为了简明，在图1中仅示出4个TFT，但是用于控制像素化的光学显示器的TFT阵列通常会包括成千上万的TFT。
在中间的层级处的图案化的导体层界定TFT阵列的源电极电路和漏电极电路。源电极电路包括多个独立的源电极导体8a、8b，所述独立的源电极导体8a、8b的电位可以被控制为彼此独立。每个源电极导体8a、8b形成对应行的TFT的源电极和该行的TFT的寻址线。漏电极电路包括多个独立的漏电极导体10a、10b、10c、10d。每个独立的漏电极导体10形成相应的TFT的漏电极，并且设置到TFT阵列的其它元件(诸如在更高的层级处的相应的像素电极)的导电路径。为了清晰起见，在图中未示出像素电极以及位于像素电极和漏电极导体之间的夹层连接。
在源电极电路和漏电极电路上形成半导体材料12的覆盖层，所述覆盖层设置每个TFT的源电极电路和漏电极电路之间的半导体沟道。半导体沟道是半导体层的与源电极电路和漏电极电路的部分连接的部分，所述源电极电路和漏电极电路被仔细地布置为彼此非常接近(例如，间隔20微米或更小)以形成相应的TFT的源电极和漏电极。半导体层12可以形成于TFT的覆盖区的基本上整个区域之上，更具体地，形成于位于源电极电路和漏电极电路之间的所有区域之上。栅极介电层14形成于半导体层12之上。另一个图案化的导体层形成于栅极介电层14的与半导体层12相反的一侧，并且界定独立的栅极线16a、16b的阵列，每个栅极线在对应列的TFT的半导体沟道上延伸。每个栅极线16的电位可以独立于其它栅极线被控制，并且栅极线16用于使对应列的TFT的半导体沟道在两个或更多个电导级之间切换。例如，栅极线16用于使对应列的TFT在导通状态和截止状态之间切换。
在界定源电极电路和漏电极电路的图案化的导体层的与半导体层12相反的一侧形成其它(further)介电层6和经由其它介电层6电容性地耦合到半导体层12的第三图案化的导体层4。所有上述的层都被支撑在衬底2上。此第三图案化的导体层4是在图中示出的示例中的上述三个图案化的导体层中第一个要形成的。第三图案化的导体层界定与TFT阵列的每个半导体沟道的位置对应的窗口20。第三图案化的导体层4跨多个晶体管的源电极电路和漏电极电路之间的半导体层的除了半导体沟道的基本上整个区域地延伸。具体地，第三图案化的导体层跨栅极线16所重叠的区域外的其中源电极电路和漏电极电路彼此最接近的各个区域地延伸。
TFT阵列的操作包括改变栅极线16的电位(并因而使TFT的半导体沟道在两个或更多个电导级之间切换)，同时将第三图案化的导体层的电位维持在基本上恒定的值，这起到在第三图案化的导体层4所重叠的半导体层12的部分中电容性地引起半导体层12的这些部分的电导的减小。这些部分的电导的减小用来抑制经由半导体层12的在源电极电路8和漏电极电路10之间的泄漏电流，该泄漏电流可能导致TFT之间不期望的串扰和来自存储电容器的不期望的电荷泄漏；并且还抑制源电极导体(源极寻址线)之间(特别是在像素阵列的周围)的泄漏电流，该抑制具有减小功耗的益处。
例如，半导体材料是p型半导体，对第三图案化的导体层施加高的正偏置电压用以减小半导体材料的电导。施加到第三图案化的导体层4的高的正电压使半导体的自由正电荷载流子完全耗尽，并因而减小半导体12的电导。(i)此正电压与(ii)第三图案化的导体层4和半导体层12之间的介电层6的厚度的比被选择为：和(iii)施加到栅极线16以使相应行的TFT切换到截止状态的电压(Vgate_off)与(iv)源电极电路8/漏电极电路10和栅极线16之间的栅极介电层的厚度的比的数量级相同。
与源电极导体8和漏电极导体10相对照，第三图案化的导体层4是在阵列中的所有TFT上连续的，并且仅需要一个到第三图案化的导体层4的触点来施加抑制上述经由栅电极电路16的区域外的基本上所有区域中的半导体层的源极漏极层级处的导体之间的泄漏电流所必需的电位。
而且，通过将上述高的正电压施加到第三图案化的导体层4所消耗的电功率是低的，因为在TFT阵列的操作期间，不存在直接流入第三图案化的导体层4的电流，并且不存在施加到第三图案化的导体层4的电压的切换。
设置了第三图案化的导体层4的层级也可以包括在TFT阵列的区域外的一个或更多个独立导体，所述独立导体用作设置支持TFT阵列的操作的逻辑电路的额外的底栅极TFT的底栅电极。
在上文说明了且图中例示了的示例中，第三图案化的导体层设置在衬底的与界定源极导体和漏极导体的导体层相同的一侧上。根据一个变型，第三图案化的导体层形成于衬底的与源极导体和漏极导体相反的一侧上，而支撑衬底2额外还起到第三图案化的导体层和半导体层之间的电介质的作用。
在上文说明了且图中例示了的示例中，TFT阵列是顶栅极TFT的阵列。然而，相同的技术同样可应用于底栅极TFT的阵列；对于底栅极TFT阵列的情况，第三图案化的导体层会是三个图案化的导体层中最后要形成的，并且将形成在界定源极导体和漏极导体的图案化的导体层之上的层级处。
除了上文清晰地提及了的任何变型以外，在本发明的范围内对所说明的实施例的各种其它变型对本领域技术人员而言都是明了的。

Claims (7)

1.一种操作器件的方法，所述器件包括：图案化的导体层，界定多个晶体管的源电极电路和漏电极电路；半导体层，设置每个晶体管的在所述源电极电路和所述漏电极电路之间的相应的半导体沟道；以及栅电极电路，与多个晶体管器件的所述半导体沟道重叠，用于使所述半导体沟道在两个或更多个电导级之间切换；其中所述方法包括使用独立于所述栅电极电路的一个或更多个其它导体以电容性地引起所述半导体沟道外的所述半导体层的一个或更多个区域的导电性的降低。
2.根据权利要求1所述的方法，其中所述半导体层的所述一个或更多个区域包括所述栅电极电路的区域外的一个或更多个区域。
3.根据权利要求2所述的方法，其中所述一个或更多个区域包括所述栅电极电路的区域外的其中所述源电极电路和所述漏电极电路彼此最接近的一个或更多个区域。
4.根据权利要求1-3中的任何一项所述的方法，包括：电容性地引起所述半导体层的所述一个或更多个区域的导电性的降低，并同时使用所述栅电极电路以电容性地引起一个或更多个所述半导体沟道的导电性的改变。
5.根据权利要求1-4中的任何一项所述的方法，其中所述一个或更多个其它导体设置在所述图案化的导体层的与所述栅电极电路相反的一侧。
6.根据权利要求5所述的方法，其中所述一个或更多个其它导体包括在所述多个晶体管的所述源电极电路和所述漏电极电路之间的除了所述半导体沟道以外的基本上所有区域上延伸的导体层。
7.一种控制器件，包括：第一图案化的导体层，界定多个晶体管器件的源电极电路和漏电极电路；半导体层，设置位于每个晶体管器件的源电极电路和漏电极电路之间的相同的晶体管器件的相应的半导体沟道；第二图案化的导体层，界定用于与所述多个晶体管器件的半导体沟道电容性耦合并且使所述半导体沟道在两个或更多个电导级之间切换的栅电极电路；其中所述半导体层延伸超过所述半导体沟道到达位于所述源电极电路和所述漏电极电路之间的其它区域；并且其中所述器件还包括布置在所述半导体层的与所述第二图案化的导体层相反的一侧的第三图案化的导体层，其中所述第三图案化的导体层在所述多个晶体管的所述源电极电路和所述漏电极电路之间的除了所述半导体沟道以外的基本上整个区域上延伸。
CN201480037535.4A 2013-07-01 2014-07-01 一种抑制多tft器件中的泄漏电流的方法和器件 Expired - Fee Related CN105393355B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB1311772.6 2013-07-01
GB1311772.6A GB2515750B (en) 2013-07-01 2013-07-01 Supressing Leakage Currents in a Multi - TFT Device
PCT/EP2014/063937 WO2015000884A1 (en) 2013-07-01 2014-07-01 Supressing leakage currents in a multi-tft device

Publications (2)

Publication Number Publication Date
CN105393355A true CN105393355A (zh) 2016-03-09
CN105393355B CN105393355B (zh) 2019-08-06

Family

ID=48999330

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480037535.4A Expired - Fee Related CN105393355B (zh) 2013-07-01 2014-07-01 一种抑制多tft器件中的泄漏电流的方法和器件

Country Status (6)

Country Link
US (1) US9748278B2 (zh)
CN (1) CN105393355B (zh)
DE (1) DE112014003128T5 (zh)
GB (1) GB2515750B (zh)
RU (1) RU2665331C2 (zh)
WO (1) WO2015000884A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2526316B (en) * 2014-05-20 2018-10-31 Flexenable Ltd Production of transistor arrays
US20190081077A1 (en) * 2016-03-15 2019-03-14 Sharp Kabushiki Kaisha Active matrix substrate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1115233A (zh) * 1994-07-22 1996-01-24 河南师范大学 5,5′-偶氮二水杨酸锌治疗肠炎和溃疡性结肠炎
US20030160236A1 (en) * 2000-03-13 2003-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
CN1183595C (zh) * 1999-08-24 2005-01-05 皇家菲利浦电子有限公司 显示装置
CN1819299A (zh) * 2004-12-23 2006-08-16 三星Sdi株式会社 薄膜晶体管、包括薄膜晶体管的平板显示器以及制造薄膜晶体管和平板显示器的方法
EP2015379A2 (en) * 2007-07-11 2009-01-14 Ricoh Company, Ltd. Organic transistor, organic transistor array, and display apparatus
CN100541811C (zh) * 2002-03-04 2009-09-16 株式会社日立制作所 有机电致发光显示装置
US20110017971A1 (en) * 2009-07-23 2011-01-27 Samsung Electronics Co., Ltd. Integrated circuit devices including low-resistivity conductive patterns in recessed regions

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620140B2 (ja) * 1986-06-11 1994-03-16 株式会社日立製作所 薄膜トランジスタ
JP2720862B2 (ja) * 1995-12-08 1998-03-04 日本電気株式会社 薄膜トランジスタおよび薄膜トランジスタアレイ
JP3535307B2 (ja) * 1996-03-15 2004-06-07 株式会社半導体エネルギー研究所 半導体装置
US20020060321A1 (en) * 2000-07-14 2002-05-23 Kazlas Peter T. Minimally- patterned, thin-film semiconductor devices for display applications
EP1312120A1 (en) * 2000-08-14 2003-05-21 Matrix Semiconductor, Inc. Dense arrays and charge storage devices, and methods for making same
KR100387122B1 (ko) * 2000-09-15 2003-06-12 피티플러스(주) 백 바이어스 효과를 갖는 다결정 실리콘 박막 트랜지스터의 제조 방법
JP2005079283A (ja) * 2003-08-29 2005-03-24 Seiko Epson Corp 薄膜半導体装置及びその製造方法、電気光学装置、並びに電子機器
JP4474900B2 (ja) * 2003-10-29 2010-06-09 カシオ計算機株式会社 静電気保護回路およびそれを備えた電子回路
KR20060118063A (ko) * 2005-05-16 2006-11-23 엘지.필립스 엘시디 주식회사 액정표시장치용 어레이 기판 및 그 제조 방법
US20080023703A1 (en) 2006-07-31 2008-01-31 Randy Hoffman System and method for manufacturing a thin-film device
GB0709093D0 (en) * 2007-05-11 2007-06-20 Plastic Logic Ltd Electronic device incorporating parylene within a dielectric bilayer
US20120146043A1 (en) * 2009-09-01 2012-06-14 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
CN102024410B (zh) * 2009-09-16 2014-10-22 株式会社半导体能源研究所 半导体装置及电子设备
JP6120530B2 (ja) * 2012-11-12 2017-04-26 キヤノン株式会社 撮像装置、および撮像システム。

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1115233A (zh) * 1994-07-22 1996-01-24 河南师范大学 5,5′-偶氮二水杨酸锌治疗肠炎和溃疡性结肠炎
CN1183595C (zh) * 1999-08-24 2005-01-05 皇家菲利浦电子有限公司 显示装置
US20030160236A1 (en) * 2000-03-13 2003-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
CN100541811C (zh) * 2002-03-04 2009-09-16 株式会社日立制作所 有机电致发光显示装置
CN1819299A (zh) * 2004-12-23 2006-08-16 三星Sdi株式会社 薄膜晶体管、包括薄膜晶体管的平板显示器以及制造薄膜晶体管和平板显示器的方法
EP2015379A2 (en) * 2007-07-11 2009-01-14 Ricoh Company, Ltd. Organic transistor, organic transistor array, and display apparatus
US20110017971A1 (en) * 2009-07-23 2011-01-27 Samsung Electronics Co., Ltd. Integrated circuit devices including low-resistivity conductive patterns in recessed regions

Also Published As

Publication number Publication date
US9748278B2 (en) 2017-08-29
CN105393355B (zh) 2019-08-06
GB2515750B (en) 2017-11-15
WO2015000884A1 (en) 2015-01-08
RU2665331C2 (ru) 2018-08-29
US20160372488A1 (en) 2016-12-22
GB2515750A (en) 2015-01-07
RU2016102696A (ru) 2017-08-07
GB201311772D0 (en) 2013-08-14
DE112014003128T5 (de) 2016-03-31

Similar Documents

Publication Publication Date Title
KR101892510B1 (ko) 실리콘 및 반도체성 산화물 박막 트랜지스터를 구비한 디스플레이
CN100587958C (zh) 具有抑制特性偏移的结构的薄膜晶体管面板及其制造方法
US8416169B2 (en) Drive circuit, active matrix substrate, and liquid crystal display device
KR100373940B1 (ko) 박막반도체장치
US9331101B2 (en) Organic light emitting display panel
CN105655345B (zh) 液晶显示装置及其制造方法
KR20150028122A (ko) 박막 트랜지스터 및 그 구동 방법
RU2710905C1 (ru) Способ уменьшения нежелательной емкостной связи в транзисторном устройстве
CN105393355A (zh) 抑制多tft器件中的泄漏电流
CN105723443B (zh) 矩阵排列的晶体管组的寻址
JP6383420B2 (ja) 薄膜トランジスタ、配列基板及び表示パネル
KR102449066B1 (ko) 표시장치용 어레이기판 및 그 제조방법
JP2006287084A (ja) 薄膜トランジスタ素子およびその製造方法
US9837450B2 (en) Reducing parasitic leakages in transistor arrays
KR101413656B1 (ko) 트랜지스터 및 그 동작방법
US9876034B2 (en) Transistor array routing
JP2809162B2 (ja) 半導体装置
TW202016631A (zh) 光電裝置
JP6279086B2 (ja) 薄膜トランジスタスイッチ及びその製造方法
TW201310620A (zh) 半導體積體電路裝置
TW202002305A (zh) 半導體基板、陣列基板、逆變器電路及開關電路
KR20060018382A (ko) 트랜지스터
JP2015018942A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190806

Termination date: 20210701

CF01 Termination of patent right due to non-payment of annual fee