CN105390436A - 预切割金属线 - Google Patents

预切割金属线 Download PDF

Info

Publication number
CN105390436A
CN105390436A CN201510516163.XA CN201510516163A CN105390436A CN 105390436 A CN105390436 A CN 105390436A CN 201510516163 A CN201510516163 A CN 201510516163A CN 105390436 A CN105390436 A CN 105390436A
Authority
CN
China
Prior art keywords
line
sacrifice
cave
layer
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510516163.XA
Other languages
English (en)
Other versions
CN105390436B (zh
Inventor
A·C-H·魏
G·布什
M·A·扎勒斯基
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN105390436A publication Critical patent/CN105390436A/zh
Application granted granted Critical
Publication of CN105390436B publication Critical patent/CN105390436B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)

Abstract

本发明公开了预切割金属线。具体地，本发明的实施例提供一种方法用于后段制程结构中牺牲金属线的切割。在金属Mx线上面形成牺牲Mx+1线。在该牺牲Mx+1线上方沉积和图案化线切口微影堆栈物并且形成切穴。该切穴用介电材料填充。以选择性蚀刻制程去除该牺牲Mx+1线，保护填充在该切穴中的电介质。接着在去除该牺牲Mx+1线的地方沉积金属来形成预切金属线。因此本发明的实施例提供预切金属线，并且不需要金属切割。通过避免金属切割的需要，也避免了与金属切割有关的风险。

Description

预切割金属线
技术领域
本发明一般是关于半导体制造，更详而言之，是有关于预切金属线。
背景技术
随着半导体装置的制造技术的日渐进步，藉由增加半导体装置的集成密度，制造商已经在芯片上放置越来越大量的组件。因此，设计规则中的临界尺寸(CD)随着该电路密度的增加而逐渐减小。
为了增加电路密度，有必要减小该半导体装置内部的组件尺寸，以及减小耦合组件在一起的互连件长度和宽度。此外，该互连件的阻抗必须够小以便能通过具有狭窄宽度的互连件，以该半导体装置内的最小能量损失来转换电子信号。
在典型的集成电路中，可能具有许多金属化层和互连通孔层在后段(BEOL)互连结构中形成。该BEOL互连结构连接各种装置(例如晶体管和电容器..等等)以形成功能电路。在制造过程中，有必要形成金属线的切口和连接以创造出所希望的连接性来实现给定的设计。随着临界尺寸持续收缩，这可以视剧有挑战性的。因此希望有所改善以解决上述问题。
发明内容
本发明的实施例提供一种用于后段制程结构中牺牲金属线的切割的方法。牺牲Mx+1线在金属Mx线上面形成。线切口微影堆栈物沉积且图案化于该牺牲Mx+1线上方，并且形成切穴。该切穴用介电材料填充。选择性蚀刻制程去除该牺牲Mx+1线，保护填充于该切穴中的该介电质。接着藉由在去除该牺牲Mx+1线的地方沉积金属来形成预切金属线。因此，本发明的实施例提供预切金属线，并且不需要进行金属切割。通过避免金属切割的需要，也避免了与金属切割有关的风险。
第一方面，本发明的实施例提供一种形成半导体结构的方法，包括:在多个金属Mx线上方形成多个牺牲Mx+1线；在该多个牺牲Mx+1线上方沉积介电层；在该多个牺牲Mx+1线的其中一个牺牲Mx+1线中形成切穴；在该切穴中形成介电区；去除该多个牺牲Mx+1线以形成多个Mx+1线穴；以及以金属填充该多个Mx+1线穴以形成多个金属Mx+1线。
第二方面，本发明的实施例提供一种形成半导体结构的方法，包括:在多个金属Mx线上方形成多个牺牲Mx+1线；在该多个牺牲Mx+1线上方沉积介电层；在该介电层上沉积有机平坦化层；在该有机平坦化层上沉积抗蚀层；在该抗蚀层和有机平坦化层中形成凹穴；去除该抗蚀层；在该有机平坦化层上沉积保形间隔层；在该保形间隔层上进行各向异性蚀刻以形成孔间隔件；在该多个牺牲Mx+1层的其中一个牺牲Mx+1线中形成切穴；在该切穴中形成介电区；去除该多个牺牲Mx+1线以形成多个Mx+1线穴；以及用金属填充该多个Mx+1线穴以形成多个金属Mx+1线。
第三方面，本发明的实施例提供一种形成半导体结构的方法，包括:在多个金属Mx线上方形成多个牺牲Mx+1线；在该多个牺牲Mx+1线上方沉积介电层；在该多个牺牲Mx+1线的其中一个牺牲Mx+1线中形成切穴；在该切穴中形成介电区；去除该多个牺牲Mx+1线以形成多个Mx+1线穴；沉积通孔切口微影堆栈物；在该通孔切口微影堆栈物中图案化开口；形成通孔穴使暴露出该多个金属Mx线的其中一个Mx金属线；去除该通孔切口微影堆栈物；以及用金属填充该多个Mx+1线穴和通孔穴以形成多个金属Mx+1线和通孔。
附图说明
附图是包含在说明书中并构成本说明书的一部分，显示出本发明教示的几个实施例，并且一起用于解释本发明教示的原理。
这些图中的某些组件可以忽略，或是不按比例示出，这是为了说明的清楚起见。这些剖视图可以用“部分”或“近看”的剖视图形式，省略某些会在“真实”剖视图中见到的背景线条，这是为了清楚说明。
通常，相似的组件可以在各附图中以相似的符号提起，在此情况下，通常最后两个有效数字是相同的，最大有效数字作为该附图的图号。此外，为清楚起见，在某些图中的某些符号可以忽略。
图1是本发明实施例起点的半导体结构。
图2是随后沉积牺牲层的制程步骤之后的半导体结构。
图3是随后沉积抗蚀层及图案化该抗蚀层的制程步骤之后的半导体结构。
图4是随后图案化该牺牲层及去除该抗蚀层的制程步骤之后的半导体结构。
图5是随后沉积介电层于该牺牲Mx+1线上方的制程步骤之后的半导体结构的侧视图。
图6是随后平坦化该介电层的制程步骤之后的半导体结构的侧视图。
图7是随后沉积和图案化线切口微影堆栈物的制程步骤之后的半导体结构。
图8是随后在牺牲Mx+1线中形成切穴的制程步骤之后的半导体结构。
图9是随后去除该线切口微影堆栈物的制程步骤之后的半导体结构。
图10是根据本发明实施例，随后去除该抗蚀层的制程步骤之后的半导体结构。
图11是根据本发明实施例，随后沉积保形间隔层的制程步骤之后的半导体结构。
图12是根据本发明实施例，随后进行各向异性蚀刻以形成孔间隔件的制程步骤之后的半导体结构。
图13是根据本发明实施例，随后在牺牲Mx+1线中形成切穴的制程步骤之后的半导体结构。
图14是随后在该切穴中形成介电区的制程步骤之后的半导体结构。
图15是随后去除该牺牲Mx+1线的制程步骤之后的半导体结构。
图16是随后沉积和图案化通孔切口微影堆栈物的制程步骤之后的半导体结构。
图17是随后形成暴露出Mx金属线的通孔穴的制程步骤之后的半导体结构。
图18是随后去除该通孔切口微影堆栈物的制程步骤之后的半导体结构。
图19是随后形成金属Mx+1线的制程步骤之后的半导体结构。
图20是图19中沿着线B-B’所视的半导体结构。
图21表示本发明实施例的制程步骤的流程图。
具体实施方式
示例性实施例现在将参照示例性实施例所示出的附图更为详细地描述出。应当理解本发明可以许多不同形式实施而不应被视为是限于本文所述的实施例。相反的，提供这些示例性实施例使得本发明将彻底且完整的公开，并且将全面地传达本发明的范围给那些本领域技术人士。
本文所用的术语仅是为了描述具体实施例，并非意在限制本发明。例如，如本文所使用的单数形式“一”和“该”是意在包括复数形式，除非上下文另外明确指出。此外，使用的术语“一”等，不表示对数量的限制，而是表示所引用项目的至少一个的存在。将进一步理解的是，术语“包括”或“包含”，当在本说明书中使用时，是指定所述特征、区域、整体、步骤、操作、组件和/或部件，但不排除存在或添加一或多个其它征、区域、整体、步骤、操作、组件、部件和/或其组合。
贯穿本说明书中对“一个实施例”、“实施例”、“实施方案”、“示例性实施方案”中，或类似语言的参考意味着一个特定特征、结构或与该实施例描述的特征是在包含在本发明的至少一个实施例。因此，“在一个实施方案中”、“在实施例”、“在实施方案中”的短语和类似语言的贯穿本说明书出现可以但不一定都指的是同一实施例。
术语“覆”或“之上”，“位于”或“设置顶上”，“底层”、“之下”或“下方”意味着第一组件，像是第一结构，例如第一层，是出现在第二组件上，像是第二结构，例如第二层，其中中间组件，像是接口结构，例如接口层，可以是存在于第一组件和第二组件之间。
图1是在本发明实施例的起始点的半导体结构100。半导体结构100显示一个具有多个金属线106的后段(BEOL)线路结构，形成在介电层102中。在实施例中，介电层102可包括SiOC(碳氧化硅)。在实施例中，金属线106包括铜。在实施例中，各个金属线106被阻挡层104包围在侧面与底部。这用于防止金属扩散。在实施例中，阻挡层104包括钽和/或氮化钽。帽层105可以沉积在金属线106的顶部上。在实施例中，帽层105可包括SiN(氮化硅)。金属线106被称为Mx线，其中“x”表示特定的金属化水平(particularmetallizationlevel)。在金属线106下面是金属线103。因此，金属线103被称为Mx-1金属线。该金属线可以用工业级标准的技术来形成，包括但不限于，阻挡层沉积、金属晶种层沉积和金属电镀制程，紧接着是平坦化制程。在实施例中，蚀刻停止层110沉积在介电层102上方，覆盖金属线106。在实施例中，蚀刻停止层110包括氧化铝(Al2O3)。
图2是随后沉积牺牲层112于该半导体结构上方的制程步骤之后的半导体结构100。牺牲层112沉积在蚀刻停止层110上。在实施例中，牺牲层112可包括SiN，并且可以用等离子增强化学气相沉积(PECVD)来进行沉积。非晶硅也可以做为牺牲材料。
图3是随后沉积和图案化抗蚀层(微影堆栈物)114因而形成图案化微影堆栈物的制程步骤之后的半导体结构100，。该图案化可用工业级标准的微影方法，包括但不限于，自对准双图案化(SADP)，或是自对准四图案化(SAQP)来完成。
图4是随后图案化该牺牲层和去除该抗蚀层的制程步骤之后的半导体结构100。这会在该半导体结构上形成牺牲“虚设(dummy)”Mx+1线116。这可藉由各向异性蚀刻图3的牺牲层112而停在蚀刻停止层110上来完成，如此去除该牺牲层未被该图案化抗蚀层覆盖的部分，以形成牺牲“虚设”线116，然后再去除抗蚀层114。在一些实施例中，蚀刻停止层110也可被去除。注意Mx和Mx+1都显示为在各层级的单向并行线的常规组合，而Mx+1垂直Mx。
图5是随后沉积介电层118于该牺牲Mx+1线上方的制程步骤之后的半导体结构100的侧视图，沿着图4的线A-A’所示。在实施例中，介电层118可包括碳氧化硅(SiOC)。该介电层可用等离子增强化学气相沉积(PECVD)制程来沉积。在实施例中，由于介电层118的保形特性，空气间隙120可形成在各牺牲线116之间。该空气间隙具有约1的介电常数，且因此可用于改善关于高速信号传播通过BEOL层的电路性能。
图6是随后平坦化介电层118使得它基本上是与牺牲线116等高的制程步骤之后的半导体结构100的侧视图。在实施例中，该平坦化是采用化学机械抛光(CMP)制程。空气间隙120可在此过程中保留(如图所示)，或在一些实施例中，可以部份打开(图未示出)。
图7是随后沉积且图案化线切口微影堆栈物122的制程步骤之后的半导体结构100。线切口微影堆栈物122可包括有机平坦化层(OPL)以及随后的光阻层(称为“抗蚀”)。在实施例中，该OPL可包括光敏有机聚合物，其包括光敏材料，当暴露在电磁波(EM)辐射下，会产生化学变化从而能够用显影溶剂除去。例如，该光敏有机聚合物可以是聚丙烯酸酯树脂、环氧树脂、酚醛树脂、聚酰胺树脂、聚酰亚胺树脂、不饱和聚酯树脂、聚苯醚树脂、聚苯硫醚树脂、或苯并环丁烯(BCB)。
多个空隙124被图案化于微影堆栈物122中。空隙124各别暴露在牺牲线116的区域，以及一些介电区118。介电层118和牺牲线116包括不同材料，允许选择性的蚀刻技术去除牺牲线116穿过空隙124暴露出的部分，而不必去除介电区118。因此，各空隙124的位置和尺寸的公差是有弹性的，能够更容易地制造且改善产品良率。
图8是随后在牺牲Mx+1线中形成切穴126的制程步骤之后的半导体结构100。如同前述，介电层118和牺牲线116包括不同材料，允许选择性蚀刻技术去除牺牲线116的部分。因此，去除牺牲线116的暴露区域，露出下面的蚀刻停止层110，并且形成切穴126。
图9是随后去除该线切口微影堆栈物(图7中的122)的制程步骤之后的半导体结构100。该微影堆栈物可以用工业级标准技术来去除，因此揭示出牺牲线116与切穴126在该替代(金属)线被分开位置的图案。
图10是根据本发明的一替代实施例，随后去除线切口微影堆栈物122的抗蚀层(见图7)，暴露出底层的有机平坦化层(OPL)的制程步骤之后的半导体结构。因此图10从图7得到，但提供额外的制程步骤来进一步控制该切穴的尺寸，如同将在下图中所示出的。空隙124在有机平坦化层128中形成以暴露出区域牺牲线116。
图11是根据本发明的一替代实施例，随后沉积保形间隔层(conformalspacer)130的制程步骤之后的半导体结构。在实施例中，保形间隔层130包括碳，并且可经由原子层沉积制程来沉积。在实施例中，该保形间隔层具有约2纳米到约5纳米范围的厚度。在该有机平坦化层中的空隙124上方形成凹部132。
图12是根据本发明的一替代实施例，随后进行各向异性蚀刻以形成孔间隔件134的制程步骤之后的半导体结构。在实施例中，该各向异性蚀刻可包括反应性离子蚀刻(RIE)制程。该各向异性蚀刻去除该保形间隔层的大部分，除了剩余部分，也就是孔间隔件134。孔间隔件134具有区段厚度D1。在实施例中，D1的范围是从约2纳米到约8纳米。在去除牺牲线116的部分以具有长度D2之前，该孔间隔件进一步限制了该开口，因此能够缩小化切穴。在实施例中，D2可具有约5纳米到30纳米的范围。
图13是根据本发明的一替代实施例，随后在牺牲Mx+1线中形成切穴的制程步骤之后的半导体结构。如同前述，介电层118和牺牲线116包括不同材料，允许选择性蚀刻技术去除牺牲线116的部分。然后可以选择性地蚀刻掉该碳间隔件。
图14是在切穴中形成介电区118A的制程步骤之后的半导体结构。从图14开始，该制程相似于图1到图9所示的实施例，以及图10到图13所示的附加步骤的替代实施例。如图14所示，附加介电材料118A沉积在各切穴中。可接着进行平坦化制程使得介电区118A基本上和牺牲线116及介电区118一样平坦。这可以通过化学机械抛光(CMP)制程和/或各向异性RIE回蚀来完成。介电区118A和介电区118最好是由相同材料制成。因此，在实施例中，介电区118A也可以包括碳氧化硅。
图15是随后去除该牺牲Mx+1线的制程步骤之后的半导体结构。这可以采用选择性蚀刻制程来完成，让介电区118和118A维持完整。
图16是随后沉积且图案化通孔切口微影堆栈物136的制程步骤之后的半导体结构。通孔切口微影堆栈物136可包含有机平坦化层、抗反射层和抗蚀层。使用图案化会在通孔切口微影堆栈物136中形成空隙138。该空隙会在已经去除牺牲线116之处的上方形成，从而揭露出沉积在该金属层下面的垂直向Mx线的帽层105部分。根据给定的设计，理想上在某些位置形成互连邻近金属化层级的通孔。因此，空隙会在希望于Mx线和Mx+1线之间形成通孔的地方形成。
图17是随后形成暴露出Mx金属线的切穴的制程步骤之后的半导体结构。该帽层(见图16的105)的区域采用选择性蚀刻制程来去除。例如，若介电层118是碳氧化硅，且帽层105是氮化硅，则可以使用各种选择性蚀刻技术来选择性去除帽层105。本发明的实施例可使用其他材料的介电层和帽层，只要这些材料对彼此的选择性蚀刻是有可能的。
图18是随后去除该通孔切口微影堆栈物(图17的136)的制程步骤之后的半导体结构。这会暴露出帽层105未有通孔形成的区域，其中Mx线106是暴露在通孔形成的范围。
图19是随后形成金属Mx+1线的制程步骤之后的半导体结构。在实施例中，这可包括电镀制程。该制程可包括沉积一或多道阻挡层和/或晶种层(未示出)。然后，在牺牲Mx+1线先前占据的位置沉积填充金属(例如铜)，形成金属化线142。介电区118A分开金属化线142A和金属化线142A’。因此，金属化线142A和金属化线142A’是预切割的，因为它们具有切口的形成已经到位，并因此避免了金属切割。金属化线142B具有通孔以连接到该Mx层级，这将在接下来的图中进一步描述。
图20是图19中沿着线B-B’所示的半导体结构。如可以看到的，Mx+1金属线142B连接到Mx金属线106。当Mx+1线142B形成时，Mx线106会暴露出，因为它的帽层被去除(见图18的106)。因此，根据本发明的实施例，该制程藉由避免金属切割而简化制造，并且也整合通孔进入该金属化制程的连接性。
图21是用于表示本发明实施例的制程步骤的流程图200。在制程步骤250，形成牺牲线。在实施例中，该牺牲线包括氮化硅。在制程步骤252，沉积介电层。在实施例中，该介电层包括碳氧化硅。在制程步骤254，沉积线切口微影堆栈物(见图7的122)。在制程步骤256，切割该牺牲线(见图9)。在制程步骤258，沉积附加电介质于该切穴(见图14的118A)中。在制程步骤260，去除该牺牲线(见图15)。在实施例中，也可以去除该蚀刻停止层(图1的110)。在制程步骤262，沉积通孔穴微影堆栈物(见图16的136)。在制程步骤264，所选定的M(x)线在通孔于该M(x)和M(x+1)层级间形成的地方打开(见图17的140)。在制程步骤266，形成M(x+1)金属线(见图19的142)。然后，本文所揭露的制程可重复制造出多个金属化层级。在一些实施例中，可以有10层或更多层。一旦该BEOL堆栈完成，附加制程的工业级标准技术，像是封装和测试可用来完成该集成电路的制造。
虽然本发明已经结合示例性实施例具体示出及描述，但可以理解的是，对于本领域技术人士，变化和修改将可想到的。例如，尽管本文中所示出的说明性实施例是一系列动作或事件，但应当理解的是，本发明不受这些行为或事件的所示顺序所限制，除非特别说明。一些动作可以按不同顺序和/或同时与其它动作或事件发生，除了那些在本文中根据本发明示出和/或描述的之外。此外，并非所有示出的步骤中可需要根据本发明的方法来实现。此外，根据本发明的方法可以结合与本文中所描述或示出的结构的形成和/或工艺以及其他未示出的结构来实现。因此，可以理解的是，所附的权利要求旨在包含所有这些落在本发明的真实精神内的修改和改变。

Claims (20)

1.一种形成半导体结构的方法，包括:
在多个金属Mx线上方形成多个牺牲Mx+1线；
在该多个牺牲Mx+1线上方沉积介电层；
在该多个牺牲Mx+1线的其中一个牺牲Mx+1线中形成切穴；
在该切穴中形成介电区；
去除该多个牺牲Mx+1线以形成多个Mx+1线穴；以及
以金属填充该多个Mx+1线穴以形成多个金属Mx+1线。
2.如权利要求1所述的方法，其特征在于，形成多个牺牲Mx+1线包括:
在该多个金属Mx线上方沉积牺牲层；
在该牺牲层上沉积微影堆栈物；
图案化该微影堆栈物以形成图案化微影堆栈物；
去除该牺牲层未被该图案化微影堆栈物覆盖的部分；以及
去除该微影堆栈物。
3.如权利要求1所述的方法，其特征在于，沉积介电层包括沉积碳氧化硅。
4.如权利要求3所述的方法，其特征在于，更包括平坦化该介电层。
5.如权利要求4所述的方法，其特征在于，平坦化该介电层包括进行化学机械抛光制程。
6.如权利要求1所述的方法，其特征在于，填充该多个具有金属的Mx+1线穴包括用铜填充该多个Mx+1线穴。
7.一种形成半导体结构的方法，包括:
在多个金属Mx线上方形成多个牺牲Mx+1线；
在该多个牺牲Mx+1线上方沉积介电层；
在该介电层上沉积有机平坦化层；
在该有机平坦化层上沉积抗蚀层；
在该抗蚀层和有机平坦化层中形成凹穴；
去除该抗蚀层；
在该有机平坦化层上沉积保形间隔层；
在该保形间隔层上进行各向异性蚀刻以形成孔间隔件；
在该多个牺牲Mx+1层的其中一个牺牲Mx+1线中形成切穴；
在该切穴中形成介电区；
去除该多个牺牲Mx+1线以形成多个Mx+1线穴；以及
用金属填充该多个Mx+1线穴以形成多个金属Mx+1线。
8.如权利要求7所述的方法，其特征在于，沉积保形间隔层包括沉积碳。
9.如权利要求8所述的方法，其特征在于，以原子层沉积制程来进行沉积碳。
10.如权利要求7所述的方法，其特征在于，形成多个牺牲Mx+1线包括:
在该多个金属Mx线上方沉积牺牲层；
在该牺牲层上沉积微影堆栈物；
图案化该微影堆栈物以形成图案化微影堆栈物；
去除该牺牲层未被该图案化微影堆栈物覆盖的部分；以及
去除该微影堆栈物。
11.如权利要求7所述的方法，其特征在于，沉积介电层包括沉积碳氧化硅。
12.如权利要求11所述的方法，其特征在于，更包括平坦化该介电层。
13.如权利要求12所述的方法，其特征在于，平坦化该介电层包括进行化学机械抛光制程。
14.如权利要求7所述的方法，其特征在于，用金属填充该多个Mx+1线穴包括用铜填充该多个Mx+1线穴。
15.一种形成半导体结构的方法，包括:
在多个金属Mx线上方形成多个牺牲Mx+1线；
在该多个牺牲Mx+1线上方沉积介电层；
在该多个牺牲Mx+1线的其中一个牺牲Mx+1线中形成切穴；
在该切穴中形成介电区；
去除该多个牺牲Mx+1线以形成多个Mx+1线穴；
沉积通孔切口微影堆栈物；
在该通孔切口微影堆栈物中图案化开口；
形成通孔穴使暴露出该多个金属Mx线的其中一个Mx金属线；
去除该通孔切口微影堆栈物；以及
用金属填充该多个Mx+1线穴和通孔穴以形成多个金属Mx+1线和通孔。
16.如权利要求15所述的方法，其特征在于，形成多个牺牲Mx+1线包括:
在该多个金属Mx线上方沉积牺牲层；
在该牺牲层上沉积线切口微影堆栈物；
图案化该线切口微影堆栈物以形成图案化线切口微影堆栈物；
去除该牺牲层未被该图案化线切口微影堆栈物覆盖的部分；以及
去除该图案化线切口微影堆栈物。
17.如权利要求15所述的方法，其特征在于，沉积介电层包括沉积碳氧化硅。
18.如权利要求17所述的方法，其特征在于，更包括平坦化该介电层。
19.如权利要求18所述的方法，其特征在于，平坦化该介电层包括进行化学机械抛光制程。
20.如权利要求19所述的方法，其特征在于，用金属填充该多个Mx+1线穴包括用铜填充该多个Mx+1线穴。
CN201510516163.XA 2014-08-20 2015-08-20 预切割半导体结构的金属线的方法 Expired - Fee Related CN105390436B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/463,801 US9263325B1 (en) 2014-08-20 2014-08-20 Precut metal lines
US14/463,801 2014-08-20

Publications (2)

Publication Number Publication Date
CN105390436A true CN105390436A (zh) 2016-03-09
CN105390436B CN105390436B (zh) 2019-04-02

Family

ID=55275498

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510516163.XA Expired - Fee Related CN105390436B (zh) 2014-08-20 2015-08-20 预切割半导体结构的金属线的方法

Country Status (3)

Country Link
US (2) US9263325B1 (zh)
CN (1) CN105390436B (zh)
TW (1) TWI567841B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481994A (zh) * 2016-06-07 2017-12-15 格罗方德半导体公司 用于具有多电轨及冗余的半导体装置的互连结构

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9263325B1 (en) * 2014-08-20 2016-02-16 Globalfoundries Inc. Precut metal lines
US9779943B2 (en) 2016-02-25 2017-10-03 Globalfoundries Inc. Compensating for lithographic limitations in fabricating semiconductor interconnect structures
US9818623B2 (en) 2016-03-22 2017-11-14 Globalfoundries Inc. Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
US9691626B1 (en) 2016-03-22 2017-06-27 Globalfoundries Inc. Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portions
US9679809B1 (en) 2016-03-22 2017-06-13 Globalfoundries Inc. Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines
US9691775B1 (en) 2016-04-28 2017-06-27 Globalfoundries Inc. Combined SADP fins for semiconductor devices and methods of making the same
US9704859B1 (en) 2016-05-06 2017-07-11 International Business Machines Corporation Forming semiconductor fins with self-aligned patterning
US9607886B1 (en) 2016-06-30 2017-03-28 International Business Machines Corporation Self aligned conductive lines with relaxed overlay
US9818641B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines
US9818640B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines
US9786545B1 (en) 2016-09-21 2017-10-10 Globalfoundries Inc. Method of forming ANA regions in an integrated circuit
US9852986B1 (en) 2016-11-28 2017-12-26 Globalfoundries Inc. Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
US9812351B1 (en) 2016-12-15 2017-11-07 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned continuity cuts
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US9934970B1 (en) * 2017-01-11 2018-04-03 International Business Machines Corporation Self aligned pattern formation post spacer etchback in tight pitch configurations
US10199270B2 (en) * 2017-05-25 2019-02-05 Globalfoundries Inc. Multi-directional self-aligned multiple patterning
EP3660890B1 (en) 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
US11158536B2 (en) 2020-01-07 2021-10-26 International Business Machines Corporation Patterning line cuts before line patterning using sacrificial fill material
US11527434B2 (en) 2020-02-20 2022-12-13 International Business Machines Corporation Line cut patterning using sacrificial material
US11195795B1 (en) 2020-06-03 2021-12-07 International Business Machines Corporation Well-controlled edge-to-edge spacing between adjacent interconnects
US11705363B2 (en) 2021-03-19 2023-07-18 Samsung Electronics Co., Ltd Fully aligned via integration with selective catalyzed vapor phase grown materials
US11804406B2 (en) 2021-07-23 2023-10-31 International Business Machines Corporation Top via cut fill process for line extension reduction
US11942424B2 (en) 2021-12-01 2024-03-26 International Business Machines Corporation Via patterning for integrated circuits

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1514478A (zh) * 2002-12-27 2004-07-21 �Ҵ���˾ 利用先桥后金属喷镀制造顺序的坚固超低k互连结构
CN1617326A (zh) * 2003-09-09 2005-05-18 三星电子株式会社 制造在互连孔的下部侧壁处具有斜面的半导体器件的方法
US20050153505A1 (en) * 2004-01-14 2005-07-14 International Business Machines Corporation Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
CN101154623A (zh) * 2006-09-30 2008-04-02 中芯国际集成电路制造(上海)有限公司 双镶嵌结构的形成方法
CN101197274A (zh) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 通孔刻蚀方法
US20130126816A1 (en) * 2011-11-17 2013-05-23 Micron Technology, Inc. Memory Arrays and Methods of Forming Memory Cells

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420262B1 (en) * 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6613664B2 (en) * 2000-12-28 2003-09-02 Infineon Technologies Ag Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
US6734090B2 (en) * 2002-02-20 2004-05-11 International Business Machines Corporation Method of making an edge seal for a semiconductor device
US6987067B2 (en) 2002-08-21 2006-01-17 International Business Machines Corporation Semiconductor copper line cutting method
KR101395060B1 (ko) 2007-09-18 2014-05-15 삼성전자주식회사 라인 패턴들을 포함하는 반도체 소자
US20090200668A1 (en) * 2008-02-07 2009-08-13 International Business Machines Corporation Interconnect structure with high leakage resistance
KR101023074B1 (ko) * 2008-09-23 2011-03-24 주식회사 동부하이텍 이미지 센서 및 그 제조 방법
US8288268B2 (en) * 2010-04-29 2012-10-16 International Business Machines Corporation Microelectronic structure including air gap
WO2012122388A2 (en) * 2011-03-08 2012-09-13 Georgia Tech Research Corporation Chip-last embedded interconnect structures and methods of making the same
WO2013095433A1 (en) * 2011-12-21 2013-06-27 Intel Corporation Electroless filled conductive structures
KR101996244B1 (ko) * 2013-06-27 2019-07-05 삼성전자 주식회사 반도체 소자 제조 방법
US9059259B2 (en) * 2013-07-19 2015-06-16 Taiwan Semiconductor Manufacturing Company Limited Hard mask for back-end-of-line (BEOL) interconnect structure
KR102154112B1 (ko) * 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
US9093386B2 (en) * 2013-11-20 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer-damage-free etching
US9324650B2 (en) * 2014-08-15 2016-04-26 International Business Machines Corporation Interconnect structures with fully aligned vias
US9263325B1 (en) * 2014-08-20 2016-02-16 Globalfoundries Inc. Precut metal lines

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1514478A (zh) * 2002-12-27 2004-07-21 �Ҵ���˾ 利用先桥后金属喷镀制造顺序的坚固超低k互连结构
CN1617326A (zh) * 2003-09-09 2005-05-18 三星电子株式会社 制造在互连孔的下部侧壁处具有斜面的半导体器件的方法
US20050153505A1 (en) * 2004-01-14 2005-07-14 International Business Machines Corporation Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
CN101154623A (zh) * 2006-09-30 2008-04-02 中芯国际集成电路制造(上海)有限公司 双镶嵌结构的形成方法
CN101197274A (zh) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 通孔刻蚀方法
US20130126816A1 (en) * 2011-11-17 2013-05-23 Micron Technology, Inc. Memory Arrays and Methods of Forming Memory Cells

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481994A (zh) * 2016-06-07 2017-12-15 格罗方德半导体公司 用于具有多电轨及冗余的半导体装置的互连结构
CN107481994B (zh) * 2016-06-07 2020-07-10 格罗方德半导体公司 用于具有多电轨及冗余的半导体装置的互连结构

Also Published As

Publication number Publication date
TWI567841B (zh) 2017-01-21
US10396026B2 (en) 2019-08-27
CN105390436B (zh) 2019-04-02
TW201620052A (zh) 2016-06-01
US20160056075A1 (en) 2016-02-25
US20160118341A1 (en) 2016-04-28
US9263325B1 (en) 2016-02-16

Similar Documents

Publication Publication Date Title
CN105390436A (zh) 预切割金属线
US9679805B2 (en) Self-aligned back end of line cut
US8298943B1 (en) Self aligning via patterning
CN103839881B (zh) 具有自对准端对端导线结构的半导体器件及其制造方法
CN108074911B (zh) 跳孔结构
US10366917B2 (en) Methods of patterning variable width metallization lines
CN104040711A (zh) 后段电可编程熔断器
US20150102496A1 (en) Novel method to make high aspect ratio vias for high performance devices interconnection application
TWI742350B (zh) 具有層心軸之自對準多重圖案化製程
US7786586B2 (en) Inductor of semiconductor device and method for manufacturing the same
CN105261551A (zh) 多层电路组件的制造
CN107591371B (zh) 形成sadp于sram上及saqp于逻辑上的装置及方法
CN110364432B (zh) 半导体器件及其制造方法
CN108369923A (zh) 防止过孔穿通的无掩模气隙
WO2020002626A1 (en) Foldable layered connection, and method for manufacturing a foldable layered connection
TWI668875B (zh) 具有浮島的片上電容器
CN106575623A (zh) 用于低剖面基板的图案间图案
CN115332156A (zh) 集成芯片
CN116964736A (zh) 自对准顶部过孔
CN108122820B (zh) 互连结构及其制造方法
TW202143440A (zh) 用於高密度電路的具有集成堆疊3d金屬線之3d電路的製作方法
CN206992079U (zh) 集成电路芯片
KR20100011121A (ko) 반도체 소자 및 그의 제조 방법
KR100778852B1 (ko) 반도체 소자 및 그 제조방법
CN105051883B (zh) 在集成电路中形成栅栏导体

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210317

Address after: California, USA

Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Patentee before: GLOBALFOUNDRIES Inc.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190402

Termination date: 20210820

CF01 Termination of patent right due to non-payment of annual fee