TW201620052A - 預切的金屬線 - Google Patents
預切的金屬線 Download PDFInfo
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- TW201620052A TW201620052A TW104122504A TW104122504A TW201620052A TW 201620052 A TW201620052 A TW 201620052A TW 104122504 A TW104122504 A TW 104122504A TW 104122504 A TW104122504 A TW 104122504A TW 201620052 A TW201620052 A TW 201620052A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 72
- 239000002184 metal Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 103
- 238000000151 deposition Methods 0.000 claims abstract description 42
- 238000001459 lithography Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims description 54
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 16
- 239000000126 substance Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 3
- 229910000420 cerium oxide Inorganic materials 0.000 claims 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims 2
- NDRMFDVLHDJXMH-UHFFFAOYSA-N [La].[C]=O Chemical compound [La].[C]=O NDRMFDVLHDJXMH-UHFFFAOYSA-N 0.000 claims 1
- 238000005520 cutting process Methods 0.000 abstract description 10
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 238000001465 metallisation Methods 0.000 description 14
- 230000008021 deposition Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000010561 standard procedure Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- OPICPBLVZCCONG-UHFFFAOYSA-N [Ta].[C]=O Chemical compound [Ta].[C]=O OPICPBLVZCCONG-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
本發明公開了預切的金屬線。具體地,本發明的實施例提供一種方法用於後段製程結構中犧牲金屬線的切割。在金屬Mx線上面形成犧牲Mx+1線。在該犧牲Mx+1線上方沉積和圖案化線切口微影堆疊物並且形成切穴。該切穴用介電材料填充。以選擇性蝕刻製程去除該犧牲Mx+1線,保護填充在該切穴中的電介質。接著在去除該犧牲Mx+1線的地方沉積金屬來形成預切金屬線。因此本發明的實施例提供預切金屬線,並且不需要金屬切割。通過避免金屬切割的需要,也避免了與金屬切割有關的風險。
Description
本發明一般是關於半導體製造,更詳而言之,是有關於預切的金屬線。
隨著半導體裝置的製造技術的日漸進步,藉由增加半導體裝置的積體密度,製造商已經在芯片上放置越來越大量的組件。因此,設計規則中的臨界尺寸(CD)隨著該電路密度的增加而逐漸減小。
為了增加電路密度,有必要減小該半導體裝置內部的組件尺寸,以及減小耦合組件在一起的互連件長度和寬度。此外,該互連件的阻抗必須夠小以便能通過具有狹窄寬度的互連件,以該半導體裝置內的最小能量損失來轉換電子信號。
在典型的積體電路中,可能具有許多金屬化層和互連通孔層在後段(BEOL)互連結構中形成。該BEOL互連結構連接各種裝置(例如電晶體和電容器..等等)以形成功能電路。在製造過程中,有必要形成金屬線的切口和連接以創造出所希望的連接性來實現給定的設計。隨著臨界尺寸持續收縮,這可以是具有挑戰性的。因此希望
有所改善以解決上述問題。
本發明的實施例提供一種用於後段製程結構中犧牲金屬線的切割的方法。犧牲Mx+1線在金屬Mx線上面形成。線切口微影堆疊物沉積且圖案化於該犧牲Mx+1線上方,並且形成切穴。該切穴用介電材料填充。選擇性蝕刻製程去除該犧牲Mx+1線,保護填充於該切穴中的該介電質。接著藉由在去除該犧牲Mx+1線的地方沉積金屬來形成預切金屬線。因此,本發明的實施例提供預切金屬線,並且不需要進行金屬切割。通過避免金屬切割的需要,也避免了與金屬切割有關的風險。
第一態樣,本發明的實施例提供一種形成半導體結構的方法,包括:在多個金屬Mx線上方形成多個犧牲Mx+1線;在該多個犧牲Mx+1線上方沉積介電層;在該多個犧牲Mx+1線的其中一個犧牲Mx+1線中形成切穴;在該切穴中形成介電區;去除該多個犧牲Mx+1線以形成多個Mx+1線穴;以及以金屬填充該多個Mx+1線穴以形成多個金屬Mx+1線。
第二態樣,本發明的實施例提供一種形成半導體結構的方法,包括:在多個金屬Mx線上方形成多個犧牲Mx+1線;在該多個犧牲Mx+1線上方沉積介電層;在該介電層上沉積有機平坦化層;在該有機平坦化層上沉積抗蝕層;在該抗蝕層和有機平坦化層中形成凹穴;去除該抗蝕層;在該有機平坦化層上沉積保形間隔件層;在該保
形間隔件層上進行非等向性蝕刻以形成孔間隔件;在該多個犧牲Mx+1線的其中一個犧牲Mx+1線中形成切穴;在該切穴中形成介電區;去除該多個犧牲Mx+1線以形成多個Mx+1線穴;以及用金屬填充該多個Mx+1線穴以形成多個金屬Mx+1線。
第三態樣,本發明的實施例提供一種形成半導體結構的方法,包括:在多個金屬Mx線上方形成多個犧牲Mx+1線;在該多個犧牲Mx+1線上方沉積介電層;在該多個犧牲Mx+1線的其中一個犧牲Mx+1線中形成切穴;在該切穴中形成介電區;去除該多個犧牲Mx+1線以形成多個Mx+1線穴;沉積通孔切口微影堆疊物;在該通孔切口微影堆疊物中圖案化開口;形成暴露出該多個金屬Mx線的其中一個Mx金屬線之通孔穴;去除該通孔切口微影堆疊物;以及用金屬填充該多個Mx+1線穴和該通孔穴以形成多個金屬Mx+1線和通孔。
100‧‧‧半導體結構
102‧‧‧介電層
103‧‧‧金屬線
104‧‧‧阻擋層
105‧‧‧帽層
106‧‧‧金屬線
110‧‧‧蝕刻停止層
112‧‧‧犧牲層
114‧‧‧抗蝕層
116‧‧‧犧牲線
118‧‧‧介電層
118A‧‧‧介電區
120‧‧‧空氣間隙
122‧‧‧線切口微影堆疊物
124‧‧‧空隙
126‧‧‧切穴
128‧‧‧有機平坦化層
130‧‧‧保形間隔件層
132‧‧‧凹部
134‧‧‧孔間隔件
136‧‧‧通孔切口微影堆疊物
138‧‧‧空隙
140‧‧‧M(x)線
142‧‧‧M(x+1)金屬線
142A‧‧‧金屬化線
142A’‧‧‧金屬化線
142B‧‧‧金屬化線
200‧‧‧製程步驟的流程
250‧‧‧製程步驟
252‧‧‧製程步驟
254‧‧‧製程步驟
256‧‧‧製程步驟
258‧‧‧製程步驟
260‧‧‧製程步驟
262‧‧‧製程步驟
264‧‧‧製程步驟
266‧‧‧製程步驟
D1‧‧‧區段厚度
D2‧‧‧長度
附圖是包含在說明書中並構成本說明書的一部分,顯示出本發明教示的幾個實施例,並且一起用於解釋本發明教示的原理。
這些圖中的某些組件可以忽略,或是不按比例示出,這是為了說明的清楚起見。這些剖視圖可以用“部分”或“近看”的剖視圖形式,省略某些會在“真實”剖視圖中見到的背景線條,這是為了清楚說明。
通常,相似的組件可以在各附圖中以相同
的元件符號提起,在此情況下,通常最後兩個有效數字是相同的,最大有效數字作為該附圖的圖號。此外,為清楚起見,在某些圖中的某些符號可以忽略。
第1圖是本發明實施例起點的半導體結構。
第2圖是隨後沉積犧牲層的製程步驟之後的半導體結構。
第3圖是隨後沉積抗蝕層及圖案化該抗蝕層的製程步驟之後的半導體結構。
第4圖是隨後圖案化該犧牲層及去除該抗蝕層的製程步驟之後的半導體結構。
第5圖是隨後沉積介電層於該犧牲Mx+1線上方的製程步驟之後的半導體結構的側視圖。
第6圖是隨後平坦化該介電層的製程步驟之後的半導體結構的側視圖。
第7圖是隨後沉積和圖案化線切口微影堆疊物的製程步驟之後的半導體結構。
第8圖是隨後在犧牲Mx+1線中形成切穴的製程步驟之後的半導體結構。
第9圖是隨後去除該線切口微影堆疊物的製程步驟之後的半導體結構。
第10圖是根據本發明實施例,隨後去除該抗蝕層的製程步驟之後的半導體結構。
第11圖是根據本發明實施例,隨後沉積保形間隔件層的製程步驟之後的半導體結構。
第12圖是根據本發明實施例,隨後進行非等向性蝕刻以形成孔間隔件的製程步驟之後的半導體結構。
第13圖是根據本發明實施例,隨後在犧牲Mx+1線中形成切穴的製程步驟之後的半導體結構。
第14圖是隨後在該切穴中形成介電區的製程步驟之後的半導體結構。
第15圖是隨後去除該犧牲Mx+1線的製程步驟之後的半導體結構。
第16圖是隨後沉積和圖案化通孔切口微影堆疊物的製程步驟之後的半導體結構。
第17圖是隨後形成暴露出Mx金屬線的通孔穴的製程步驟之後的半導體結構。
第18圖是隨後去除該通孔切口微影堆疊物的製程步驟之後的半導體結構。
第19圖是隨後形成金屬Mx+1線的製程步驟之後的半導體結構。
第20圖是第19圖中沿著線B-B’所視的半導體結構。
第21圖表示本發明實施例的製程步驟的流程圖。
示例性實施例現在將參照示例性實施例所示出的附圖更為詳細地描述出。應當理解本發明可以許多
不同形式實施而不應被視為是限於本文所述的實施例。相反的,提供這些示例性實施例使得本發明將徹底且完整的公開,並且將全面地傳達本發明的範圍給那些本領域技術人士。
本文所用的術語僅是為了描述具體實施例,並非意在限制本發明。例如,如本文所使用的單數形式“一”和“該”是意在包括複數形式,除非上下文另外明確指出。此外,使用的術語“一”等,不表示對數量的限制,而是表示所引用項目的至少一個的存在。將進一步理解的是,術語“包括”或“包含”,當在本說明書中使用時,是指定所述特徵、區域、整體、步驟、操作、組件和/或部件,但不排除存在或添加一或多個其它征、區域、整體、步驟、操作、組件、部件和/或其組合。
貫穿本說明書中對“一個實施例”、“實施例”、“實施方案”、“示例性實施方案”中,或類似語言的參考意味著一個特定特徵、結構或與該實施例描述的特徵是在包含在本發明的至少一個實施例。因此,“在一個實施方案中”、“在實施例”、“在實施方案中”的短語和類似語言的貫穿本說明書出現可以但不一定都指的是同一實施例。
術語“覆”或“之上”,“位於”或“設置頂上”,“底層”、“之下”或“下方”意味著第一組件,像是第一結構,例如第一層,是出現在第二組件上,像是第二結構,例如第二層,其中中間組件,像是接口結
構,例如接口層,可以是存在於第一組件和第二組件之間。
第1圖是在本發明實施例的起始點的半導體結構100。半導體結構100顯示一個具有多個金屬線106的後段(BEOL)線路結構,形成在介電層102中。在實施例中,介電層102可包括SiOC(碳氧化矽)。在實施例中,金屬線106包括銅。在實施例中,各個金屬線106被阻擋層104包圍在側面與底部。這用於防止金屬擴散。在實施例中,阻擋層104包括鉭和/或氮化鉭。帽層105可以沉積在金屬線106的頂部上。在實施例中,帽層105可包括SiN(氮化矽)。金屬線106被稱為Mx線,其中“x”表示特定的金屬化水平(particular metallization level)。在金屬線106下麵是金屬線103。因此,金屬線103被稱為Mx-1金屬線。該金屬線可以用工業級標準的技術來形成,包括但不限於,阻擋層沉積、金屬晶種層沉積和金屬電鍍製程,緊接著是平坦化製程。在實施例中,蝕刻停止層110沉積在介電層102上方,覆蓋金屬線106。在實施例中,蝕刻停止層110包括氧化鋁(Al2O3)。
第2圖是隨後沉積犧牲層112於該半導體結構上方的製程步驟之後的半導體結構100。犧牲層112沉積在蝕刻停止層110上。在實施例中,犧牲層112可包括SiN,並且可以用電漿增強化學氣相沉積(PECVD)來進行沉積。非晶矽也可以做為犧牲材料。
第3圖是隨後沉積和圖案化抗蝕層(微影堆疊物)114因而形成圖案化微影堆疊物的製程步驟之後的半
導體結構100,。該圖案化可用工業級標準的微影方法,包括但不限於,自對準雙圖案化(SADP),或是自對準四圖案化(SAQP)來完成。
第4圖是隨後圖案化該犧牲層和去除該抗蝕層的製程步驟之後的半導體結構100。這會在該半導體結構上形成犧牲“虛設(dummy)”Mx+1線116。這可藉由非等向性蝕刻第3圖的犧牲層112而停在蝕刻停止層110上來完成,如此去除該犧牲層未被該圖案化抗蝕層覆蓋的部分,以形成犧牲“虛設”線116,然後再去除抗蝕層114。在一些實施例中,蝕刻停止層110也可被去除。注意Mx和Mx+1都顯示為在各層級的單向並行線的常規組合,而Mx+1垂直Mx。
第5圖是隨後沉積介電層118於該犧牲Mx+1線上方的製程步驟之後的半導體結構100的側視圖,沿著第4圖的線A-A’所示。在實施例中,介電層118可包括碳氧化矽(SiOC)。該介電層可用電漿增強化學氣相沉積(PECVD)製程來沉積。在實施例中,由於介電層118的保形特性,空氣間隙120可形成在各犧牲線116之間。該空氣間隙具有約1的介電常數,且因此可用於改善關於高速信號傳播通過BEOL層的電路性能。
第6圖是隨後平坦化介電層118使得它基本上是與犧牲線116等高的製程步驟之後的半導體結構100的側視圖。在實施例中,該平坦化是採用化學機械拋光(CMP)製程。空氣間隙120可在此過程中保留(如圖所示),
或在一些實施例中,可以部份打開(圖未示出)。
第7圖是隨後沉積且圖案化線切口微影堆疊物122的製程步驟之後的半導體結構100。線切口微影堆疊物122可包括有機平坦化層(OPL)以及隨後的光阻層(稱為“抗蝕”)。在實施例中,該OPL可包括光敏有機聚合物,其包括光敏材料,當暴露在電磁波(EM)輻射下,會產生化學變化從而能夠用顯影溶劑除去。例如,該光敏有機聚合物可以是聚丙烯酸酯樹脂、環氧樹脂、酚醛樹脂、聚醯胺樹脂、聚醯亞胺樹脂、不飽和聚酯樹脂、聚苯醚樹脂、聚苯硫醚樹脂、或苯並環丁烯(BCB)。
多個空隙124被圖案化於微影堆疊物122中。空隙124各別暴露在犧牲線116的區域,以及一些介電區118。介電層118和犧牲線116包括不同材料,允許選擇性的蝕刻技術去除犧牲線116穿過空隙124暴露出的部分,而不必去除介電區118。因此,各空隙124的位置和尺寸的公差是有彈性的,能夠更容易地製造且改善產品良率。
第8圖是隨後在犧牲Mx+1線中形成切穴126的製程步驟之後的半導體結構100。如同前述,介電層118和犧牲線116包括不同材料,允許選擇性蝕刻技術去除犧牲線116的部分。因此,去除犧牲線116的暴露區域,露出下面的蝕刻停止層110,並且形成切穴126。
第9圖是隨後去除該線切口微影堆疊物(第7圖中的122)的製程步驟之後的半導體結構100。該微影堆
疊物可以用工業級標準技術來去除,因此揭示出犧牲線116與切穴126在該替代(金屬)線被分開位置的圖案。
第10圖是根據本發明的一替代實施例,隨後去除線切口微影堆疊物122的抗蝕層(見第7圖),暴露出底層的有機平坦化層(OPL)的製程步驟之後的半導體結構。因此第10圖從第7圖得到,但提供額外的製程步驟來進一步控制該切穴的尺寸,如同將在下圖中所示出的。空隙124在有機平坦化層128中形成以暴露出區域犧牲線116。
第11圖是根據本發明的一替代實施例,隨後沉積保形間隔件層(conformal spacer)130的製程步驟之後的半導體結構。在實施例中,保形間隔件層130包括碳,並且可經由原子層沉積製程來沉積。在實施例中,該保形間隔件層具有約2奈米到約5奈米範圍的厚度。在該有機平坦化層中的空隙124上方形成凹部132。
第12圖是根據本發明的一替代實施例,隨後進行非等向性蝕刻以形成孔間隔件134的製程步驟之後的半導體結構。在實施例中,該非等向性蝕刻可包括反應性離子蝕刻(RIE)製程。該非等向性蝕刻去除該保形間隔件層的大部分,除了剩餘部分,也就是孔間隔件134。孔間隔件134具有區段厚度D1。在實施例中,D1的範圍是從約2奈米到約8奈米。在去除犧牲線116的部分以具有長度D2之前,該孔間隔件進一步限制了該開口,因此能夠縮小化切穴。在實施例中,D2可具有約5奈米到30奈米
的範圍。
第13圖是根據本發明的一替代實施例,隨後在犧牲Mx+1線中形成切穴的製程步驟之後的半導體結構。如同前述,介電層118和犧牲線116包括不同材料,允許選擇性蝕刻技術去除犧牲線116的部分。然後可以選擇性地蝕刻掉該碳間隔件。
第14圖是在切穴中形成介電區118A的製程步驟之後的半導體結構。從第14圖開始,該製程相似於第1圖到第9圖所示的實施例,以及第10圖到第13圖所示的附加步驟的替代實施例。如第14圖所示,附加介電材料118A沉積在各切穴中。可接著進行平坦化製程使得介電區118A基本上和犧牲線116及介電區118一樣平坦。這可以通過化學機械拋光(CMP)製程和/或非等向性RIE回蝕來完成。介電區118A和介電區118最好是由相同材料製成。因此,在實施例中,介電區118A也可以包括碳氧化矽。
第15圖是隨後去除該犧牲Mx+1線的製程步驟之後的半導體結構。這可以採用選擇性蝕刻製程來完成,讓介電區118和118A維持完整。
第16圖是隨後沉積且圖案化通孔切口微影堆疊物136的製程步驟之後的半導體結構。通孔切口微影堆疊物136可包含有機平坦化層、抗反射層和抗蝕層。使用圖案化會在通孔切口微影堆疊物136中形成空隙138。該空隙會在已經去除犧牲線116之處的上方形成,從而揭
露出沉積在該金屬層下面的垂直向Mx線的帽層105部分。根據給定的設計,理想上在某些位置形成互連鄰近金屬化層級的通孔。因此,空隙會在希望於Mx線和Mx+1線之間形成通孔的地方形成。
第17圖是隨後形成暴露出Mx金屬線的切穴的製程步驟之後的半導體結構。該帽層(見第16圖的105)的區域採用選擇性蝕刻製程來去除。例如,若介電層118是碳氧化矽,且帽層105是氮化矽,則可以使用各種選擇性蝕刻技術來選擇性去除帽層105。本發明的實施例可使用其他材料的介電層和帽層,只要這些材料對彼此的選擇性蝕刻是有可能的。
第18圖是隨後去除該通孔切口微影堆疊物(第17圖的136)的製程步驟之後的半導體結構。這會暴露出帽層105未有通孔形成的區域,其中Mx線106是暴露在通孔形成的範圍。
第19圖是隨後形成金屬Mx+1線的製程步驟之後的半導體結構。在實施例中,這可包括電鍍製程。該製程可包括沉積一或多道阻擋層和/或晶種層(未示出)。然後,在犧牲Mx+1線先前佔據的位置沉積填充金屬(例如銅),形成金屬化線142。介電區118A分開金屬化線142A和金屬化線142A’。因此,金屬化線142A和金屬化線142A’是預切的,因為它們具有切口的形成已經到位,並因此避免了金屬切割。金屬化線142B具有通孔以連接到該Mx層級,這將在接下來的圖中進一步描述。
第20圖是第19圖中沿著線B-B’所示的半導體結構。如可以看到的,Mx+1金屬線142B連接到Mx金屬線106。當Mx+1線142B形成時,Mx線106會暴露出,因為它的帽層被去除(見第18圖的106)。因此,根據本發明的實施例,該製程藉由避免金屬切割而簡化製造,並且也整合通孔進入該金屬化製程的連接性。
第21圖是用於表示本發明實施例的製程步驟的流程200。在製程步驟250,形成犧牲線。在實施例中,該犧牲線包括氮化矽。在製程步驟252,沉積介電層。在實施例中,該介電層包括碳氧化矽。在製程步驟254,沉積線切口微影堆疊物(見第7圖的122)。在製程步驟256,切割該犧牲線(見第9圖)。在製程步驟258,沉積附加電介質於該切穴(見第14圖的118A)中。在製程步驟260,去除該犧牲線(見第15圖)。在實施例中,也可以去除該蝕刻停止層(第1圖的110)。在製程步驟262,沉積通孔穴微影堆疊物(見第16圖的136)。在製程步驟264,所選定的M(x)線在通孔於該M(x)和M(x+1)層級間形成的地方打開(見第17圖的140)。在製程步驟266,形成M(x+1)金屬線(見第19圖的142)。然後,本文所揭露的製程可重複製造出多個金屬化層級。在一些實施例中,可以有10層或更多層。一旦該BEOL堆疊完成,附加製程的工業級標準技術,像是封裝和測試可用來完成該積體電路的製造。
雖然本發明已經結合示例性實施例具體示出及描述,但可以理解的是,對於本領域技術人士,變化
和修改將可想到的。例如,儘管本文中所示出的說明性實施例是一系列動作或事件,但應當理解的是,本發明不受這些行為或事件的所示順序所限制,除非特別說明。一些動作可以按不同順序和/或同時與其它動作或事件發生,除了那些在本文中根據本發明示出和/或描述的之外。此外,並非所有示出的步驟中可需要根據本發明的方法來實現。此外,根據本發明的方法可以結合與本文中所描述或示出的結構的形成和/或工藝以及其他未示出的結構來實現。因此,可以理解的是,所附的申請專利範圍旨在包含所有這些落在本發明的真實精神內的修改和改變。
200‧‧‧製程步驟的流程
250‧‧‧製程步驟
252‧‧‧製程步驟
254‧‧‧製程步驟
256‧‧‧製程步驟
258‧‧‧製程步驟
260‧‧‧製程步驟
262‧‧‧製程步驟
264‧‧‧製程步驟
266‧‧‧製程步驟
Claims (20)
- 一種形成半導體結構的方法,包括:在多個金屬Mx線上方形成多個犧牲Mx+1線;在該多個犧牲Mx+1線上方沉積介電層;在該多個犧牲Mx+1線的其中一個犧牲Mx+1線中形成切穴;在該切穴中形成介電區;去除該多個犧牲Mx+1線以形成多個Mx+1線穴;以及以金屬填充該多個Mx+1線穴以形成多個金屬Mx+1線。
- 如申請專利範圍第1項所述的方法,其中,形成多個犧牲Mx+1線包括:在該多個金屬Mx線上方沉積犧牲層;在該犧牲層上沉積微影堆疊物;圖案化該微影堆疊物以形成圖案化微影堆疊物;去除該犧牲層未被該圖案化微影堆疊物覆蓋的部分;以及去除該微影堆疊物。
- 如申請專利範圍第1項所述的方法,其中,沉積介電層包括沉積碳氧化矽。
- 如申請專利範圍第3項所述的方法,更包括平坦化該介電層。
- 如申請專利範圍第4項所述的方法,其中,平坦化該 介電層包括進行化學機械拋光製程。
- 如申請專利範圍第1項所述的方法,其中,填充該多個具有金屬的Mx+1線穴包括用銅填充該多個Mx+1線穴。
- 一種形成半導體結構的方法,包括:在多個金屬Mx線上方形成多個犧牲Mx+1線;在該多個犧牲Mx+1線上方沉積介電層;在該介電層上沉積有機平坦化層;在該有機平坦化層上沉積抗蝕層;在該抗蝕層和有機平坦化層中形成凹穴;去除該抗蝕層;在該有機平坦化層上沉積保形間隔件層;在該保形間隔件層上進行非等向性蝕刻以形成孔間隔件;在該多個犧牲Mx+1線的其中一個犧牲Mx+1線中形成切穴;在該切穴中形成介電區;去除該多個犧牲Mx+1線以形成多個Mx+1線穴;以及用金屬填充該多個Mx+1線穴以形成多個金屬Mx+1線。
- 如申請專利範圍第7項所述的方法,其中,沉積保形間隔件層包括沉積碳。
- 如申請專利範圍第8項所述的方法,其中,沉積碳係 以原子層沉積製程來進行。
- 如申請專利範圍第7項所述的方法,其中,形成多個犧牲Mx+1線包括:在該多個金屬Mx線上方沉積犧牲層;在該犧牲層上沉積微影堆疊物;圖案化該微影堆疊物以形成圖案化微影堆疊物;去除該犧牲層未被該圖案化微影堆疊物覆蓋的部分;以及去除該微影堆疊物。
- 如申請專利範圍第7項所述的方法,其中,沉積介電層包括沉積碳氧化矽。
- 如申請專利範圍第11項所述的方法,更包括平坦化該介電層。
- 如申請專利範圍第12項所述的方法,其中,平坦化該介電層包括進行化學機械拋光製程。
- 如申請專利範圍第7項所述的方法,其中,用金屬填充該多個Mx+1線穴包括用銅填充該多個Mx+1線穴。
- 一種形成半導體結構的方法,包括:在多個金屬Mx線上方形成多個犧牲Mx+1線;在該多個犧牲Mx+1線上方沉積介電層;在該多個犧牲Mx+1線的其中一個犧牲Mx+1線中形成切穴;在該切穴中形成介電區;去除該多個犧牲Mx+1線以形成多個Mx+1線穴; 沉積通孔切口微影堆疊物;在該通孔切口微影堆疊物中圖案化開口;形成暴露出該多個金屬Mx線的其中一個Mx金屬線之通孔穴;去除該通孔切口微影堆疊物;以及用金屬填充該多個Mx+1線穴和該通孔穴以形成多個金屬Mx+1線和通孔。
- 如申請專利範圍第15項所述的方法,其中,形成多個犧牲Mx+1線包括:在該多個金屬Mx線上方沉積犧牲層;在該犧牲層上沉積線切口微影堆疊物;圖案化該線切口微影堆疊物以形成圖案化線切口微影堆疊物;去除該犧牲層未被該圖案化線切口微影堆疊物覆蓋的部分;以及去除該圖案化線切口微影堆疊物。
- 如申請專利範圍第15項所述的方法,其中,沉積介電層包括沉積碳氧化矽。
- 如申請專利範圍第17項所述的方法,更包括平坦化該介電層。
- 如申請專利範圍第18項所述的方法,其中,平坦化該介電層包括進行化學機械拋光製程。
- 如申請專利範圍第19項所述的方法,其中,用金屬填充該多個Mx+1線穴包括用銅填充該多個Mx+1線穴。
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-
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Also Published As
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