CN105378923B - 半导体装置的制造方法以及pin二极管 - Google Patents

半导体装置的制造方法以及pin二极管 Download PDF

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CN105378923B
CN105378923B CN201380078145.7A CN201380078145A CN105378923B CN 105378923 B CN105378923 B CN 105378923B CN 201380078145 A CN201380078145 A CN 201380078145A CN 105378923 B CN105378923 B CN 105378923B
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pin diode
layer
diode
type layer
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CN105378923A (zh
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藤井秀纪
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Mitsubishi Electric Corp
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Abstract

在半导体衬底(1)形成IGBT(15)。在半导体衬底(1)上利用多晶硅或者非晶硅形成温度感测二极管(17)。在形成IGBT(15)之后将温度感测二极管(17)的一部分选择性地氧化或者升华，从而将温度感测二极管(17)分割为多个二极管。由此，能够消除由多晶硅的完成尺寸的波动导致的对特性的影响。其结果，能够抑制特性波动并实现小型化。

Description

半导体装置的制造方法以及PIN二极管
技术领域
本发明涉及利用多晶硅或非晶硅形成PIN二极管的半导体装置的制造方法。
背景技术
在IPM等功率模块中，为了监视工作温度，在IGBT中内置有温度感测二极管。温度感测二极管是由多晶硅或非晶硅构成的PIN二极管(例如，参照专利文献1)。监视该二极管的VF特性，进行温度的管理、保护。为了保证高精度的温度，要求温度感测二极管具有高精度的VF特性的温度依赖性。另外，在由于异常动作等而功率芯片急剧地温度上升的情况下，还要求瞬间追随的高速响应性。
专利文献1：日本特表2003-520441号公报
发明内容
多晶硅二极管的特性由下述因素决定，即：多晶硅的膜厚度、离子注入量、热处理条件(温度时间)、多晶硅的完成尺寸、以及多晶硅的膜质(晶粒的大小)。对于离子注入量和多晶硅的完成尺寸的波动，如果将二极管的面积加大则能够忽视，但是存在装置整体的面积变大的问题。另外，还存在二极管受到形成IGBT时的热处理的影响，二极管的特性发生波动的问题。
本发明就是为了解决上述课题而提出的，其目的在于获得一种能够抑制特性波动并实现小型化的半导体装置的制造方法。
本发明涉及的半导体装置的制造方法，其特征在于，具有：在半导体衬底形成晶体管的工序；在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；以及在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序。
发明的效果
根据本发明，能够抑制特性波动并实现小型化。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是沿图1的I—II的剖视图。
图3是表示本发明的实施方式1涉及的二极管的俯视图。
图4是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图6是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图7是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图8是表示本发明的实施方式1涉及的半导体装置的制造方法的俯视图。
图9是表示本发明的实施方式1涉及的半导体装置的制造方法的俯视图。
图10是表示本发明的实施方式2涉及的二极管的俯视图。
图11是表示本发明的实施方式3涉及的二极管的剖视图。
图12是表示本发明的实施方式4涉及的二极管的剖视图。
图13是表示本发明的实施方式5涉及的二极管的俯视图。
图14是表示本发明的实施方式6涉及的二极管的剖视图。
图15是表示本发明的实施方式7涉及的二极管的剖视图。
图16是表示本发明的实施方式8涉及的二极管的剖视图。
图17是表示本发明的实施方式9涉及的二极管的剖视图。
图18是表示本发明的实施方式10涉及的二极管的剖视图。
图19是表示本发明的实施方式11涉及的二极管的剖视图。
图20是表示本发明的实施方式12涉及的二极管的剖视图。
图21是表示本发明的实施方式13涉及的二极管的剖视图。
图22是表示本发明的实施方式13涉及的二极管的下层部的俯视图。
图23是表示本发明的实施方式14涉及的二极管的剖视图。
图24是表示本发明的实施方式15涉及的二极管的剖视图。
图25是表示本发明的实施方式16涉及的二极管的剖视图。
图26是表示本发明的实施方式16涉及的二极管的俯视图。
图27是表示本发明的实施方式17涉及的二极管的俯视图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置的制造方法进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。图2是沿图1的I—II的剖视图。在由n型的硅构成的半导体衬底1的表面依次形成有n型层2、p型基极层3。在p型基极层3内形成有n+型发射极层4和p+型接触层5。在半导体衬底1的表面侧形成沟槽6，在该沟槽6内经由栅极绝缘膜7形成有由n+型的多晶硅构成的沟槽栅极8。
在沟槽栅极8上形成有氧化膜9。沟槽栅极8经由Al配线10与栅极焊盘11连接。由Al构成的发射极电极12与p+型接触层5连接。在半导体衬底1的背面形成有n型缓冲层13和p型集电极层14。由这些结构构成IGBT 15(Insulated Gate Bipolar Transistor)。
在半导体衬底1的表面上形成有厚度的由SiO2构成的氧化膜16。在该氧化膜16上形成有温度感测二极管17。温度感测二极管17通过氧化膜16与半导体衬底1电气隔离。温度感测二极管17具有从中央向外侧配置成同心圆状的n+型层18、p+型层19以及n-型层20。n+型层18经由Al配线21与阴极焊盘22连接，p+型层19经由Al配线23与阳极焊盘24连接。
以覆盖温度感测二极管17的方式形成有氧化膜25。氧化膜25以及Al配线10、21、23被保护膜26覆盖。保护膜26是在厚度折射率2.2～2.7的SInSiN半绝缘膜上，层叠厚度折射率1.8～2.2的绝缘膜而成的。
图3是表示本发明的实施方式1涉及的二极管的俯视图。温度感测二极管17由多晶硅或非晶硅构成，将n+型层18以及n-型层20的一部分选择性地氧化而分割为4个二极管。分割为4个的二极管并联连接。
下面，对本实施方式的半导体装置的制造方法进行说明。图4-7是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图，图8以及图9是表示本发明的实施方式1涉及的半导体装置的制造方法的俯视图。但是，图8以及图9是将二极管的部分放大后的图。
首先，如图4所示，形成IGBT 15的衬底顶面侧的MOS构造。接着，如图5所示，通过在半导体衬底1上堆积氧化膜并图案化，从而形成氧化膜9、16。然后，使厚度的多晶硅膜27成膜，将1E12～1E14[1/cm2]的磷或砷注入至整个面，决定n-型层20的浓度。此外，也可以用掺杂多晶硅或非晶硅代替多晶硅膜27。另外，在p+p-n+型的PIN二极管的情况下注入硼以代替磷或砷。
接着，如图6所示，通过照相制版将多晶硅膜27图案化而形成温度感测二极管17的构造。接着，如图7所示，在p+型层19的部分注入1E13～1E16[1/cm2]的硼，在n+型层18的部分注入1E13～1E16[1/cm2]的磷或砷，并通过热处理(900℃～1200℃、30分～120分)而活性化。在该阶段中温度感测二极管17如图8所示。
接着，如图9所示，通过在氧气氛中选择性地进行RTA(Rapid Thermal Annealing：激光退火、电子束退火或者灯退火、脉冲灯退火等)，将温度感测二极管17的一部分选择性地氧化而形成氧化膜28，从而将温度感测二极管17分割为多个二极管。
接着，堆积厚度的氧化膜25，在将接触部分开口后，通过蒸镀或者溅射形成厚度1μm～10μm的Al膜。将Al膜图案化而形成Al配线10、21、23。接着，使保护膜26成膜，将进行导线配线的发射极电极12、栅极焊盘11等上的保护膜26除去。最后，将半导体衬底1的背面研磨至希望的厚度，通过离子注入和热处理在半导体衬底1的背面形成n型缓冲层13和p型集电极层14。
在本实施方式中，通过将温度感测二极管17的一部分选择性地氧化，能够形成多个小型的二极管。通过分割为多个二极管，能够消除由多晶硅的完成尺寸的波动导致的对特性的影响。其结果，能够抑制特性波动并实现小型化。
实施方式2
图10是表示本发明的实施方式2涉及的二极管的俯视图。在本实施方式中分割为4个的二极管串联连接。其他的结构与实施方式1相同。如上所述，能够自由地设定分割的二极管的连接关系。
实施方式3
图11是表示本发明的实施方式3涉及的二极管的剖视图。在本实施方式中将温度感测二极管17的n+型层18、n-型层20以及p+型层19分别利用RTA进行热处理并再结晶化。这时施加小于或等于硅的沸点的热量。
多晶硅的电阻是晶粒的电阻和晶粒的边界部的电阻之和。由于晶粒的边界部作为陷阱能级起作用，因此边界部越多则响应性越差。另外，由于高温连续通电而引起晶粒的边界部的状态发生变化、特性发生变动。因此，通过对PIN二极管进行热处理并再结晶化，能够改善这些问题。
此外，不限定于将多晶硅整体再结晶化，也可以是将一部分再结晶化而使晶粒的大小变大的程度。由此，能够调整PIN二极管的特性。另外，再结晶化处理只要是在多晶硅成膜后，则无论是在氧化膜28的形成的前后、杂质注入的前后，在任何时刻进行均可。
实施方式4
图12是表示本发明的实施方式4涉及的二极管的剖视图。如果将二极管小型化，则导致接触电阻增大。因此，在本实施方式中将n+型层18选择性地再结晶化。由此，能够降低阴极的接触电阻。
实施方式5
图13是表示本发明的实施方式5涉及的二极管的俯视图。如果将二极管小型化，则导致ESD耐量下降。因此，在本实施方式中将n-型层20选择性地再结晶化。由此，能够缓和由浪涌电流引起的电流集中，因此能够提高ESD耐量。此外，通过使再结晶化的程度变化，能够对特性进行调整。
实施方式6
图14是表示本发明的实施方式6涉及的二极管的剖视图。在本实施方式中将n+型层18和n-型层20选择性地再结晶化。由此，能够取得实施方式4、5的效果。
实施方式7
图15是表示本发明的实施方式7涉及的二极管的剖视图。在本实施方式中将p+型层19选择性地再结晶化。由此，能够降低阳极的接触电阻。另外，由于晶粒的边界(晶粒的边界部)处的空穴不会被消灭，因此能够实现高速响应。
实施方式8
图16是表示本发明的实施方式8涉及的二极管的剖视图。在本实施方式中将n+型层18与n-型层20的结区域29以及p+型层19与n-型层20的结区域30选择性地再结晶化。由此，能够减小漏电流而实现高速响应。
实施方式9
图17是表示本发明的实施方式9涉及的二极管的剖视图。在本实施方式中将除了结区域29、30以外的区域选择性地再结晶化。在该情况下也能够得到实施方式4～7的效果。
实施方式10
图18是表示本发明的实施方式10涉及的二极管的剖视图。在本实施方式中将温度感测二极管17的各层的上层部选择性地再结晶化。由此，各层成为并联连接2个电阻的构造。能够根据再结晶化的程度对PIN二极管的特性进行调整。
实施方式11
图19是表示本发明的实施方式11涉及的二极管的剖视图。在本实施方式中将温度感测二极管17的n+型层18的上层部选择性地再结晶化。由此，能够降低阴极的接触电阻。
实施方式12
图20是表示本发明的实施方式12涉及的二极管的剖视图。多晶硅膜27的厚度的波动对VF特性造成的影响大。因此，在本实施方式中，仅将温度感测二极管17的各层的上层部氧化而形成氧化膜31。由此，能够高精度地控制下层部的厚度，因此能够降低由多晶硅膜27的厚度的波动所引起的VF波动。另外，通过对进行氧化的区域和其厚度进行调整，能够对特性进行调整。另外，能够通过利用RTA而选择性地进行热处理，从而高精度地形成氧化膜31，因此能够高精度地调整温度感测二极管17的特性。
实施方式13
图21是表示本发明的实施方式13涉及的二极管的剖视图。图22是表示本发明的实施方式13涉及的二极管的下层部的俯视图。在本实施方式中将p+型层19的上层部和n+型层18的上层部选择性地氧化而形成氧化膜31。
由于多晶硅膜27形成在氧化膜16上，因此半导体衬底1与多晶硅膜27的高低差较大。从而，在对氧化膜25进行蚀刻而同时形成达到半导体衬底1的接触孔和达到温度感测二极管17的接触孔时，由蚀刻过度所造成的损伤会施加于温度感测二极管17，接触电阻会变高。
与此相对，在本实施方式中p+型层19的下层部和n+型层18的下层部与半导体衬底1的高度差变小，因此能够减小由接触蚀刻造成的损伤、降低接触电阻。另外，n-型层20没有被氧化而维持较厚，因此能够得到高的ESD耐量，而没有使流过n-型层20的电流路径变窄。
实施方式14
图23是表示本发明的实施方式14涉及的二极管的剖视图。在本实施方式中将n-型层20的上层部选择性地氧化。由此，无需改变电子和空穴的注入量而能够对电流路径的宽度进行调整，因此能够更加高精度地调整特性。另外，还能够实现高电流密度动作。
实施方式15
图24是表示本发明的实施方式15涉及的二极管的剖视图。在本实施方式中将除了结区域29、30以外的区域的上层部选择性地氧化。由此，能够取得实施方式13、14的效果，并且还能够实现高温动作。
实施方式16
图25是表示本发明的实施方式16涉及的二极管的剖视图。图26是表示本发明的实施方式16涉及的二极管的俯视图。在本实施方式中将p+型层19的上层部和n+型层18的上层部选择性地氧化而形成氧化膜31。将结区域29、30选择性地再结晶化。由此，能够取得实施方式8、13的效果。
实施方式17
图27是表示本发明的实施方式17涉及的二极管的俯视图。在本实施方式中通过RTA使温度感测二极管17的一部分选择性地升华而形成分离槽32。利用该分离槽32将温度感测二极管17分割为多个二极管。由此，能够取得与实施方式1等同样的效果。并且，不需要对RTA的功率、气氛进行调整，所以能够简单地形成。
此外，半导体衬底1不限定于由硅形成，也可以由与硅相比带隙宽的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或者金刚石。由这样的宽带隙半导体形成的半导体装置耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化的装置，能够使安装有该装置的半导体模块也小型化。另外，由于装置的耐热性高，因此能够将散热器的散热片小型化、能够空冷化而替换水冷部，因而能够将半导体模块进一步小型化。另外，装置的电力损耗低并且高效率，因此能够使半导体模块高效率化。
标号的说明
1 半导体衬底，15 IGBT(晶体管)，17 温度感测二极管(PIN二极管)，18 n+型层(n型层)，19 p+型层(p型层)，20 n-型层(i型层)，29、30 结区域。

Claims (10)

1.一种半导体装置的制造方法，其特征在于，具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层，
将所述n型层选择性地再结晶化。
2.一种半导体装置的制造方法，其特征在于，具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层，
将所述i型层选择性地再结晶化。
3.一种半导体装置的制造方法，其特征在于，具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层，
将所述p型层选择性地再结晶化。
4.一种半导体装置的制造方法，其具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层，
将所述n型层与所述i型层的结区域以及所述p型层与所述i型层的结区域选择性地再结晶化。
5.一种半导体装置的制造方法，其特征在于，具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层，
将除了所述n型层与所述i型层的结区域以及所述p型层与所述i型层的结区域以外的区域选择性地再结晶化。
6.一种半导体装置的制造方法，其特征在于，具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层，
将所述p型层的上层部、所述i型层的上层部以及所述n型层的上层部选择性地再结晶化。
7.一种半导体装置的制造方法，其特征在于，具有：
在半导体衬底形成晶体管的工序；
在所述半导体衬底上利用多晶硅或者非晶硅形成PIN二极管的工序；
在形成所述晶体管之后使所述PIN二极管的一部分选择性地氧化或升华，从而将所述PIN二极管分割为多个二极管的工序；以及
对所述多个二极管的一部分选择性地进行热处理而进行再结晶化、氧化或者晶粒大小的变更的工序，
将所述PIN二极管的上层部选择性地氧化，
所述PIN二极管具有横向排列配置的n型层、i型层以及p型层。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于，
将所述PIN二极管的p型层的上层部和n型层的上层部选择性地氧化。
9.根据权利要求7所述的半导体装置的制造方法，其特征在于，
将所述PIN二极管的i型层的上层部选择性地氧化。
10.根据权利要求7所述的半导体装置的制造方法，其特征在于，
将所述PIN二极管除了n型层与i型层的结区域和p型层与所述i型层的结区域以外的区域的上层部选择性地氧化。
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CN112005381B (zh) * 2018-04-27 2024-05-14 三菱电机株式会社 半导体装置以及电力转换装置
JP7268330B2 (ja) * 2018-11-05 2023-05-08 富士電機株式会社 半導体装置および製造方法
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