CN105280657A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN105280657A
CN105280657A CN201510321410.0A CN201510321410A CN105280657A CN 105280657 A CN105280657 A CN 105280657A CN 201510321410 A CN201510321410 A CN 201510321410A CN 105280657 A CN105280657 A CN 105280657A
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mentioned
insulating barrier
electrode
chip
semiconductor device
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CN105280657B (zh
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谷田一真
吉田贵光
内海邦朗
川崎敦子
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

根据实施方式，提供一种半导体装置。半导体装置具备绝缘层、电极和槽。绝缘层设在基板的表面上。电极埋设在绝缘层中，一方的端面从绝缘层露出。槽形成在基板表面的电极的周围。此外，槽以电极的外侧面为一方的侧面，绝缘层的表面侧被开放。埋设在绝缘层中的电极其一方的端面从绝缘层的表面突出。

Description

半导体装置及半导体装置的制造方法
本申请基于2014年7月8日提出的日本专利申请第2014－140390号享受优先权，在本申请中引用其全部内容。
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
以往，有通过将在基板上形成有半导体元件或集成电路的芯片多级贴合来减小半导体装置的占用面积的技术。在贴合的芯片的各贴合面上设有绝缘层，在各绝缘层的对应的位置上，设有通过贴合而连接芯片的多个电极。将这样的各芯片在进行研磨以使贴合面变平坦后贴合。
但是，在将各芯片的贴合面研磨的工序中，有绝缘层的贴合面和电极的贴合面不为同面的情况。在这样的情况下，有在芯片彼此的接合部分发生接合不良而成品率下降的情况。
发明内容
本发明要解决的课题是，提供一种能够使成品率提高的半导体装置及半导体装置的制造方法。
一技术方案的半导体装置具备：绝缘层，设置于基板的表面；电极，埋设于上述绝缘层，一方的端面从绝缘层露出；槽，形成在上述基板表面的上述电极的周围。
另一技术方案的半导体装置的制造方法包括：在基板的表面形成绝缘层；将一方的端面从上述绝缘层露出的电极埋设到上述绝缘层；在上述基板表面的上述电极的周围形成槽。
根据上述结构的半导体装置及半导体装置的制造方法，能够使成品率提高。
附图说明
图1是有关第1实施方式的半导体装置的立体的说明图。
图2是图1所示的半导体装置的分解立体图。
图3是表示有关第1实施方式的第2芯片的电极部分的俯视的说明图。
图4是表示图3所示的A－A′线的第2芯片的示意性的截面的说明图。
图5是表示有关第1实施方式的贴合前的第1芯片及第2芯片的示意性的截面的说明图。
图6是表示有关第1实施方式的贴合后的第1芯片及第2芯片的示意性的截面的说明图。
图7是表示在有关第1实施方式的第1芯片及第2芯片中发生了对位偏差的状态的说明图。
图8A～图9C是表示有关第1实施方式的半导体装置的制造工序的说明图。
图10是表示有关第1实施方式的变形例的第2芯片的示意性的截面的说明图。
图11是表示有关第2实施方式的第2芯片的示意性的截面的说明图。
图12A及图12B是表示有关第2实施方式的第2芯片的制造工序的说明图。
图13是表示有关第2实施方式的贴合前的第1芯片及第2芯片的示意性的截面的说明图。
图14A～图14C是表示有关第2实施方式的另一制造工序的说明图。
具体实施方式
根据本实施方式，提供一种半导体装置。半导体装置具备绝缘层、电极和槽。绝缘层设在基板的表面上。电极埋设在上述绝缘层中，一方的端面从绝缘层露出。槽形成在上述基板表面的上述电极的周围。
以下，参照附图详细地说明有关实施方式的半导体装置及半导体装置的制造方法。另外，并不通过这些实施方式限定本发明。此外，以下举半导体装置是固体摄像装置的情况为例进行说明，但有关实施方式的装置并不限定于固体摄像装置。
(第1实施方式)
图1及图2是表示有关第1实施方式的半导体装置1的立体的说明图，图2是图1所示的半导体装置1的分解立体图。如图1所示，半导体装置1具备相互贴合的第1芯片2和第2芯片3。
第1芯片2例如是具备将被摄体摄像的CMOS(ComplementaryMetalOxideSemiconductor)图像传感器20等的传感器芯片。此外，第2芯片3例如是具备从CMOS图像传感器20将摄像图像的图像信号读出、对所读出的图像信号进行各种信号处理的逻辑电路等的逻辑芯片。
另外，半导体装置1也可以是将第1逻辑芯片与第2逻辑芯片贴合的结构，也可以是将逻辑芯片与存储器芯片贴合的结构。此外，半导体装置1也可以是将3个以上的芯片贴合的结构。
如图2所示，第2芯片3具备设有逻辑电路等的基板31、设在基板31的上侧表面上的绝缘层32、和埋设在绝缘层32中并且一方的端面从绝缘层32露出的多个电极33。各电极33例如经由基板31内部的配线而与逻辑电路等连接。
另一方面，第1芯片2具备设有CMOS传感器20等的基板21、设在基板21的下侧表面上的绝缘层22、和埋设在绝缘层22的与第2芯片3的电极33对应的位置、一方的端面从绝缘层22露出的多个对应电极。各对应电极例如经由基板21内部的配线而与CMOS传感器20等连接。
对于这些第1芯片2及第2芯片3而言，在将各贴合面研磨而平坦化后，不使用粘接剂而直接贴合。由此，将第1芯片2和第2芯片3通过绝缘层22、32间的分子间力的氢键而临时接合。然后，对第1芯片2及第2芯片3实施热处理。由此，将第1芯片2和第2芯片3通过绝缘层22、32间的共价键而正式接合。
这样，在半导体装置1中，能够将设在第1芯片2所具备的CMOS图像传感器20的下表面上的对应电极与设在第2芯片3的上表面上的电极33连接。因而，例如通过第2芯片3所具备的逻辑电路，能够从CMOS图像传感器20的正下方进行信号的读出，所以能够减小芯片的占用面积。
在这样的半导体装置1中，在第1芯片2的贴合面被研磨的情况下，有绝缘层22的贴合面与对应电极的贴合面不为同面的情况。同样，在第2芯片3中，在贴合面被研磨的情况下，有绝缘层32的贴合面与电极33的贴合面不为同面的情况。
并且，如果第1芯片2的对应电极从绝缘层22的接合面突出，则当将第1芯片2与第2芯片3贴合时，有电极33与对应电极的接合部分向接合面的面方向鼓出(pushedout)而被夹在周围的绝缘层22、32间的情况。
这样，在电极33或对应电极的鼓出部分夹在绝缘层22、32间的情况下，有可能在绝缘层22、32间发生称作空隙的未接合部，空隙成为原因而第1芯片2从第2芯片3剥离，半导体装置1的成品率下降。
所以，在半导体装置1中，通过精心设计第1芯片2及第2芯片3的各贴合面的形状，能够实现成品率的提高。关于这样的第1芯片2及第2芯片3的接合部分的形状，接着参照图3及图4进行说明。
另外，第1芯片2及第2芯片3的各贴合面的结构是同样的，所以这里对第2芯片3的贴合面的形状进行说明，关于第1芯片2省略其说明。
图3是表示有关实施方式的第2芯片3的电极33部分的俯视的说明图。此外，图4是表示图3所示的A－A′线的第2芯片3的示意性的截面的说明图。另外，在图4中，有选择地图示了基板31上表面的设有绝缘层32的部分，关于其他部分省略了图示。
如图3及图4所示，第2芯片3具备埋设在绝缘层32中并且一方的端面从绝缘层32露出的电极33。电极33构造为，外侧面及底面由阻挡金属34形成，阻挡金属34的内周面被种子膜35覆盖、在被种子膜35覆盖的空间内设有由导电性材料形成的接触插头36。
这样的电极33如图4所示，连接在设于基板31内的配线37上，经由配线37与例如逻辑电路等连接。另外，在除了电极33与配线37的连接部以外的基板31与绝缘层32之间，设有绝缘膜38。
此外，第2芯片3如图3及图4所示，具备将电极33的外侧面作为一方的侧面、绝缘层32的表面侧被开放而将电极33以环状包围的槽39。由此，在半导体装置1中，即使第1芯片2的对应电极从绝缘层22的接合面突出，当将第1芯片2与第2芯片3贴合时，也能够抑制电极33与对应电极的接合部分夹在周围的绝缘层22、32间。关于这一点，接着参照图5及图6进行说明。
图5是表示有关第1实施方式的贴合前的第1芯片2及第2芯片3的示意性的截面的说明图，图6是表示有关第1实施方式的贴合后的第1芯片2及第2芯片3的示意性的截面的说明图。
这里，举第1芯片2的对应电极23从绝缘层22的接合面突出的情况为例进行说明。另外，图5所示的第2芯片3与图4所示的结构相同。因此，通过对于第2芯片3赋予与图4所示的标号同样的标号，省略其说明。
如图5所示，第1芯片2的贴合面部分为与第2芯片3的贴合面部分同样的结构，在基板21的内部设有配线27，在基板21的下侧表面上设有绝缘层22。此外，在绝缘层22上，在与第2芯片3的电极33对应的位置设有对应电极23。另外，在除了对应电极23与配线27的连接部以外的基板21与绝缘层22之间，设有绝缘膜28。
对应电极23与第2芯片3的电极33同样，是外侧面及底面由阻挡金属24形成、阻挡金属24的内周面被种子膜25覆盖、在被种子膜25覆盖的空间内设有接触插头26的构造。此外，第1芯片2与第2芯片3同样，具备将对应电极23的外侧面作为一方的侧面、绝缘层22的表面侧被开放而将对应电极23以环状包围的槽29。
在将这样的第1芯片2与第2芯片3贴合的情况下，如图5所示，首先，在第2芯片3上对置配置第1芯片2，进行对位，以使对应的第1芯片2的对应电极23位于第2芯片3的电极33上。
这里，在第1芯片2中，例如有因在研磨中使用的研磨液(slurry)的配合等而对应电极23没有被充分研磨、从绝缘层22的贴合面突出的情况。如果从该状态将第1芯片2向第2芯片3贴合，则对应电极23从绝缘层22突出，从而如图6所示，有对应电极23与电极33的接合部分向接合面的面方向鼓出的情况。
在这样的情况下，如果在绝缘层22、32上没有槽29、39，则对应电极23及电极33的鼓出的接合部分夹在绝缘层22、32间，发生空隙，成为接合不良或芯片剥离的原因。
所以，在半导体装置1中，在电极33的周围设有槽39，在对应电极23的周围设有槽29。由此，在半导体装置1中，这些槽29、39内的空间成为对应电极23及电极33的鼓出的接合部分的退避场所。
因而，根据半导体装置1，通过抑制由对应电极23及电极33的鼓出的接合部分夹入绝缘层22、32间带来的空隙或接合不良而引起的芯片剥离，能够使成品率提高。
此外，半导体装置1通过设置上述槽29、39，即使是在对应电极23和电极33的位置中发生了一些对位偏差的情况，也能够抑制电流的泄漏。关于这一点，接着参照图7进行说明。图7是表示在有关第1实施方式的第1芯片2及第2芯片3中发生了对位偏差的状态的说明图。
如图7所示，在半导体装置1中，在对应电极23和电极33的位置上发生了对位偏差的情况下，只要偏差量是槽29、39的宽度以下，第1芯片2的接触插头26及种子膜25就不会与第2芯片3的绝缘层32接触。同样，在半导体装置1中，第2芯片3的接触插头36及种子膜35不会与第1芯片2的绝缘层22接触。
因而，根据半导体装置1，只要对应电极23与电极33的位置的偏差量是槽29、39的宽度以下，就能够防止因接触插头26、36及种子膜25、35的材料向绝缘层22、32扩散而带来的电流的泄漏。
另外，为了防止对应电极23与第2芯片3的绝缘层32的接触、以及电极33与第1芯片2的绝缘层22的接触，虽然也取决于电极33及对应电极23的尺寸，但优选的是使槽29、39的宽度为0.2微米～5微米。由此，能够在抑制芯片面积的增大的同时防止电流的泄漏。
接着，参照图8A～图9C对有关第1实施方式的半导体装置1的制造方法进行说明。图8A～图9C是表示有关第1实施方式的半导体装置1的制造工序的说明图。这里，对形成第2芯片3的电极33部分的制造工序进行说明。另外，形成第1芯片2的对应电极23部分的制造工序与形成电极33的制造工序是同样的。
如图8A所示，在形成第2芯片3的电极33部分的情况下，准备在内部形成有配线37或逻辑电路等的基板31。另外，在形成第1芯片2的对应电极23部分的情况下，准备在内部形成有配线27或CMOS图像传感器20等的基板21。配线37例如是通过镶嵌法形成的Cu(铜)配线。
接着，在基板31的表面上，例如由氮化硅等的绝缘材料形成绝缘膜38后，在绝缘膜38的表面上例如由TEOS(四乙氧基硅烷，Tetraethoxysilane)等的绝缘材料形成绝缘层32。
然后，如图8B所示，在绝缘层32的电极33的形成位置形成开口41。这里，首先在绝缘层32的表面部分形成与之后形成的电极33的贴合面大致相同开口面积的孔后，形成从孔的底面中央达到配线37的上表面的导通孔，从而形成开口41。
接着，如图8C所示，在开口41的内周面及绝缘层32的上表面，例如通过Ta(钽)、TaN(氮化钽)、Ti(钛)、TiW(钛钨)等的导电材料将阻挡金属34成膜。
然后，在阻挡金属34的表面，例如通过Cu等的导电材料将镀层用的种子膜35成膜后，通过电解镀层使Cu析出在种子膜35的表面上而形成接触插头36。由此，形成电极33。另外，种子膜35及接触插头36的材料并不限定于Cu，也可以是Cu以外的金属。
接着，如图9A所示，例如通过CMP(ChemicalMechanicalPolishing)将绝缘层32及电极33上的不需要的Cu除去。然后，通过用修整(touchup)CMP将第2芯片3的表面研磨，将绝缘层32上的阻挡金属34除去，使绝缘层32及电极33的贴合面成为同面。
接着，如图9B所示，在除了槽39的形成位置以外的绝缘层32的上表面及电极33的上表面形成抗蚀剂51，以抗蚀剂51为掩模进行干式蚀刻。由此，如图9C所示，形成槽39。最后，通过将抗蚀剂51除去，完成图4所示的第2芯片3。另外，在将绝缘层32有选择地蚀刻的条件的情况下，不需要在电极33上形成抗蚀剂51。
如上述那样，有关第1实施方式的半导体装置1在基板31的表面上设有绝缘层32，在绝缘层32中埋设电极33。并且，在绝缘层32以将电极33包围的方式设有环状的槽39。
根据这样的半导体装置1，在第2芯片3的电极33从绝缘层32突出的情况下、或第1芯片2的对应电极23从绝缘层22突出的情况下，通过抑制第1芯片2从第2芯片3剥落，能够使成品率提高。
另外，在上述实施方式中，对通过将绝缘层22、32加工而形成槽29、39的情况进行了说明，但也可以如图10所示的变形例那样，通过将电极33加工而形成槽。
图10是表示有关第1实施方式的变形例的第2芯片3a的示意性的截面的说明图。另外，这里在图10所示的第2芯片3a的构成要素中，关于由与图4所示的第2芯片3的构成要素相同的材料形成、承担相同的功能的构成要素，通过赋予与图4所示的标号相同的标号，省略其说明。
对于变形例的第2芯片3a而言，阻挡金属34a由Ti或TiW形成、如图10所示那样通过将阻挡金属34a加工而形成槽39a这一点上与图4所示的第2芯片3不同。
这样，通过不将绝缘层32加工，而将第2芯片3a的表面侧的阻挡金属34a部分地除去，也能够形成将电极33a的外侧面作为一方的侧面、绝缘层32的表面侧被开放、将电极33a以环状包围的槽39a。
在这样的第2芯片3a中，将阻挡金属34a加工而形成的槽39a与图4所示的第2芯片3的槽39同样，成为对应电极23及电极33a的鼓出的接合部分的逃避场所。
因而，即使代替图4所示的第2芯片3而将图10所示的第2芯片3a应用到半导体装置1中，也与图1所示的半导体装置1同样，通过抑制芯片剥离而能够使成品率提高。
在制造有关本变形例的第2芯片3a的情况下，进行与图8A～图9A所示的制造工序同样的制造工序。但是，阻挡金属34a通过Ti或TiW形成。然后，例如进行基于氟酸的湿式蚀刻。
此时，由于阻挡金属34a由Ti或TiW形成，所以在基于氟酸的湿式蚀刻中，绝缘层32、种子膜35及接触插头36不被蚀刻，而阻挡金属34a被有选择地蚀刻。由此，根据本变形例，能够不使用图9B及图9C所示的抗蚀剂51而形成槽39a。
(第2实施方式)
接着，参照图11～图13，对有关第2实施方式的半导体装置进行说明。有关第2实施方式的半导体装置，除了绝缘层的形状与图5所示的绝缘层22、32不同这一点以外，是与有关第1实施方式的半导体装置1同样的结构。
此外，第2实施方式的第1芯片的绝缘层及第2芯片的绝缘层的形状是相同的。因此，这里对第2实施方式的第2芯片的形状进行说明，关于第1芯片省略其说明。
图11是表示第2实施方式的第2芯片3b的示意性的截面的说明图。此外，图12A及图12B是表示第2实施方式的第2芯片3b的制造工序的说明图。此外，图13是表示第2实施方式的贴合前的第1芯片2b及第2芯片3b的示意性的截面的说明图。
另外，这里，关于在图11所示的第2芯片3b的构成要素中的、由与图4所示的第2芯片3的构成要素相同的材料形成且承担相同的功能的构成要素，通过赋予与图4所示的标号相同的标号，省略其说明。
如图11所示，第2芯片3b与图4所示的第2芯片3的不同点在于，电极33的作为贴合面的一方端面从绝缘层32的表面突出了高度d的量。在制造这样的第2芯片3b的情况下，首先，如图12A所示，准备有关第1实施方式的第2芯片3。
并且，在设在第1芯片3中的电极33的作为贴合面的上表面上形成抗蚀剂52。接着，如图12B所示，通过以抗蚀剂52为掩模进行对于绝缘层32的蚀刻，使绝缘层32的贴合面及槽39的底面向绝缘层32的深度方向后退厚度d的量。然后，通过将抗蚀剂52除去，图11所示的第2芯片3b完成。另外，在将绝缘层32有选择地蚀刻的条件的情况下，不需要在电极33上形成抗蚀剂52。
根据这样的第2芯片3b，即使是电极33或对应电极23的贴合面在制造过程中凹陷的情况，也能够适当地使电极33与对应电极23连接。具体而言，如图13所示，第1芯片2b有在电极23的贴合面上发生凹陷的情况。
这样的凹陷，例如有时在使对应电极23及绝缘层22的贴合面成为同面的研磨工序中、对应电极23相比绝缘层22被过度地研磨的情况下发生。即使是这样的情况，如图13所示，根据第2实施方式，第1芯片2b的对应电极23也从绝缘层22的表面突出高度d的量，第2芯片3b的电极33也从绝缘层32的表面突出高度d的量。
因此，即使是对应电极23的贴合面凹陷的情况，通过将第1芯片2b与第2芯片3b贴合，也能够适当地使电极33与对应电极23连接。此外，在第1芯片2b上，与第1实施方式同样具有槽29，在第2芯片3b上也与第1实施方式同样具有槽39。
由此，根据第2实施方式，即使电极33与对应电极23的接合部分向接合面的面方向鼓出，也能够抑制鼓出的部分夹在绝缘层22、32间，所以能够抑制起因于芯片剥离的成品率的下降。
另外，使电极33的贴合面从绝缘层32的表面突出而在电极33的周围形成槽39的方法并不限定于图12A及图12B所示的制造工序。这里，参照图14A～图14C，对使电极33的贴合面从绝缘层32的表面突出、在电极33的周围形成槽39的其他的制造方法进行说明。图14A～图14C是表示有关第2实施方式的其他的制造工序的说明图。
另外，这里，关于在图14A～图14C所示的第2芯片3c的构成要素中的、由与图12B所示的第2芯片3b的构成要素相同的材料形成且承担相同的功能的构成要素，通过赋予与图12B所示的标号相同的标号，省略其说明。
在其他制造方法中，在将绝缘层32及电极33的表面研磨的情况下，调整研磨用的研磨液的配合，以将绝缘层32比电极33过度地研磨。由此，如图14A所示，研磨后的电极33成为从绝缘层32的表面突出的状态。
接着，如图14B所示，在除了槽39的形成位置以外的绝缘层32的上表面及电极33的上表面上形成抗蚀剂53，通过进行以抗蚀剂53为掩模的蚀刻，形成槽39。
然后，如图14C所示，通过将抗蚀剂53除去，能够制造出电极33的作为贴合面的一方端面从绝缘层32的表面突出的第2芯片3c。另外，在将绝缘层32有选择地蚀刻的条件的情况下，不需要在电极33上形成抗蚀剂53。
根据这样的其他制造方法，能够不进行使绝缘层32的贴合面后退的蚀刻，而制造电极33的贴合面从绝缘层32的表面突出、具备槽39的第2芯片3c。
如上述那样，根据第2实施方式，能够提供电极33的贴合面从绝缘层32的表面突出、具备槽39的第2芯片3c。根据第2实施方式，即使是在第2芯片3b、3c的电极33及第1芯片2b的对应电极23的贴合面上发生凹陷的情况，也能够适当地使电极33与对应电极23连接，能够抑制因连接不良带来的成品率的下降。
另外，在第1及第2实施方式中，对在贴合的两枚芯片两者的贴合面上具有槽的情况进行了说明，但槽也可以设在至少一方的芯片的贴合面上。只要在一方芯片上设置槽，该槽就成为电极的鼓出的接合部分的退避场所，所以只要电极的鼓出的接合部分比较小，就能够与第1及第2实施方式同样使成品率提高。
此外，在第2实施方式中，对使贴合的两枚芯片两者的电极从绝缘层突出的情况进行了说明，但使电极从绝缘层突出的，也可以是至少一方的芯片。通过这样的结构，也能够使贴合的两枚芯片的电极充分而适当地连接。
说明了本发明的一些实施方式，但这些实施方式是作为例子提示的，并不是要限定发明的范围。这些新的实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明和其等价的范围中。

Claims (19)

1.一种半导体装置，其特征在于，具备：
绝缘层，设置于基板的表面；
电极，埋设于上述绝缘层，一方的端面从绝缘层露出；以及
槽，形成在上述基板表面的上述电极的周围。
2.如权利要求1所述的半导体装置，其特征在于，
上述槽以上述电极的外侧面为一方的侧面，上述绝缘层的表面侧被开放。
3.如权利要求1所述的半导体装置，其特征在于，
上述电极的上述一方的端面从上述绝缘层的表面突出。
4.如权利要求1所述的半导体装置，其特征在于，具备：
其他基板，经由上述绝缘层与上述基板贴合；
绝缘层，设置于上述其他基板的贴合面；以及
对应电极，埋设在该绝缘层中的与上述电极对应的位置，一方的端面从该绝缘层的表面露出。
5.如权利要求4所述的半导体装置，其特征在于，
具备以上述对应电极的外侧面为一方的侧面、埋设该对应电极的上述绝缘层的表面侧被开放地将上述对应电极包围的槽。
6.如权利要求4所述的半导体装置，其特征在于，
上述电极和上述对应电极以在接合面的面方向上错开的状态连接；
在上述电极表面的非连接部与设有上述对应电极的上述绝缘层的表面之间、以及上述对应电极表面的非连接部与设有上述电极的上述绝缘层的表面之间具有空隙。
7.如权利要求4所述的半导体装置，其特征在于，
上述对应电极的一方的端面从设在上述其他基板侧的贴合面处的上述绝缘层的表面突出。
8.如权利要求4所述的半导体装置，其特征在于，
上述基板具备逻辑电路；
上述其他基板具备图像传感器。
9.如权利要求4所述的半导体装置，其特征在于，
上述基板具备逻辑电路；
上述其他基板具备存储器。
10.一种半导体装置的制造方法，其特征在于，包括：
在基板的表面形成绝缘层；
将一方的端面从上述绝缘层露出的电极埋设到上述绝缘层；以及
在上述基板表面的上述电极的周围形成槽。
11.如权利要求10所述的半导体装置的制造方法，其特征在于，包括：
形成以上述电极的外侧面为一方的侧面、上述绝缘层的表面侧被开放地将上述电极包围的上述槽。
12.如权利要求10所述的半导体装置的制造方法，其特征在于，包括：
通过蚀刻使上述绝缘层的表面有选择地后退，使上述电极从上述绝缘层的表面突出。
13.如权利要求10所述的半导体装置的制造方法，其特征在于，包括：
将埋设上述电极且形成上述槽之前的上述绝缘层，使用使上述绝缘层比上述电极过度地研磨的研磨液来研磨，使上述电极从上述绝缘层的表面突出。
14.如权利要求10所述的半导体装置的制造方法，其特征在于，包括：
在其他基板的表面形成绝缘层；
在该绝缘层中的与上述电极对应的位置，埋设表面露出的对应电极；以及
将埋设了上述对应电极的上述其他基板与埋设了上述电极的上述基板贴合。
15.如权利要求14所述的半导体装置的制造方法，其特征在于，包括：
形成以上述对应电极的外侧面为一方的侧面、形成在上述其他基板上的上述绝缘层的表面侧被开放地将上述对应电极包围的槽。
16.如权利要求10所述的半导体装置的制造方法，其特征在于，包括：
通过将上述绝缘层蚀刻而形成上述槽。
17.如权利要求10所述的半导体装置的制造方法，其特征在于，包括：
在上述绝缘层中的上述电极的形成位置形成开口；
将上述开口的内周面通过阻挡金属覆盖；
将内周面被上述阻挡金属覆盖的上述开口通过金属填埋而形成上述电极；以及
通过将上述阻挡金属从上述绝缘层的表面侧有选择地蚀刻而形成上述槽。
18.如权利要求14所述的半导体装置的制造方法，其特征在于，包括：
在上述基板形成逻辑电路；
在上述其他基板形成图像传感器。
19.如权利要求14所述的半导体装置的制造方法，其特征在于，包括：
在上述基板形成逻辑电路；
在上述其他基板形成存储器。
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