TWI532144B - 半導體裝置與其形成方法及半導體元件 - Google Patents

半導體裝置與其形成方法及半導體元件 Download PDF

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TWI532144B
TWI532144B TW102145313A TW102145313A TWI532144B TW I532144 B TWI532144 B TW I532144B TW 102145313 A TW102145313 A TW 102145313A TW 102145313 A TW102145313 A TW 102145313A TW I532144 B TWI532144 B TW I532144B
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substrate
metal
bonding pattern
conductive
metal bonding
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TW102145313A
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TW201426964A (zh
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張貴松
鄭鈞文
艾利克斯 卡尼斯基
朱家驊
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台灣積體電路製造股份有限公司
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Description

半導體裝置與其形成方法及半導體元件
本發明係關於半導體元件，更特別關於主動元件基板與被動元件基板之接合結構與其形成方法。
對小尺寸且高效能IC的需求，發展了系統單晶片(SOC)元件。部份的晶片用於記憶體，而其他部份的晶片則用於邏輯或其他種類的電路。然而整合不同電路的製程技術是個問題，因此難以製作多種電路的IC。
本發明一實施例提供一種裝置，包括：第一基板，包括至少一被動元件與第一金屬接合圖案於第一基板上，其中被動元件包括電容，且電容包括較上電容板、較下電容板、與介電層於較上電容板及較下電容板之間；以及第二基板，包括主動元件與第二金屬接合圖案於第二基板上，第二基板之第二金屬接合圖案對應第一基板之第一金屬接合圖案，且第一金屬接合圖案與第二金屬接合圖案合併形成導電金屬界面，其中主動元件經由導電金屬界面接合至被動元件。
本發明一實施例提供一種裝置的形成方法，包括：提供第一基板，且第一基板具有導電區於第一基板上；圖案化與蝕刻導電區，以形成至少一溝槽於導電區中；沉積介電 層於基板上，且介電層襯墊溝槽；將導電材料填入溝槽，且導電材料位於介電層上；形成至少一接觸通孔，以電性連接至導電材料；形成第一金屬接合圖案，第一金屬接合圖案具有至少平坦化層於一或多個接觸通孔上；提供第二基板與第一基板相鄰，其中第二基板包括第二金屬接合圖案於第二基板上，且第二金屬接合圖案對應第一基板的第一金屬接合圖案；以及接合第二基板之第二金屬接合圖案與第一基板之第一金屬接合圖案，以形成導電金屬界面。
本發明一實施例提供一種元件，包括：第一基板，包括溝槽式電容與第一金屬接合圖案於第一基板上；第二基板，包括CMOS元件與第二金屬接合圖案於第二基板上，第二基板之第二金屬接合圖案對應第一基板之第一金屬接合圖案，第一金屬接合圖案與第二金屬接合圖案合併形成導電金屬界面，且第二基板經由導電金屬界面接合至第一基板；以及封環包圍導電金屬界面。
100‧‧‧第一基板
102、202‧‧‧基板
104‧‧‧導電區
106‧‧‧硬遮罩層
108、109‧‧‧溝槽
110‧‧‧介電層
112‧‧‧導電材料
114‧‧‧介電氧化層
116‧‧‧接點
118、218‧‧‧金屬接合圖案
120(a)、120(b)‧‧‧開口
200‧‧‧第二基板
204‧‧‧主動元件
219(a)‧‧‧第一金屬層
219(b)‧‧‧第二金屬層
220(a)、220(b)‧‧‧導電金屬界面
222(a)、222(b)‧‧‧接觸墊
223、223(a)、223(b)‧‧‧封環
224(a)、224(b)‧‧‧焊料凸塊
300‧‧‧方法
302、304、306、308、310、312、314、316‧‧‧步驟
第1A至1J及1L圖係本發明一實施例中，形成裝置之製程的部份剖視圖；第1K圖係本發明一實施例中，形成裝置之製程的上視圖；以及第2圖係本發明某些實施例中，製作裝置的流程圖。
下述說明將配合圖示標號，而相同標號將用以標 示相同元件。圖示中的多種結構不一定依比例繪示。在下述說明中，特定的數值範圍僅用以方便了解，本技術領域中具有通常知識者在實際操作時可稍微超出特定的數值範圍。另一方面，以方塊圖標示已知結構及元件幫助理解。
在現有的VLSI技術中，CMOS晶片的主動元件經由晶圓/矽通孔(TSV)或中介片直接安裝於基板或接地面上，使訊號連接至基板或接地面。其他晶片之積體被動元件直接安裝於基板或接地面上，或直接安裝於具有主動區(如微控制器或功率放大器)的CMOS晶片上，端視積體方案而定。與積體被動元件晶片相較，主動元件通常為較先進的技術節點。打線接合常作為具有主動元件之晶片與具有被動元件之晶片之間的訊號線，而接合墊位於CMOS晶片上之主動區的邊緣附近。
長打線接合會在CMOS晶片上的主動元件之外新增高電感與高電容。此外，打線接合會劣化熱傳導的熱性質。另一方面，CMOS晶片上的主動元件之邊緣上的接合墊雖可連接主動元件至訊號線之間的打線接合，但浪費有價值的實際面積。凡此種種，均會降低設計彈性、增加設計成本、及/或增加製程成本。
綜上所述，本發明提供裝置與晶圓級的裝置製作方法，藉由導電金屬界面結合被動元件與主動元件，以消除外部電路如打線接合的必要性。進而最小化與穩定化寄生現象。
第1A至1J及1L圖係本發明一實施例中，以導電金屬界面接合具有主動元件之基板與被動元件之基板的裝置其製程剖視圖。如第1A圖所示，基板102具有導電區104。可以理 解的是，基板102包含半導體晶圓或基板，其組成可為半導體材料如矽、絕緣層上矽(SOI)結構、鍺、碳化矽、砷化鎵、砷化鋁鎵、磷化銦、氮化鎵、或鍺矽化物。導電區104之形成方法係將雜質導入基板102的特定區域中。為形成導電區104，可採用任何合適製程如佈植或熱擴散。
硬遮罩層106係位於基板102上。在一實施例中，硬遮罩層106可為單層或多層結構，並具有任何合適材料或其組合。在一實施例中，硬遮罩層106為氧化矽。硬遮罩層106可為其他合適材料，包括但不限於氮化矽與氮氧化矽。硬遮罩層106之形成方法可為任何合適製程或其組合。
接著將光阻層塗佈於硬遮罩層106上，並依所需圖案選擇性曝光光阻層，再顯影曝光後之光阻層。接著以圖案化的光阻作為遮罩蝕刻硬遮罩層106，使光阻層之溝槽圖案轉移至硬遮罩層106。在剝除光阻層後，進行蝕刻製程以蝕刻導電區104(形成溝槽108)與基板102(形成溝槽109)。蝕刻製程可為任何合適步驟，比如一般的電漿蝕刻。上述製程所形成的結構如第1B圖所示。在一實施例中，在形成溝槽後可移除硬遮罩層106。在另一實施例中，在形成溝槽後可保留硬遮罩層106，且硬遮罩層106將與後續沉積之介電層結合。
在第1C圖中，順應性地沉積介電層110以襯墊溝槽108、溝槽109、與蝕刻後的導電區104(請參考第1B圖)。介電層110可為任何合適介電材料之單層或多層結構。在一實施例中，介電層110可為四乙氧矽烷(TEOS)氧化物、氧化矽、氮氧化矽、或氮化矽。介電層110之形成方法可為任何合適製程或 其組合，比如低壓化學氣相沉積(LPCVD)或電漿增強化學氣相沉積(PECVD)。當實施例需要較厚的介電層時，較厚的介電層110除了襯墊溝槽108外還覆蓋基板102的上表面。
在第1D圖中，沉積導電材料112，以填入溝槽108與109中。一般而言，導電材料112之組成可為任何合適的導電材料與其組合，比如掺雜的半導體材料、金屬、或金屬化合物。金屬可為但不限於鎢、鈦、鉭、釕、鈷、銅、鋁、鉛、鉑、錫、銀、或金。金屬化合物可為但不限於氮化鉭、氮化鈦、鎢矽化物、氮化鎢、氮化鉭、氧化釕、鈷矽化物、或鎳矽化物。在一實施例中，導電材料112可為掺雜多晶矽。導電材料112之沉積製程可為任何合適製程或其組合，比如化學氣相沉積(CVD)或熱氧化。導電材料112可填入溝槽108並覆蓋基板102。在沉積導電材料112後，可進行化學機械研磨(CMP)及/或蝕刻製程以平坦化導電材料112，直到露出介電層106(若之前未移除)的上表面為止，如第1D圖所示。
如第1E圖所示，進行表面氧化製程以形成介電氧化層114於導電材料112、溝槽108、與基板102露出的表面上。在一實施例中，介電氧化層114之厚度可介於約5nm至5μm之間。接著進行另一圖案化步驟，以提供接觸通孔遮罩如第1F圖所示。接著進行蝕刻製程，以形成通孔穿過介電氧化層114。之後將金屬填入通孔以形成接點116。接點116電性連接至導電材料112或導電區104。
用以填入通孔以形成接點116之金屬可覆蓋介電氧化層114之表面。以CMP等製程平坦化金屬，直到露出介電 氧化層114之上表面與接點116的金屬表面。如第1F圖所示，接點116可電性連接至導電材料112或導電區104。
如第1G圖所示，接著形成金屬接合圖案118(具有至少一平坦化層)於硬遮罩層106中的接點116上。在一實施例中，金屬接合圖案118可為鋁、銅、金、或上述之組合。金屬接合圖案118之形成方法可為沉積金屬層，再形成光阻層於金屬層上。接著依所需圖案選擇性曝光並顯影光阻層，再以圖案化之光阻層作為遮罩以蝕刻金屬層，即形成金屬接合圖案118。
在第1H圖中，蝕刻硬遮罩層106與基板102以形成開口120(a)與120(b)於基板102中。如第1H圖所示，基板102具有一或多個溝槽式電容形成其上。溝槽式電容其較下方的電容板為導電區104，而較上方的電容板為溝槽108與109中的導電材料112。上述電容板之間隔有圍繞導電材料112的介電層，上述結構即電容。
在一實施例中，第1I圖中的基板200可包含主動元件204(如CMOS元件)於基板202中。內連線層206位於基板202與主動元件204上。基板202包含金屬接合圖案218(具有至少一平坦化層)於內連線層206上。在一實施例中，金屬接合圖案218之組成可為鋁、銅、鍺、金、或上述之組合。在一實施例中，金屬接合圖案218包含第一金屬層219(a)與第二金屬層219(b)，其中第一金屬層219(a)可為鋁、銅、金、鍺、或上述之組合，而第二金屬層219(b)可為鍺、鋁、金、或上述之組合。接著進行回火製程，以接合第一基板100之金屬接合圖案118與第二基板200之金屬接合圖案218，進而形成導電金屬界面 220(a)與220(b)以耦接電容與CMOS元件，如第1J圖所示。金屬接合圖案形成的導電金屬界面220(a)與220(b)具有鋁-鋁接合、金-金接合、金-鍺接合、鋁-鍺接合、銅-銅接合、或銅-鍺接合。在一實施例中，回火步驟之溫度介於約100℃至約500℃之間。
在接合製程後，可蝕刻或研磨保留之第一基板100的開口120(a)與120(b)，以露出接觸墊222(a)與222(b)。在一實施例中，可先露出內連線層206較上方的部份金屬層，以在接合製程前先形成接觸墊222(a)與222(b)於基板202上。在另一實施例中，可研磨第一基板100後再露出內連線層206較上方的部份金屬層，以在接合製程後形成接觸墊222(a)與222(b)。
第1K圖係第1J圖之結構的上視圖，封環223圍繞較內側的導電金屬界面220(a)與220(b)。封環223分為較內側邊緣的封環223(a)與較外側邊緣的封環223(b)。封環223密封並保護較內側的導電金屬界面220(a)與220(b)免於接觸水氣或後續製程的其他化學試劑。
如第1L圖所示，接觸墊222(a)與222(b)連接至外部電路。在一實施例中，上述連接可採用形成於接觸墊220(a)與220(b)上的焊料凸塊224(a)與224(b)。在另一實施例中，電性連接至外部電路的方式可為打線接合形成的打線。
第2圖係本發明一實施例中，形成元件之方法300的流程圖。雖然下述內容與圖式中的方法300為一連串的操作或事件，但可理解的是這些操作或事件的順序並不受限於下述內容與圖式中的順序。舉例來說，某些操作可以不同的順序進 行，甚至同時進行多種操作。此外，並非所有操作均為必要的操作。另一方面，可一步或多步進行下述操作。
步驟302提供第一基板，其具有導電區。步驟304圖案化與蝕刻導電區，以形成多個溝槽於導電區中。在某些實施例中，導電區可作為第一電容板。
步驟306沉積介電層於基板上並襯墊溝槽。步驟308接著沉積導電材料於溝槽中。在某些實施例中，介電層可作為電容介電層，而導電材料可作為第二電容板。
步驟310形成至少一接觸通孔，以電性連接至導電材料。
步驟312形成第一金屬接合圖案於接觸通孔上，且第一金屬接合圖案電性連接至溝槽式電容。
在步驟314中，具有第二金屬接合圖案之第二基板與具有第一金屬接合圖案之第一基板相鄰，且第二金屬接合圖案對應第一金屬接合圖案。第二基板與第一基板之形成製程可不相同。舉例來說，若第一基板進行簡單的溝槽式電容製程，則第二基板可進行較複雜的CMOS製程以形成主動元件於其上。
在步驟316中，將第二金屬接合圖案與第一金屬接合圖案接合在一起，以形成導電金屬界面。導電金屬界面將第一基板上的元件(如溝槽式電容)電性連接至第二基板上的元件(如CMOS元件)。如此一來，上述方法提供一種有效的方法，以電性耦接不同製程技術形成的基板及/或元件。
綜上所述，本發明提供之裝置包括：第一基板， 包括至少一被動元件如電容，且電容包括較上電容板、較下電容板、與介電層於較上電容板及較下電容板之間。第一基板包括第一金屬接合圖案於第一基板上。此裝置更包括第二基板，其包括主動元件與第二金屬接合圖案於第二基板上。第二基板之第二金屬接合圖案對應第一基板之第一金屬接合圖案，且第一金屬接合圖案與第二金屬接合圖案合併形成導電金屬界面。主動元件經由導電金屬界面接合至被動元件。
本發明更提供裝置的形成方法，包括：提供第一基板，且第一基板具有導電區於第一基板上，並圖案化與蝕刻導電區以形成至少一溝槽於導電區中。上述方法更沉積介電層於基板上，且介電層襯墊溝槽。接著將導電材料填入溝槽。上述方法更形成至少一接觸通孔，以電性連接至導電材料。接著形成第一金屬接合圖案，且第一金屬接合圖案具有至少一平坦化層於一或多個接觸通孔上。上述方法更提供第二基板與第一基板相鄰，其中第二基板包括第二金屬接合圖案於第二基板上，且第二金屬接合圖案對應第一基板的第一金屬接合圖案。之後接合第二基板之第二金屬接合圖案與第一基板之第一金屬接合圖案，以形成導電金屬界面。
本發明更提供一種元件，包括第一基板，其具有溝槽式電容與第一金屬接合圖案於第一基板上。此元件更包括第二基板，其具有CMOS元件與第二金屬接合圖案於第二基板上。第二基板之第二金屬接合圖案對應第一基板之第一金屬接合圖案。第一金屬接合圖案與第二金屬接合圖案合併形成導電金屬界面，且第二基板經由導電金屬界面接合至第一基板。此 元件亦包含封環包圍導電金屬界面。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧第一基板
202‧‧‧基板
118、218‧‧‧金屬接合圖案
200‧‧‧第二基板
204‧‧‧主動元件
220(a)、220(b)‧‧‧導電金屬界面
222(a)、222(b)‧‧‧接觸墊
223(a)、223(b)‧‧‧封環

Claims (9)

  1. 一種半導體裝置，包括：一第一基板，包括至少一被動元件與一第一金屬接合圖案於該第一基板上，其中該被動元件包括一電容，且該電容包括一較上電容板、一較下電容板、與一介電層於該較上電容板及該較下電容板之間；一第二基板，包括一主動元件與一第二金屬接合圖案於該第二基板上，該第二基板之該第二金屬接合圖案對應該第一基板之該第一金屬接合圖案，且該第一金屬接合圖案與該第二金屬接合圖案合併形成一導電金屬界面與一封環，其中該主動元件經由該導電金屬界面接合至該被動元件，其中該封環圍繞該導電金屬界面。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該導電金屬界面包括鋁-鋁接合、金-金接合、金-鍺接合、鋁-鍺接合、銅-銅接合、或銅-鍺接合。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第二基板包括一內連線層於該第二基板與該主動元件上，以及一接觸墊形成於該第二基板之該內連線層中的一開口中。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該第一基板包括一溝槽式電容，其中該上電容板包括一導電材料於個別的溝槽中，位於該較上電容板與該較下電容板之間的該介電層圍繞該導電材料，且該第二基板包括一CMOS元件，其中該導電金屬界面耦接該溝槽式電容與該CMOS元件。
  5. 一種半導體裝置的形成方法，包括： 提供一第一基板，且該第一基板具有一導電區於該第一基板上；圖案化與蝕刻該導電區，以形成至少一溝槽於該導電區中；沉積一介電層於該基板上，且該介電層襯墊該溝槽；將一導電材料填入該溝槽，且該導電材料位於該介電層上；形成至少一接觸通孔，以電性連接至該導電材料；形成一第一金屬接合圖案，該第一金屬接合圖案具有至少一平坦化層於一或多個該接觸通孔上；提供一第二基板與該第一基板相鄰，其中該第二基板包括一第二金屬接合圖案於該第二基板上，且該第二金屬接合圖案對應該第一基板的該第一金屬接合圖案；以及接合該第二基板之該第二金屬接合圖案與該第一基板之該第一金屬接合圖案，以形成一導電金屬界面與一封環，其中該封環包圍該導電金屬界面。
  6. 如申請專利範圍第5項所述之半導體裝置的形成方法，其中該第二基板之第二金屬接合圖案包括一第一金屬層與一第二金屬層，該第一金屬層包括鋁、銅、金、鍺、或上述之組合，而第二金屬層包括鍺、鋁、金、或上述之組合。
  7. 如申請專利範圍第5項所述之半導體裝置的形成方法，其中接合該第二基板之該第二金屬接合圖案與該第一基板之該第一金屬接合圖案的步驟包括溫度介於約100℃至約500℃之間的一回火製程。
  8. 如申請專利範圍第5項所述之半導體裝置的形成方法，其中該第二基板更包括一主動元件於該第二基板上，以及一內連 線層位於該第二基板與該主動元件上，且更包括蝕刻一開口穿過該第一基板至該第二基板的該內連線層中，以形成多個接觸墊。
  9. 一種半導體元件，包括：一第一基板，包括一溝槽式電容與一第一金屬接合圖案於該第一基板上；以及一第二基板，包括一CMOS元件與一第二金屬接合圖案於該第二基板上，該第二基板之該第二金屬接合圖案對應該第一基板之該第一金屬接合圖案，該第一金屬接合圖案與該第二金屬接合圖案合併形成一導電金屬界面與一封環，且該第二基板經由該導電金屬界面接合至該第一基板，其中該封環包圍該導電金屬界面。
TW102145313A 2012-12-28 2013-12-10 半導體裝置與其形成方法及半導體元件 TWI532144B (zh)

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