CN105190889B - 用以控制接通电流的垂直nand串的硅化钨栅源和单元柱制造 - Google Patents

用以控制接通电流的垂直nand串的硅化钨栅源和单元柱制造 Download PDF

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CN105190889B
CN105190889B CN201480011173.1A CN201480011173A CN105190889B CN 105190889 B CN105190889 B CN 105190889B CN 201480011173 A CN201480011173 A CN 201480011173A CN 105190889 B CN105190889 B CN 105190889B
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memory cell
channel
memory device
tungsten silicide
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CN105190889A (zh
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F.A.辛塞克-埃格
K.K.帕拉特
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Intel Corp
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Abstract

公开了一种非易失性存储器器件和一种用于形成非易失性存储器器件的方法。在存储器器件的制造期间，硅化钨被用作取代常规使用的氧化铝的蚀刻停止层以形成具有高纵横比的沟道柱。硅化钨的使用对于消除在常规地使用Al氧化物蚀刻停止层时形成的所不期望的蚀刻停止凹陷和所不期望的浮动栅而言是有用的。

Description

用以控制接通电流的垂直NAND串的硅化钨栅源和单元柱制造
技术领域
本文所描述的技术的实施例涉及半导体制造，并且更具体地涉及制造垂直NAND串。
背景技术
常规的垂直NAND串使用氧化铝（Al氧化物）蚀刻停止层以用于停止高纵横比柱（沟槽）蚀刻。由于Al氧化物蚀刻停止层不具有足够的蚀刻选择性，因此需要相对较厚的Al氧化物层以便能够控制蚀刻的停止。相对较厚的Al氧化物层导致选择栅（SG）和NAND串的第一字线（WL）之间的不合期望的较长沟道距离，从而未充分使用NAND串沟道的完整长度。此外，用于Al氧化物快速蚀刻以清洗干法蚀刻聚合物的典型的湿法蚀刻清洗化学品（诸如氢氟酸（HF）、缓冲氧化物蚀刻（BOE）化学和磷酸）容易蚀刻Al氧化物并且导致形成不合期望的浮动栅（FG）的Al氧化物层处的沟道侧壁中的凹陷，并且造成针对NAND串的接通电流退化。
附图说明
通过示例的方式而不是通过限制的方式在附图的各图中图示本文所公开的实施例，在附图中相同的参考标号是指类似的元件并且在附图中：
图1描绘了在NAND串的制造期间常规形成的垂直NAND串的示例性实施例的侧截面视图；
图2描绘了根据本文所公开的主题的、在制造期间的垂直NAND串的第一示例性实施例的侧截面视图；
图3描绘了根据本文所公开的主题的、在制造期间的垂直NAND串的第一示例性实施例的侧截面视图；
图4描绘了根据本文所公开的主题的、用于形成图2的垂直NAND串的示例性实施例的示例性过程的流程图；以及
图5A-5I描绘了根据本文所公开的主题的图4的示例性过程的各种阶段。
将领会到，为了说明的简化和/或清楚，图中描绘的元件不一定按照比例绘制。例如，为了清楚起见，一些元件的尺寸可能相对于其它元件有所夸大。图的尺度不表示本文所描绘的各种元件的精确尺寸和/或尺寸比例。另外，如果认为恰当的话，在各图之间重复参考标号以指示对应和/或类似的元件。
具体实施方式
本文所描述的技术的实施例涉及半导体制造，并且更具体地涉及制造垂直NAND串。在以下描述中，阐述大量特定细节以提供对本文所公开的实施例的透彻理解。然而，本领域技术人员将认识到，本文所公开的实施例可以在没有所述特定细节中的一个或多个的情况下，或者利用其它方法、组件、材料等来实现。在其它实例中，未示出或详细描述公知的结构、材料或操作以避免使说明书的各方面晦涩难懂。
遍及本说明书对“一个实施例”或“实施例”的提及意指结合所述实施例描述的具体特征、结构或特性被包括在至少一个实施例中。因此，在遍及本说明书的各种地方中的短语“在一个实施例中”或“在实施例中”的出现不一定都是指相同的实施例。另外，具体特征、结构或特性可以以任何合适的方式组合在一个或多个实施例中。此外，词语“示例性”在本文中用于意指“充当示例、实例或说明”。本文中描述为“示例性”的任何实施例不被解释为必然比其它实施例优选或有利。
可以顺序地并且以最有助于理解所要求保护的主题的方式将各种操作描述为多个分立的操作。然而，描述的次序不应当被解释为暗示这些操作必然是与次序相关的。具体地，这些操作不需要以呈现的次序执行。所描述的操作可以以与所描述的实施例不同的次序执行。可以执行各种附加操作和/或在附加的实施例中可以省略所描述的操作。
图1描绘了在NAND串的制造期间常规形成的垂直NAND串100的示例性实施例的侧截面视图。在图1中描绘的具体制造点处，垂直NAND串100包括源101、第一氧化物层102、由p型多晶硅材料形成的选择栅源（SGS）层103、氧化铝（Al氧化物）蚀刻停止层104、第二氧化物层105、第一n型多晶硅层106、第三氧化物层107、第二n型多晶硅层108、第四氧化物层109、第三n型多晶硅层110、第五氧化物层111、第四n型多晶硅层112、第六氧化物层113、第五n型多晶硅层114、第七氧化物层115和化学机械平面化（CMP）层116，诸如氮化硅层。垂直NAND串100还包括多个单独的闪存单元117（在图1中仅指示其中的几个闪存单元117）和多晶硅沟道118。
NAND串100的多晶硅层106将成为字线WL0。类似地，多晶硅层108,110,112和114将分别成为字线WL1-WL4。应当理解的是，为了图1的清楚性，并未指示构成垂直NAND串100的所有结构。还应当理解的是，多晶硅层106,108,110,112和114可以可替换地由p型多晶硅材料形成。此外，应当理解的是，所描绘的垂直NAND串100的各种层和结构以公知的方式形成。
当在垂直NAND串100的制造期间常规地使用电介质蚀刻停止层104时，在选择栅源（SGS）103与第一字线（WL0）106之间产生不合期望的大距离X。例如，如果距离X小于50nm对于选择栅SG 103与WL0 106之间的距离而言是所期望的，则使用Al氧化物蚀刻停止层104的常规技术可能是不可接受的，因为其造成大于所期望的50nm的SG到WL0距离X，因为用于柱蚀刻的过程控制需要大于45nm的Al氧化物厚度。此外，过程控制要求20nm正硅酸四乙酯（TEOS）氧化物，其通过化学气相沉积（CVD）沉积。针对Al氧化物层104的湿法蚀刻速率对于SG 103与WL0 106之间的所期望的距离而言过快。而且，由于柱蚀刻过程具有高聚合速率以便实现用于沟道118的高纵横比蚀刻，因此用于后续湿法清洗的选项是有限的。此外，在柱湿法蚀刻清洗期间不可避免地形成大约7nm的沟道侧壁的Al氧化物中的凹陷。该凹陷在Al氧化物蚀刻停止层104中形成不合期望的浮动栅（FG）119，其不利地影响器件100的“接通”电流。也就是说，接通电流沿沟道的侧壁而行，并且Al氧化物凹陷——或者浮动栅在Al氧化物区中的存在——改变电流路径。这和/或距离X的增加使得更难以接通和控制垂直NAND串。
图2描绘了根据本文所公开的主题的、在制造期间的垂直NAND串200的第一示例性实施例的侧截面视图。在一个示例性实施例中，垂直NAND串200可以形成用于例如固态存储器或固态驱动器（SSD）的NAND串阵列的一部分。在图2中描绘的具体制造点处，垂直NAND串200包括源201、掺杂的多晶硅缓冲层202、第一氧化物层203、由p型多晶硅材料形成的选择栅源（SGS）层204、硅化钨（WSiX）层205、第二氧化物层206、第一n型多晶硅层207、第三氧化物层208、第二n型多晶硅层209、第四氧化物层210、第三n型多晶硅层211、第五氧化物层212、第四n型多晶硅层213、第六氧化物层214、第五n型多晶硅层215、第七氧化物层216和化学机械平面化（CMP）层217，诸如但不限于氮化硅层。垂直NAND串200还包括多个单独的闪存单元218（在图2中仅指示其中的几个闪存单元）和多晶硅沟道219。与源201相对的多晶硅沟道219的一端将最终耦合到位线（BL）（未示出）。
在图2中描绘的示例性实施例中，多晶硅207将成为字线WL0。类似地，多晶硅层209,211,213和215将分别成为字线WL1-WL4。应当理解的是，为了图2的清楚性，并未指示构成垂直NAND串200的所有结构。还应当理解的是，多晶硅层207,209,211,213和215可以由p型多晶硅材料形成。另外，应当理解的是，所描绘的垂直NAND串200的各种层和结构以公知方式形成。此外，本文所公开的主题不限于浮动栅（FG）垂直NAND器件，而是还适用于其它垂直晶体管架构，诸如电荷捕获型闪存（CTF）NAND器件，并且可以增强堆叠式柱垂直NAND缩放方法方面的性能，诸如但不限于固态存储器或固态驱动器（SSD）。
在图2中描绘的示例性实施例中，WSiX层205可以被形成为大约20nm厚，并且可以用作蚀刻停止层以形成具有大约30:1的纵横比的柱（即沟道）。因此，WSiX层205成为选择栅（SGS）204的一部分，并且SGS到WL0的距离Y1减小到大约30nm，其还减小器件200的接通电流。更进一步地，在常规地使用Al氧化物蚀刻停止层时（即图1）形成的所不期望的蚀刻停止凹陷和所不期望的浮动栅被实质上消除，因为WSiX层205与用于形成闪存单元218的IPD侧壁移除技术兼容。
图3描绘了根据本文所公开的主题的、在制造期间的垂直NAND串300的第一示例性实施例的侧截面视图。在一个示例性实施例中，垂直NAND串300可以形成用于例如固态存储器或固态驱动器（SSD）的NAND串阵列的一部分。在图3中描绘的制造点处，垂直NAND串300包括源301、n+型多晶硅缓冲层302、第一氧化物层303、由p型多晶硅材料形成的第一选择栅源（SGS）层304、硅化钨（WSiX）层305、由p型多晶硅材料形成的第二选择栅（SGS）层306、第二氧化物层307、第一n型多晶硅层308、第三氧化物层309、第二n型多晶硅层310、第四氧化物层311、第三n型多晶硅层312、第五氧化物层313、第四n型多晶硅层314、第六氧化物层315、第五n型多晶硅层316、第七氧化物层317和化学机械平面化（CMP）层318，诸如但不限于氮化硅层。垂直NAND串300还包括多个单独的闪存单元319（在图3中仅指示其中的几个闪存单元319）和多晶硅沟道320。与源301相对的多晶硅沟道320的一端将最终耦合到位线（BL）（未示出）。
在图3中描绘的示例性实施例中，多晶硅308将成为字线WL0。类似地，多晶硅层310,312,314和316将分别成为字线WL1-WL4。应当理解的是，为了图3的清楚性，并未指示构成垂直NAND串300的所有结构。还应当理解的是，多晶硅层308,310,312,314和316可以由p型多晶硅材料形成。另外，应当理解的是，所描绘的垂直NAND串300的各种层和结构以公知方式形成。此外，本文所公开的主题不限于浮动栅（FG）垂直NAND器件，而是还适用于其它垂直晶体管架构，诸如电荷捕获型闪存（CTF）NAND器件，并且可以增强堆叠式柱垂直NAND缩放方法方面的性能，诸如但不限于固态存储器或固态驱动器（SSD）。
在图3中描绘的示例性实施例中，WSiX层305形成在第一SGS层304与第二SGS层306之间，并且提供由图2中描绘的示例性实施例200提供的所有益处。也就是说，WSiX层305可以被形成为大约20nm厚，并且用作用于形成具有大约30:1的纵横比的柱（即沟道）的蚀刻停止层。因此，WSiX层305成为SGS 304和306的一部分，并且SGS到WL0的距离Y2减小到大约30nm。更进一步地，在常规地使用Al氧化物蚀刻停止层时（图1）形成的所不期望的蚀刻停止凹陷和所不期望的浮动栅被实质上消除，因为WSiX层305与用于形成闪存单元319的IPD侧壁移除技术兼容。此外，由于用于该示例性实施例的WSiX层305形成在两个多晶硅层之间，所以SG层304和306与WSiX层305的表面之间的界面粘附强于示例性实施例200（图2）的WSiX层205与第二氧化物层206之间的界面粘附。
图4描绘了根据本文所公开的主题的、用于形成垂直NAND串200（图2）的示例性过程400的流程图。图5A-5I描绘了示例性过程400的各种阶段。
图4中的块401表示到过程400中的示例性进入点。图5A描绘了用于制造图2中描绘的示例性垂直NAND串的实施例500的一个示例性进入点。如图5A中所示，已经使用公知的方式沉积了各种层。具体地，器件500包括由掺杂的多晶硅材料层或由WSiX材料层形成的源层501。如果源材料501由WSiX形成，则n+型缓冲多晶硅材料层502形成在源层501上。如果源材料501由掺杂的多晶硅形成，则不需要缓冲层502。第一氧化物层503形成在缓冲多晶硅层502上。用于氧化物层503的合适的材料包括但不限于，TEOS氧化物，以及高纵横比工艺（HARP）氧化物膜，诸如臭氧/正硅酸四乙酯（O3/TEOS）。选择源栅（SGS）层504形成在第一氧化物层503上。WSiX-SGS层505形成在SGS层504上。（在该点处，如果期望图3中描绘的示例性垂直NAND串的实施例，则第二SGS层将形成在WSiX-SGS层505上）。
返回到图4的过程的示例性进入点（块401）和图5A的器件500，第二氧化物层506形成在WSiX层505上，并且第一n型多晶硅层507形成在氧化物层506上。取决于垂直NAND串将包括的闪存单元的数目而形成氧化物和n型多晶硅的交替层。图5A-5I中描绘的示例性垂直NAND串将具有五个闪存单元，因此氧化物层508,510,512和514以及n型多晶硅层509,511,513和515交替形成在氧化物层506上。应当理解的是，根据本文所公开的主题的垂直NAND串的实施例可以具有比五个闪存单元更多或更少的闪存单元。氧化物层516形成在n型多晶硅层515上。氮化物盖层517形成在氧化物层516上。氧化物盖层518形成在氮化物盖层517上。诸如碳之类的硬掩模层519形成在氧化物盖层518上，并且抗蚀剂层520形成在硬掩模层519上。在可替换的实施例中，盖层518可以由氮化物材料、多晶硅材料或Hi-K电介质材料形成。
在图5B中，以公知的方式执行柱蚀刻（图4中的块402），其停止在WSiX层505中以形成将最终成为器件500的沟道的高纵横比沟槽521。图5B还示出被移除的抗蚀剂层520和硬掩模层519。尽管器件500将仅具有五个闪存单元堆层，但是应当理解的是，本文所公开的主题不因此受限，并且可以具有多得多的（近似40个）闪存单元堆层。
在图5C中，在沟槽521中执行四甲基氢氧化铵（TMAH）蚀刻（块403）以在522处回蚀（etch back）n型多晶硅层507,509,511,513和515，为了图5C的清楚性，仅指示其中的几个位置。WSiX层505不受TMAH蚀刻影响，从而避免当常规使用Al氧化物蚀刻停止层以便形成垂直NAND串时形成的所不期望的蚀刻停止凹陷和浮动栅。在图5D中，以公知的方式在沟槽521和回蚀位置522中形成多晶硅层间电介质（IPD）材料523（块404）。形成浮动栅（FG）多晶硅材料524（块405）以填充回蚀位置523。
在图5E中，执行公知的干法蚀刻技术（块406）以蚀刻沟槽521的底部521a，穿过IPD材料523、多晶硅材料524和WSiX层505，在氧化物层503中停止，刚好在缓冲多晶硅层502上方。在图5F中，执行公知的湿法蚀刻技术（块407），其从沟槽521移除任何剩余的FG多晶硅材料523以防止任何WL到WL短路。此外，使用公知的氮化硅蚀刻剂移除IPD材料523。WSiX层505保持完整，而在常规过程中，Al氧化物不保持完整并且将形成所不期望的蚀刻停止凹陷和所不期望的浮动栅。
在图5G中，以公知的方式在沟槽521中形成隧穿氧化物层525（块408）。用于隧穿氧化物层525的合适材料包括但不限于通过公知的快速热CVD（RTCVD）工艺沉积的高温氧化物（HTO）。然后在隧穿氧化物层525上形成多晶硅衬里526（块409）以保护隧穿氧化物层免受从沟槽521的底部清除氧化物层502和多晶硅衬里526的后续蚀刻。在图5H中，后续干法蚀刻移除多晶硅衬里526（块410）并且从沟槽的底部521b清除氧化物层502和多晶硅衬里526，同时还从器件500的顶部移除CAP层518。此外，为了得到更好的沟道连续性，执行另一蚀刻（后冲压清洗）清洗以移除沟道与源层501之间的任何剩余SGS氧化物，使得沟道与源层501进行电气接触。
在图5I中，以公知的方式利用多晶硅527填充沟槽521（块411）以形成沟道，并且公知的多晶硅CMP技术用于从沟道移除过量的多晶硅。
可以按照以上的详细描述做出这些修改。在随附权利要求中使用的术语不应当被解释为将范围限制到说明书和权利要求中公开的特定实施例。而是，本文所公开的实施例的范围将由随附权利要求确定，其要依照权利要求解释的所建立的原则来加以解释。

Claims (24)

1.一种存储器器件，包括：
包括第一端和第二端的沟道，所述沟道的第一端耦合到源，并且所述沟道的第二端耦合到位线；以及
形成在所述沟道的第一端处以选择性地控制所述位线与所述沟道之间的传导的选择栅，所述选择栅包括用作蚀刻停止层的硅化钨层，
沿所述选择栅与所述沟道的第二端之间的沟道的长度形成的至少一个非易失性存储器单元；
耦合到所述至少一个非易失性存储器单元的至少一个字线。
2.根据权利要求1 的存储器器件，其中所述至少一个非易失性存储器单元包括浮动栅（FG）存储器单元或电荷捕获型闪存（CTF）存储器单元。
3.根据权利要求1 的存储器器件，其中所述存储器器件包括固态驱动器（SSD）的部分。
4.根据权利要求1 的存储器器件，其中所述存储器器件包括存储器器件的阵列的部分。
5.根据权利要求1 的存储器器件，其中所述选择栅包括形成在两个多晶硅层之间的硅化钨层。
6.根据权利要求5 的存储器器件，还包括：
沿所述选择栅与所述沟道的第二端之间的沟道的长度形成的至少一个非易失性存储器单元。
7.根据权利要求6 的存储器器件，其中所述至少一个非易失性存储器单元包括浮动栅（FG）存储器单元或电荷捕获型闪存（CTF）存储器单元。
8.根据权利要求6 的存储器器件，其中所述存储器器件包括固态驱动器（SSD）的部分。
9.根据权利要求6 的存储器器件，其中所述存储器器件包括存储器器件的阵列的部分。
10.一种存储器器件，包括：
包括第一端和第二端的沟道，所述沟道的第一端耦合到源，并且所述沟道的第二端耦合到位线；
形成在所述沟道的第一端处以选择性地控制所述位线与所述沟道之间的传导的选择栅，所述选择栅包括用作蚀刻停止层的硅化钨层；并且所述选择栅与多晶硅层相邻，
沿所述选择栅与所述沟道的第二端之间的沟道的长度形成的至少一个非易失性存储器单元，
耦合到所述至少一个非易失性存储器单元的至少一个字线。
11.根据权利要求10 的存储器器件，其中所述至少一个非易失性存储器单元包括浮动栅（FG）存储器单元或电荷捕获型闪存（CTF）存储器单元。
12.根据权利要求10 的存储器器件，其中所述存储器器件包括固态驱动器（SSD）的部分。
13.根据权利要求10 的存储器器件，其中所述存储器器件包括存储器器件的阵列的部分。
14.根据权利要求10 的存储器器件，其中所述选择栅包括形成在两个多晶硅层之间的硅化钨层。
15.一种形成垂直NAND 串的方法，包括：
形成用于垂直NAND 串的源层；
在所述源层上形成选择栅层；
在所述选择栅层上形成硅化钨层；
在所述硅化钨层上形成多个交替的氧化物层和多晶硅层，氧化物层形成在所述硅化钨层上；
以及
使用所述硅化钨层作为蚀刻停止来穿过氧化物层和多晶硅层的所述多个交替层蚀刻高纵横比沟槽以最终形成沟道，
沿所述选择栅与所述沟道的第二端之间的沟道的长度形成的至少一个非易失性存储器单元；
耦合到所述至少一个非易失性存储器单元的至少一个字线。
16.根据权利要求15 的方法，其中所述源层由掺杂的多晶硅材料形成。
17.根据权利要求15 的方法，其中所述源层由硅化钨形成，以及
其中所述方法还包括在所述硅化钨源层上形成缓冲层，以及
其中在所述源层上形成所述选择栅层包括在所述缓冲层上形成所述选择栅层。
18.根据权利要求15 的方法，还包括沿所述高纵横比沟槽在氧化物层和多晶硅层的至少一个交替层中形成非易失性存储器单元。
19.根据权利要求18 的方法，其中所述至少一个非易失性存储器单元包括浮动栅（FG）存储器单元或电荷捕获型闪存（CTF）存储器单元。
20.根据权利要求18 的方法，其中所述垂直NAND 串包括固态驱动器（SSD）的部分。
21.根据权利要求18 的方法，其中所述垂直NAND 串包括存储器器件的阵列的部分。
22.根据权利要求18 的方法，其中在所述选择栅层上形成所述硅化钨层还包括在所述硅化钨层上形成多晶硅层，以及
其中形成所述多个交替的氧化物层和多晶硅层还包括在形成在所述硅化钨层上的所述多晶硅层上形成所述多个交替的氧化物层和多晶硅层，氧化物层形成在所述多晶硅层上，所述多晶硅层形成在所述硅化钨层上。
23.根据权利要求22 的方法，其中所述至少一个非易失性存储器单元包括浮动栅（FG）存储器单元或电荷捕获型闪存（CTF）存储器单元。
24.根据权利要求22 的方法，其中所述垂直NAND 串包括固态驱动器（SSD）的部分。
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