CN105144371A - 用于功率半导体装置的模块布置 - Google Patents

用于功率半导体装置的模块布置 Download PDF

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Publication number
CN105144371A
CN105144371A CN201480024240.3A CN201480024240A CN105144371A CN 105144371 A CN105144371 A CN 105144371A CN 201480024240 A CN201480024240 A CN 201480024240A CN 105144371 A CN105144371 A CN 105144371A
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Prior art keywords
module
arrangement
power semiconductor
housing
substrate
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CN201480024240.3A
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M.拉希莫
H.杜兰
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ABB Technology AG
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ABB T&D Technology AG
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Publication of CN105144371A publication Critical patent/CN105144371A/zh
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Abstract

本发明涉及一种用于功率半导体装置的模块布置，包括一个或多个功率半导体模块(38)，其中一个或多个功率半导体模块(38)包括具有第一表面(42)以及布置成与第一表面(42)相对的第二表面(44)的衬底(40)，其中该衬底(40)至少部分电绝缘，其中传导结构布置在衬底(40)的第一表面(42)，其中至少一个功率半导体装置布置在所述传导结构上并且与其电连接，其中一个或多个模块(38)包括用于接收至少一个功率半导体装置的内体积(56)，该体积通过模块壳体(58)从其周围环境密封，其中模块布置(36)包括至少部分限定用于接收一个或多个模块(38)的体积(62)的布置壳体(60)，并且其中布置壳体(60)覆盖所述体积(62)。这种布置考虑到改进的安全性以及改进的可靠性。

Description

用于功率半导体装置的模块布置
技术领域
本发明涉及包括具有功率半导体装置的至少一个模块的模块布置。具体来说，本发明涉及具有为半导体装置提供非常安全和可靠保护的能力的用于功率半导体装置的模块布置。
背景技术
多种功率半导体模块是已知的，并且用于许多不同电子装置中。这些功率电子模块的要求是要提供可接受的可靠性以及安全性。
关于安全性和可靠性，功率电子模块以及由其所组成的功率半导体装置已知对环境影响是敏感的。特别地是，湿气和水分在考虑不利地影响和潜在地损坏功率半导体装置或相应地功率半导体模块时具有相关性。为了防止水分和其他污染物渗入模块中并且到达功率半导体装置，例如，已知的是将硅凝胶应用到衬底和功率半导体装置。
例如，从DE102010041714A1已知的是一种功率半导体模块及其生产方法。这种功率半导体模块包括互连装置和基板。基板包括密封并且布置用于接收冷却流体的体积（volume）。此外，提供一种外壳，该外壳密闭地连接到基板。
此外，从EP1686621A1已知的是一种表面可安装的密封封装。这种封装包括密封在其外壳部分中的半导体装置。
但是，半导体装置的保护并且因此布置在模块或相应地模块布置中的功率半导体装置以及用其装备的电气装置的可靠性仍然具有改进的潜力。
US6650559B1在图3和图7中公开具有两个功率半导体模块的用于功率半导体装置的模块布置，由此模块包括用于接收功率半导体装置的内体积，该体积由模块壳体（enclosure）来包围。
此外，US2009/0021916A1也在图3和图4中示出用于功率半导体装置的这种模块布置，由此模块包括用于接收至少一个功率半导体装置的内体积，该体积由模块壳体来包围。
EP2437295A1在图1和图2中公开一种用于功率半导体装置的众所周知的模块布置。
此外，EP1544915A1公开一种电路模块散热器安装布置，由此图25是以截面来示出电路模块的封装构造的示意配置的视图。这个电路模块具有一种夹具（fixture），包含盒装配部分（casefittingportion）或螺旋装配部分，其用于固定树脂或金属盒，以在其中收容通过使用电路模块所构成的电气设备。
US2012/0098119A1在图4和图5中再次示出用于功率半导体装置的模块布置，由此模块包括用于接收至少一个功率半导体装置的内体积，该体积由模块壳体来包围。
发明内容
因此，本发明的一个目的是提供一种改进模块布置，其允许对半导体装置的特别安全保护并且因此允许显著改进的可靠性。
这个目的通过如权利要求1所述的用于功率半导体装置的模块布置来实现。在从属权利要求中限定本发明的优选实施例。
本发明涉及一种用于功率半导体装置的模块布置，其包括一个或多个功率半导体模块，其中一个或多个半导体功率模块包括具有第一表面以及布置成与第一表面相对的第二表面的衬底，其中该衬底至少部分电绝缘，其中传导结构布置在衬底的第一表面处，其中至少一个功率半导体装置布置在所述传导结构上并且与其电连接，其中一个或多个模块包括用于接收至少一个功率半导体装置的内体积，该体积通过模块壳体从其周围环境密封，其中该模块布置包括至少部分限定用于接收一个或多个模块的体积的布置壳体，并且其中该壳体覆盖所述体积。
按照本发明，可提供一种模块布置，其在保持其部分放电性能(这对高电压应用或相应地高功率应用是特别有利的)的同时，允许半导体装置或相应地芯片的改进保护而免受环境影响(例如湿气和水分)。这类功率应用示范和非限制性地一般可以是处理大于75A的电流和/或大于1000V的电压的那些应用。
详细来说，用于功率半导体装置的模块布置包括一个或多个功率半导体模块。因此，按照本发明，可提供功率模块布置仅包括一个功率半导体模块，或者它可包括一个以上功率半导体模块。在非限制性示例中，两个或以上、例如2至6个功率半导体模块可在功率半导体模块布置中提供。此外，可为一个或者所限定数量的现有功率半导体模块提供描述的以下特征，其中不具有描述的性质或者以不同方式所布置的其他半导体模块可存在，并且由功率半导体布置所组成，而没有离开本发明的范围。
关于一个或多个功率半导体模块，这些可包括具有第一表面以及布置成与第一表面相对的第二表面的衬底。衬底至少部分电绝缘，这具体表示这个衬底的区或相应地区域可以电绝缘，而其他区或相应地区域可以不电绝缘，而是导电的。备选地，衬底例如可在由电绝缘材料来形成的情况下完全电绝缘。
一般来说，本领域的技术人员知道为此所提供的功率半导体模块和衬底的要求，由于这个要求，本领域的技术人员知道哪一种材料适合作为导电材料和相应地电绝缘材料。作为示例并且以非限制性方式，绝缘材料可包括其中包含电阻率为1010ohm.m的氮化铝(AlN)的材料，而导电材料以示范的和非限制性方式可包括诸如电阻率为0.1695×10-7ohm.m的铜的材料。
此外，导电衬底、例如具体是导电通路(例如具体是金属化)布置在衬底的第一表面。这可示范地表示传导结构在衬底的表面上形成。例如在衬底完全电绝缘并且传导结构因此可通过将它例如作为所构成的金属化（metallization）沉积在衬底的电绝缘材料的表面来形成的情况下，这个布置可以是有利的。备选地，衬底同样可部分电绝缘并且部分导电来形成。因此，导电区或相应地位置同样可形成衬底的第一表面或者其至少一部分并且具体是导电结构。
传导结构可基本上提供在衬底的第一表面处，以便接收一个或多个功率半导体装置，如在下面将描述。
详细来说，如同从已知的功率半导体模块基本上已知的，至少一个功率半导体装置布置在上述传导结构上并且与其电连接。半导体装置一般可如本领域对功率半导体模块或相应地功率半导体布置已知的那样来提供。例如，一个或多个功率半导体装置可以是绝缘栅双极晶体管(IGBT)、反向导电绝缘栅双极晶体管(反向导通IGBT)、双模绝缘栅晶体管(BIGT)和/或二极管、例如肖特基二极管。此外并且为了使功率半导体模块以及因此功率半导体布置适当地工作，一个以上的不同或相同半导体装置可存在。作为非限制性示例，IGBT和二极管可存在于一个模块中。功率半导体装置还可借助于具有适当电导率的粘合剂来连接到衬底。例如，半导体装置可借助于焊料来固定到衬底或相应地其传导结构。具体来说，诸如IGBT的集电极的半导体装置的第一主接触件例如可固定到衬底，而诸如IGBT的发射极的半导体装置的第二主接触件可例如借助于接合线来连接到衬底的其他位置并且具体是连接到导电结构的其他部分或者其他导电通路。
此外，按照本发明，一个或多个模块包括用于接收至少一个功率半导体装置的内体积，该体积通过模块壳体从其周围环境密封。按照这个方面，模块的内部、例如具体是功率半导体装置和衬底相应的第一表面或者整个衬底被密封，并且因此与模块的周围环境有效地分开。
因此，密封可具体表示密封或相应地封装，其不允许液体或气体物质特别是在标准工作条件(例如呈现在标准性能下的环境压力和温度)下被引入或者离开相应的密封体积。
此外，模块布置包括布置壳体，其至少部分限定用于接收一个或多个模块的体积，并且壳体覆盖所述体积。换言之，密封模块内部的一个或多个模块壳体因而从体积来接收，该体积是模块布置的一部分，并且又由布置壳体来覆盖，以及因此与布置的周围环境分开。这个布置提供功率半导体模块以及功率半导体布置的显著改进安全性和可靠性行为。
详细来说，已经通过提供一个或多个功率半导体模块的密封，因而可显著地保护模块以及在其中布置的功率半导体装置免受由要插入的不希望的成分来不利地影响它们。例如，可显著阻止湿气或相应地水分渗入模块。这允许保护功率半导体模块和相应地功率半导体装置免受腐蚀性环境，这又很大程度上增强后者的长期稳定性并且因此增强其可靠性以及用其装备的电气装置的可靠性。
此外，通过为模块布置提供作为构筑块的模块的附加保护，通过提供至少部分限定用于接收一个或多个模块的体积的布置壳体(并且壳体覆盖所述体积)，另外可以增强安全性以及可靠性。这归因于第一保护通过布置壳体来提供的事实。甚至在这个壳体不密封后者的内体积的情况下，也可已经给予第一保护度。因此，对模块壳体起作用的不利影响可显著地降低到最小。此外，模块因而提供另一种极好的保护，使得半导体装置被损坏的危险进一步显著降低。换言之，模块壳体可充当内壳体，并且布置壳体可充当外壳体，这可加倍保护。
因此可限制布置壳体的要求。布置壳体或相应地外壳体可简单地由塑料来形成，使得形成这个壳体特别简易并且成本节约，因此无论如何都提供极好的安全性。
此外，甚至在模块被损坏的情况下，对其他所提供模块的影响可由于其他所提供模块通过密封壳体来安全地保护的事实而显著降低。
除了那个之外，可实现模块的高电流能力、良好热导率和良好隔离能力。这允许模块或模块布置的性能不受到不利影响。因此，性能对于所需和已知应用是完全可用的。示范和非限制性应用包括牵引应用、工业驱动以及传输和分配。
生产过程由于模块受到完全保护并且能够对其完全性能进行电测试的事实而进行简化。这也简化完全模块布置的设计和组装。对于等于或小于3.3kV的范围中的应用，情况特别是真实的。
因此，按照本发明的模块布置提供特别改进的可靠性，从而允许因而布置的以及用其装备的电气装置的改进长期稳定性。除了那个之外，性能不受到不利影响。
按照一个实施例，一个或多个模块的每个内体积通过模块壳体从其周围环境密封。按照这个实施例，不仅密封单个所限定功率模块，而且同样保护现有全部模块。因此，这个实施例由于如下事实而允许特别高的保护度：保护全部模块免受不希望的影响，并且基于不同模块进一步保护全部模块。因此，按照这个实施例的可靠性特别高。
按照另一个实施例，至少一个模块的衬底包括电绝缘区和导电区，电绝缘区和导电区布置用于通过衬底或相应地通过其导电区外部地接触由模块所包含的至少一个半导体装置。例如，按照这个实施例，衬底可基于包括铜接合氮化硅封装技术的布置。这个实施例允许提供到模块外部的电接触件，而无需提供模块壳体中的孔。因此，密封甚至对于特别长的时间尺度也可耐受特别恶劣的条件。因此，按照这个实施例的可靠性特别高。此外，壳体可以特别简易并且还特别节省时间来形成。电导率以及电阻率的量因此可适合特殊用途。实际上，必须选择材料，使得电流可以允许模块正确工作的适当来方式来引导，而绝缘结构应当避免在模块的工作条件下携带任何电流。实际上，绝缘结构例如可以是陶瓷材料，和/或传导结构可以是金属。
按照这个实施例，特别优选的是，导电区借助于通孔将至少一个功率半导体装置连接到位于模块壳体外部的连接区。由于接触件可以经由衬底来单独地提供的事实，这种实施例提供模块内部的有源装置、即功率半导体装置的特别优选、明确限定和可适配外部接触件。因此，模块壳体的损坏或泄漏可进一步降低，按照其，按照这个实施例的模块的可靠性以及耐用性得到特别改进。
按照另一个实施例，用于接触一个或多个模块的内部的电导体借助于密封被引导经过模块壳体。这允许使用常规衬底，从而使这个衬底的使用特别简易和成本节约。关于密封，可提供两个示范实施例，即使这个实施例并不局限于后续备选方案。作为第一示例，接触件可被引导经过壳体，并且可借助于玻璃密封来密封。按照第二示例，接触件可借助于陶瓷密封来密封。陶瓷密封的优点是提供与相邻材料、例如壳体和电导体的材料中的一个很匹配的系数的可能性。玻璃密封的优点具体可以是它的低成本。
按照另一个实施例，模块壳体和/或布置壳体包括从由AlSiC和金属所组成的组中选取的至少一种材料。
关于AlSiC，这种材料包括其中包含铝的基体，其中布置基体碳化硅微粒。关于这个方面，可实现相对标准材料的高达40%至70%的重量减少，从而引起特别对移动应用、例如火车中的应用的显著优点。此外，热膨胀系数(CTE)可与相邻组件的组件很匹配，这降低特别是由于温度变化引起的裂缝的危险，并且进一步改进功率布置或者用其装备的电子装置的可靠性。除了那个之外，这种材料的热导率比较高，使得所生成的热可易于耗散，使得热影响可进一步降低。这还改进可靠性。
所使用的特定AlSiC材料不受限制。例如，可使用下列材料。例如可使用AlSiC-9、AlSiC-10或AlSiC-12，其全部具有处于大约170至200W/mK的范围中的相应的热膨胀系数，这对功率半导体装置可以是特别有利的。
关于金属材料，可使用若干金属。例如，镍-钴铁合金可以是有利的，其下以其名称科瓦合金（Kovar）可购买的合金可以是特别优选的。关于这个方面，科瓦合金可具有大约54wt.%铁、29wt.%镍、17wt.%钴的典型组成。然而，该组成可偏离上述组成，因为少量碳、硅和锰可存在，后者以小于1wt.%、具体小于0.5wt.%的量存在。上述指定的合金还可具有接近相邻组件的这些的有利热膨胀系数的优点，从而引起特别高的可靠性。
按照另一个实施例，一个或多个模块的内体积填充有从由硅胶和惰性气体所组成的组中选取的填加物。
硅胶的优点因此可在电气和机械性质(即，其柔软度、可塑性和粘着性连同极好的隔离能力)的唯一组合中看到。
惰性气体的优点可具体来说例如由于惰性气体的易于操控和处理而在于用于产生模块以及整个布置的简易方法。此外，特别是通过将惰性气体用于填充功率半导体模块的内部，工作温度不受限制，但是可在没有关于半导体组件的相应的应用和能力的任何限制的情况下选择，而不管封装。没有预计对温度稳定的惰性气体的不利影响。此外，考虑到发生不希望的物质被引入模块中，比较不重要的是为模块提供少许过压。此外，通过使用惰性气体作为模块的内部的填充材料，不存在不希望的成分从模块流出并且使后者周围的其他成分降级的危险。相应惰性气体的示例在非限制性列表中包括氩和氮。总之，上述实施例特别是对于改进按照本发明的布置以及用其装备的电气装置的安全性和可靠性具有极大贡献。
此外，通过使用适当惰性气体或硅胶，也能够使部分放电能力为最小，从而进一步改进可靠性。
按照另一个实施例，单个衬底布置用于收容两个或更多模块，两个或更多模块各自布置在布置壳体所限定的体积内部。这个实施例的优点包括改进的可缩放性以及模块性。
按照另一个实施例，布置壳体密封从其所限定的体积。例如，布置壳体可连接到布置在衬底的第二表面的基板。按照这个实施例，可靠性因如下事实而特别高：布置的外壳体或相应地壳体提供密封。因此，诸如特别是湿气或相应地水分之类的不希望的物质将不会引入功率模块布置的体积中，并且因而将不会接触到模块。因此，可靠性由于功率半导体装置关于外部环境的双重密封而将会特别高。
按照另一个实施例，至少部分由布置壳体所限定的体积填充有从由硅胶和惰性气体所组成的组中选取的填加物。按照这个实施例，可提供显式气体以及以上关于模块的填充所述的优点。此外，由布置壳体所限定的这个体积的填充与模块内部的体积相比可以是相同或不同的。这个实施例可允许相应性质对预期应用的改进适配。
关于所述功率模块布置的其他技术特征和优点，参阅电气装置以及附图的描述。
本发明还涉及一种电气装置，其包括按照如前述权利要求中的任一项所述的模块布置。这种电气装置具有显著改进的工作行为并且还具有显著改进的可靠性的特定优点。
这类电子装置的非限制性示例包括用于具有高可靠性的工业驱动和牵引、恶劣条件的高可靠应用例如海底、太空、军事应用和汽车工业的装置。
附图说明
在从属权利要求、附图以及以下对附图和示例的描述中公开本发明的主题的附加特征、特性和优点，以示范方式示出按照本发明的半导体模块布置的实施例和示例。
附图包括：
图1示出按照现有技术的模块的实施例的截面侧视图；
图2示出按照本发明的实施例的模块布置的实施例的截面侧视图；
图3示出用于按照本发明的模块布置的模块的实施例；以及
图4示出用于按照本发明的模块布置的模块的另一个实施例。
具体实施方式
图1中，示意示出按照现有技术的功率半导体模块10的布置。详细来说，描述所述功率模块10的内部结构。功率模块10包括外壳12，其中布置至少一个功率半导体装置14。半导体装置14以示范的方式可以是绝缘栅双极晶体管(IGBT)、二极管、金属氧化物半导体场效应晶体管(MOSFET)等。按照图1，提供二极管和IGBT。半导体装置14或者多个半导体装置14经由端子16并且经由栅连接件18是可连接的，其中半导体装置14优选地通过铝接合线20来接合。
作为绝缘体，环氧树脂层22可布置在半导体装置14上面。半导体装置14还可布置在衬底24上。半导体装置14、端子16以及栅连接件18经由金属化26、具体是铜金属化以及焊料28和相应地组块（lot）来连接到衬底24。然而，可应用同等的连接、例如超声焊接。另外，衬底24在其底侧连接到另一个金属化30、具体是铜金属化。外壳12内部的其余体积填充有绝缘凝胶32。
此外，功率模块10包括基板34。基板34在其上侧经由金属化30和焊料31与半导体装置14热接触。
在图2中，示出按照本发明的模块布置36。按照图2的布置36在非限制性示例中包括两个功率半导体模块38，其仅示意示出，并且将关于以下图3和图4更详细描述。功率半导体模块38位于具有第一表面42以及布置成与第一表面42相对的第二表面44的衬底40上，其中衬底40至少部分电绝缘。例如，衬底42可由陶瓷绝缘体、具体来说由氮化铝陶瓷绝缘体来形成。此外，传导结构布置在衬底40的第一表面42，其中至少一个半导体装置布置在所述传导结构上并且与其电连接。导电结构在图1中没有详细示出。
此外，模块38可通过端子46以及栅连接件48来连接，所述连接可经由导电材料、例如焊料50来连接到衬底40或者其传导结构，或者它们可例如焊接于此。
衬底40还将其第二表面44经由金属化53和焊料54连接到基板52。
按照本发明，至少一个、优选地全部模块38包括用于接收至少一个功率半导体装置的内体积56，该体积56通过模块壳体58从其周围环境密封。此外，模块布置36包括布置壳体60，其例如由塑料制成，至少部分限定用于接收一个或多个模块38的体积62，并且其中布置壳体60覆盖所述体积62。
模块壳体58以及布置壳体60因此可包括从由AlSiC和金属所组成的组中选取的至少一种材料。作为替代或补充，一个或多个模块38的内体积56以及至少部分由布置壳体62所限定的体积62填充有从由硅胶和惰性气体所组成的组中选取的填加物。
优选地，布置壳体60密封由其所限定的体积62。对于这种密封，由此在图1中预知密封件，为了清楚起见一般未示出密封件。密封件能够如本说明书以及图2和图3中所提到和所公开的方式来形成和实现。
图3中，详细示出布置36的模块38的实施例。按照图3，模块38包括模块壳体58，其限定体积56。与上文所述相似，这个体积56例如可填充有惰性气体或者硅胶。还布置在体积56中的是两个功率半导体装置，即，二极管64和IGBT66。半导体装置例如借助于焊料68进一步连接到衬底40或者其导电区域，并且通过接合线70进一步接合到衬底40或者其传导结构。此外，提供密封件59、例如用于将壳体58密封到衬底的金属图案。
关于衬底40，后者包括电绝缘区和导电区，电绝缘区和导电区布置用于通过衬底40从外部接触模块36所包含的至少一个半导体装置。详细来说，衬底40在多层结构中形成，多层结构包括：结构化导电层72、例如铜层，形成导电区域；以及绝缘层74，包括绝缘材料、例如陶瓷材料，例如形成电绝缘区域。因此，导电层72和绝缘层74的结构并且因此导电和绝缘区域的布置布置成使得相应导体例如借助于位于壳体58外部的连接区76来形成，以用于从外部接触模块38。因此，导电区、例如通孔78也可布置在绝缘层74中，以用于提供预期导电通路，或者反之，用于生成层72、74的预期结构。这种布置可基于铜接合氮化硅技术。
衬底40的上面的结构例如可通过将两个陶瓷层相互铜接合来实现。上陶瓷层因此可提供通过焊料以机械方式以及通过丝焊以电气方式来附连功率半导体装置的电路图案。
图4中，示出按照本发明的模块布置36的模块38的另一个实施例。
按照图4，模块38包括模块壳体58。模块壳体58按照这个实施例，但是一般来说也可在单件中形成，或者它可从壁件（wallpiece）80或相应地框架以及盖子82(其可有利地通过密封件84密闭地连接)来形成。可提供其他密封件85以用于将壁件80连接到基板86，后者例如由金属形成。密封件84、85可对应于关于图3所述的密封件59。模块壳体58进一步限定体积56。与上面所述相似，这个体积56例如可填充有惰性气体或者硅胶。进一步布置在体积56中的是两个功率半导体装置，即，二极管64和IGBT66。半导体装置例如借助于焊料68进一步连接到衬底40或者其导电区域、例如金属化88，并且通过接合线70进一步接合到衬底40或者其传导结构。此外，金属化88、例如铜层可布置在衬底40上面和下面。下金属化88可借助于焊料90来连接到基板。
此外，为了电连接模块38的内部组件，提供电导体92，从而连接到例如上金属化88，并且借助于密封件94被引导经过模块壳体58。这些密封件94例如可由玻璃或者由陶瓷材料来形成。
为了产生这种实施例，在第一步骤，具有钎焊的和丝焊的功率半导体装置的衬底40可钎焊到金属基板。此后，具有导体馈通96的金属框架可钎焊或铜焊到基板。馈通96则可使用US焊接来连接到衬底金属化。最后，壳体58可钎焊或铜焊到框架，以便密封该封装。
虽然在附图和在前描述中详细图示和描述了本发明，但是这种图示和描述被认为是说明性的或示范性的而不是限制性的；本发明并不局限于所公开的实施例。根据附图、本公开和所附权利要求书的研究，对所公开的实施例的其他变更在实施所主张的发明中能够由本领域的技术人员理解并且实现。在权利要求书中，词语“包括”并不排除其他元件或步骤，以及不定冠词“一”或者“一个”并不排除多个。在互不相同的从属权利要求中所陈述某些测量的纯粹的事实并不指示这些测量的组合不能用于产生良好效果。权利要求书中的任何参考标号不应当被理解为限制范围。
参考标号列表
10　功率半导体模块
12　外壳
14　功率半导体装置
16　端子
18　栅连接件
20　接合线
22　环氧树脂
24　衬底
26　金属化
28　焊料
30　金属化
31　焊料
32　绝缘凝胶
34　基板
36　模块布置
38　功率半导体模块
40　衬底
42　第一表面
44　第二表面
46　端子
48　栅连接件
50　焊料
52　基板
53　金属化
54　焊料
56　内体积
58　模块壳体
59　密封件
60　布置壳体
62　体积
64　二极管
66　IGBT
68　焊料
70　接合线
72　导电层
74　绝缘层
76　连接区
78　通孔
80　壁件
82　盖子
84　密封件
85　密封件
86　基板
88　金属化
90　焊料
92　电导体
94　密封件
96　馈通。

Claims (10)

1.一种用于功率半导体装置的模块布置，包括一个或多个功率半导体模块(38)，其中所述一个或多个功率半导体模块(38)包括具有第一表面(42)以及布置成与所述第一表面(42)相对的第二表面(44)的衬底(40)，其中该衬底(40)至少部分电绝缘，其中传导结构布置在所述衬底(40)的所述第一表面(42)处，其中至少一个功率半导体装置布置在所述传导结构上并且与其电连接，其中所述一个或多个模块(38)包括用于接收所述至少一个功率半导体装置的内体积(56)，所述体积通过模块壳体(58)从其周围环境密封，其中所述模块布置(36)包括至少部分限定用于接收所述一个或多个模块(38)的体积(62)的布置壳体(60)，并且其中所述布置壳体(60)覆盖所述体积(62)。
2.如权利要求1所述的模块布置，其中，所述一个或多个模块(38)的每个内体积(56)通过模块壳体(58)从其周围环境密封。
3.如权利要求1或2所述的模块布置，其中，至少一个模块(38)的所述衬底(40)包括电绝缘区和导电区，所述电绝缘区和所述导电区布置用于通过所述衬底(40)从外部接触由模块(38)所包括的至少一个半导体装置。
4.如权利要求3所述的模块布置，其中，所述导电区借助于通孔(78)将至少一个功率半导体装置连接到位于所述模块壳体(58)外部的连接区(76)。
5.如前述权利要求中的任一项所述的模块布置，其中，用于接触所述一个或多个模块(38)的内部的电导体(92)借助于密封件(94)被引导经过所述模块壳体(58)。
6.如前述权利要求中的任一项所述的模块布置，其中，所述模块壳体(58)和/或所述布置壳体(60)包括从由AlSiC和金属所组成的组中选取的至少一种材料。
7.如前述权利要求中的任一项所述的模块布置，其中，所述一个或多个模块(38)的所述内体积(56)填充有从由硅胶和惰性气体所组成的组中选取的填加物。
8.如前述权利要求中的任一项所述的模块布置，其中，所述布置壳体(60)密封由其所限定的所述体积(62)。
9.如前述权利要求中的任一项所述的模块布置，其中，至少部分由所述布置壳体(60)所限定的所述体积(62)填充有从由硅胶和惰性气体所组成的组中选取的填加物。
10.一种电气装置，包括前述权利要求中的任一项所述的模块布置(36)。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110313220A (zh) * 2016-12-09 2019-10-08 恩德莱斯和豪瑟尔欧洲两合公司 电子模块

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10959342B2 (en) * 2019-04-08 2021-03-23 Kevin R. Williams Condensation resistant power semiconductor module
US10104759B2 (en) * 2016-11-29 2018-10-16 Nxp Usa, Inc. Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof
US12002780B2 (en) * 2020-11-12 2024-06-04 Taiwan Semiconductor Manufacturing Company Ltd. Package structure including a base and a lid disposed over the base and method of forming the package structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5750926A (en) * 1995-08-16 1998-05-12 Alfred E. Mann Foundation For Scientific Research Hermetically sealed electrical feedthrough for use with implantable electronic devices
CN1226746A (zh) * 1997-04-30 1999-08-25 国际商业机器公司 用于半导体衬底的多层焊料密封带及其工艺
CN1351417A (zh) * 2000-10-31 2002-05-29 富士电机株式会社 电力变换装置
CN101350334A (zh) * 2007-07-20 2009-01-21 英飞凌科技股份公司 具有壳体的半导体组件
CN101989585A (zh) * 2009-07-30 2011-03-23 台湾积体电路制造股份有限公司 微电子封装体

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949697B2 (ja) * 1979-12-10 1984-12-04 三菱電機株式会社 半導体装置
JPH07161925A (ja) * 1993-12-09 1995-06-23 Mitsubishi Electric Corp パワーモジュール
EP0764393B1 (en) * 1995-03-02 2001-07-04 Circuit Components, Incorporated A low cost, high performance package for microwave circuits in the up to 90 ghz frequency range using bga i/o rf port format and ceramic substrate technology
JP2002246515A (ja) * 2001-02-20 2002-08-30 Mitsubishi Electric Corp 半導体装置
JP2003068979A (ja) * 2001-08-28 2003-03-07 Hitachi Ltd 半導体装置
FR2833802B1 (fr) * 2001-12-13 2004-03-12 Valeo Electronique Module de puissance et ensemble de modules de puissance
US6873049B2 (en) * 2003-07-31 2005-03-29 The Boeing Company Near hermetic power chip on board device and manufacturing method therefor
US7183587B2 (en) * 2003-09-09 2007-02-27 Cree, Inc. Solid metal block mounting substrates for semiconductor light emitting devices
JP4154325B2 (ja) 2003-12-19 2008-09-24 株式会社日立産機システム 電気回路モジュール
US7948069B2 (en) 2004-01-28 2011-05-24 International Rectifier Corporation Surface mountable hermetically sealed package
US20060097385A1 (en) * 2004-10-25 2006-05-11 Negley Gerald H Solid metal block semiconductor light emitting device mounting substrates and packages including cavities and heat sinks, and methods of packaging same
US20060124953A1 (en) * 2004-12-14 2006-06-15 Negley Gerald H Semiconductor light emitting device mounting substrates and packages including cavities and cover plates, and methods of packaging same
JP5029078B2 (ja) * 2006-03-15 2012-09-19 株式会社日立製作所 電力用半導体装置
US7880283B2 (en) * 2006-04-25 2011-02-01 International Rectifier Corporation High reliability power module
JP4390799B2 (ja) * 2006-11-21 2009-12-24 株式会社日立製作所 接続材料、接続材料の製造方法、および半導体装置
US8223496B2 (en) * 2007-05-18 2012-07-17 Sansha Electric Manufacturing Co., Ltd. Arc discharge device
US7768109B2 (en) * 2007-08-24 2010-08-03 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP5176507B2 (ja) * 2007-12-04 2013-04-03 富士電機株式会社 半導体装置
US8237260B2 (en) * 2008-11-26 2012-08-07 Infineon Technologies Ag Power semiconductor module with segmented base plate
EP2337070A1 (en) * 2009-12-17 2011-06-22 ABB Technology AG Electronic device with non-linear resistive field grading and method for its manufacturing
DE102010041714A1 (de) 2010-09-30 2011-08-25 Infineon Technologies AG, 85579 Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls
DE102010041849A1 (de) 2010-10-01 2012-04-05 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit einem Grundmodul und einem Verbindungsmodul
US8574965B2 (en) 2010-10-22 2013-11-05 Ati Technologies Ulc Semiconductor chip device with liquid thermal interface material
US20130050228A1 (en) * 2011-08-30 2013-02-28 Qualcomm Mems Technologies, Inc. Glass as a substrate material and a final package for mems and ic devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5750926A (en) * 1995-08-16 1998-05-12 Alfred E. Mann Foundation For Scientific Research Hermetically sealed electrical feedthrough for use with implantable electronic devices
CN1226746A (zh) * 1997-04-30 1999-08-25 国际商业机器公司 用于半导体衬底的多层焊料密封带及其工艺
CN1351417A (zh) * 2000-10-31 2002-05-29 富士电机株式会社 电力变换装置
CN101350334A (zh) * 2007-07-20 2009-01-21 英飞凌科技股份公司 具有壳体的半导体组件
CN101989585A (zh) * 2009-07-30 2011-03-23 台湾积体电路制造股份有限公司 微电子封装体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110313220A (zh) * 2016-12-09 2019-10-08 恩德莱斯和豪瑟尔欧洲两合公司 电子模块

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