CN101002320A - 集成的电路模块和具有这种集成的电路模块的多芯片电路模块 - Google Patents

集成的电路模块和具有这种集成的电路模块的多芯片电路模块 Download PDF

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CN101002320A
CN101002320A CNA2004800437836A CN200480043783A CN101002320A CN 101002320 A CN101002320 A CN 101002320A CN A2004800437836 A CNA2004800437836 A CN A2004800437836A CN 200480043783 A CN200480043783 A CN 200480043783A CN 101002320 A CN101002320 A CN 101002320A
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circuit board
carrier substrates
main circuit
circuit module
semiconductor chip
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托尔班·巴拉斯
阿尔内·F.·雅各布
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Technische Universitaet Braunschweig
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Abstract

本发明描述了一种集成的电路模块(3)，其具有带有端子的载体衬底(4)，所述端子用于该载体衬底(4)与一个主电路板(2)电触点接通，以及具有至少一个与载体衬底(4)电触点接通并且集成到载体衬底(4)中的半导体芯片(9)。该载体衬底(4)具有至少一个与用于主电路板(2)的安装表面(10)邻接的、用于容纳至少一个半导体芯片(9)的腔(8)，并且在该腔(8)中设置有用于至少一个半导体芯片(9)的对应的端子的端子触点(11a，11b)，用于半导体芯片(9)与载体衬底(4)的电触点接通。载体衬底(4)是多层的，具有横向延伸穿过多个层的印制导线，并且腔(8)以密封的并且能够导热的封盖(12)封闭。

Description

集成的电路模块和具有这种集成的电路模块的多芯片电路模块
本发明涉及一种集成的电路模块，其具有带有端子的载体衬底，所述端子用于载体衬底与主电路板电触点接通，以及具有至少一个与载体衬底电触点接通并且集成到载体衬底中的半导体芯片，其中该载体衬底具有至少一个与用于主电路板的安装表面邻接的、用于容纳至少一个半导体芯片的腔，并且在该腔中设置有用于所述至少一个半导体芯片的对应的端子(Anschluesse)的端子触点，用于半导体芯片与载体衬底的电触点接通。
本发明此外涉及一种多芯片电路模块，其具有主电路板、至少一个安装在主电路板上并且与主电路板电触点接通的载体衬底，并且具有至少一个在载体衬底上的半导体芯片用于形成集成的电路模块，其中该半导体芯片与该载体衬底电触点接通，该载体衬底在用于主电路板的安装表面上具有至少一个腔，所述腔用于容纳至少一个半导体芯片，在该腔中设置有用于所述至少一个半导体芯片的对应的端子的端子触点，用于半导体芯片与载体衬底的电触点接通，并且载体衬底的安装表面被施加到主电路板的接触表面上。
多芯片电路模块例如由DE 100 11 005 A1和DE 100 41 770 A1充分已知。特别是在直到100GHz频率范围中的高频电路被以这种多芯片电路模块的形式实现。在此，多芯片电路模块由载体衬底构成，在引线键合工艺或倒装芯片(Flip-Chip)工艺中，单个的半导体芯片被安装到该载体衬底上。合适的半导体芯片例如可以是毫米波单片集成电路MMIC。此外，例如在载体衬底的表面上或在较深的平面中，载体衬底还可以有无源的电路元件。对于高频应用，载体衬底例如可以是多层陶瓷，如例如低温共烧陶瓷LTCC。
具有无源和有源电路元件的载体衬底又形成了子模块，这些子模块被合并在另外的衬底、主电路板上。子模块与主电路板电触点接通，并且由此也彼此电触点接通。
为了将载体衬底与主电路板触点接通(Kontaktierung)，例如由DE 199 31 004 A1公开了球栅阵列BGA—连接技术。
多芯片电路模块接着以介电的填充材料包封，如在DE 101 16 510A1中公开的那样，或者以金属壳体屏蔽，如在DE 100 59 688 A1中所描述的那样。
在EP 0 900 477 B1中描述了一种具有表面波滤波器的电子元件，其中载体衬底以倒装芯片技术被安装在主电路板上。在载体衬底的、与在载体衬底和主电路板之间的连接区域背离的侧上直接施加有金属的保护层，直到主电路板，使得存在对主电路板的紧密密封。
例如在DE 100 41 695 A1、DE 100 43 450 A1和DE 100 29 255A1中描述了倒装芯片技术，用于将半导体芯片电触点接通到载体衬底上或用于借助凸部(Bumps)将载体衬底电触点接通到主电路板上，这些凸部与端子触点相连。
为了屏蔽多芯片电路模块，不利地需要附加的工作步骤。
在DE 196 40 192 A1中描述了一种方法，用于通过使用各向异性的、能传导的粘合剂将集成电路的倒装芯片无凸块地安装到衬底上。
JP 2003174141 A1公开了一种多芯片电路模块，其中半导体芯片与一些凸块相连，这些凸块在载体衬底的层面上被导向在载体衬底的腔中的连接接触。载体衬底的安装表面借助位于中间的填充材料与主电路板的接触表面相连，使得半导体芯片被包封。载体衬底的电触点接通通过至主电路板的腔实现。
传统的多芯片电路模块的问题在于，半导体在安装在主电路板上时才被封装和保护。这对于带有主电路板的集成的电路模块的储藏和安装提出了更高的要求。
因此本发明的任务是实现一种改进的集成的电路模块以及一种改进的具有这种集成的电路模块的多芯片电路模块，它被密封地封装并且仍能够实现良好的散热。
该任务借助这种类型的集成的电路模块以及这种类型的多芯片电路模块通过这种方式解决，即载体衬底是多层的，具有横向延伸穿过多个层的印制导线，并且在多层载体衬底中的腔以密封的并且能够导热的封盖封闭。
通过将半导体芯片设置到与用于主电路板的安装表面相邻接的腔中，通过密封的并且能够导热的封盖保证了良好的直接散热到主电路板上以及集成的电路模块的密封的封装。由此重要的是，腔直接地与主电路板邻接。该腔可以在制造集成的电路模块时在至少一个被容纳在腔中的半导体芯片的触点接通之后密封地通过封盖来封闭，使得集成的电路模块受保护并且相对坚固。
优选的是，在腔中在至少一个半导体芯片和封盖之间设置导热的接触材料。由此可以平衡所述至少一个半导体芯片的高度差并且保证在封盖和半导体芯片之间的良好的热耦合。
此外有利的是，在封盖和主电路板之间设置导热的接触材料，用于封盖与主电路板的直接热耦合。
在主电路板中优选地可以设置与封盖和/或在该封盖上的导热的接触材料邻接的热过孔，用于通过主电路板至主电路板的散热装置的散热。
载体衬底优选地直接与主电路板触点接通，其中载体衬底的安装表面直接地与主电路板邻接。
可选地或对此补充地，载体衬底也可以借助球栅阵列与主电路板触点接通。球栅阵列是具有微焊球的焊接连接，这些微焊球阵列状地彼此相隔一定距离地设置在接触点上。球栅阵列焊接技术由微技术已经充分公开。
载体衬底可以为了进一步改善的散热而被放入主电路板中的凹部中，并且直接地与主电路板的散热装置邻接。由此，热不再必须例如通过热过孔通过主电路板的电绝缘层导向散热装置，而是可以被直接散发。
集成的电路模块与主电路板的电连接例如可以借助载体衬底的端子与主电路板的场耦合(Feldkopplung)来实现。该场耦合可以借助载体衬底的以及主电路板的彼此平行竖立的或者彼此重叠的端子来实现。
但是载体衬底也可以具有在主电路板的接触表面区域中的端子，这些端子直接地或者借助键合连接地与主电路板的对应的端子连接。
以下将借助附图示例性地进一步阐述本发明。其中：
图1示出了本发明的多芯片电路模块第一实施形式的截面图；
图2示出了根据本发明的具有球栅阵列接触的多芯片电路模块的第二实施形式的截面图；
图3示出了根据本发明的具有放入主电路板中的载体衬底和场耦合的多芯片电路模块的第三实施形式的截面图；
图4示出了根据本发明的具有放入主电路板中的载体衬底和直接触点接通的多芯片电路模块的第四实施形式的截面图。
图1中可以看出具有一个施加在主电路板2上的集成的电路模块3的多芯片电路模块1的第一实施形式的截面图。集成的电路模块3具有多层载体衬底4，无源的元件5可以被集成到该载体衬底中。此外在载体衬底4的表面上还可以安装密封封装的有源或无源元件6、7。
在载体衬底4中设置了至少一个腔8用于容纳至少一个在用于主电路板2的载体衬底4的安装表面10上的半导体芯片9。所述至少一个元件与载体衬底4的在腔8的内部的所属的端子触点11a、11b电触点接通。
腔8被以密封的并且导热的封盖12封闭。在制造该集成的电路模块3时，该模块已经以封盖12密封地封闭，使得在随后的加工阶段中对于储藏和集成的电路模块3与主电路板2的安装所必须提出的要求较低。
导热的封盖12此外还用于热能从半导体芯片9至主电路板2的良好的热量导出。热耦合可以借助在半导体芯片9和封盖12之间以及在封盖12和主电路板2的电绝缘的层14之间的导热的接触材料13a、13b来改善。借助导热的接触材料13a、13b，也可以平衡所安装的半导体芯片9的高度波动。
在封盖12和多层的载体衬底4之间的密封可以借助密封的密封物15实现，该密封物例如设置在封盖12的边缘。
通过电绝缘的层14(该层同时通常也不良地导热)至主电路板2的散热装置16的热流可以借助热过孔17改善，这些热过孔与封盖12相邻接地延伸穿过主电路板2的电绝缘层14直到散热装置16。
在所示的实施形式中，集成的电路模块3借助直接的触点接通18与主电路板2电连接，并且基本上直接位于主电路板2上。
在图2中示出了多芯片电路模块1的第二实施形式，其中集成的电路模块3不是直接位于衬底2上，而是电地通过使用球栅阵列(BGA)19与主电路板2电触点接通。这导致了在集成的电路模块3和主电路板2之间的间距，该间距借助导热的接触材料13b来补偿。
图3中可以看到多芯片电路模块1的第三实施形式，其中被密封地封闭的集成的电路模块3被引入特别是电绝缘层14中的、主电路板2的凹部20中。这样的优点是，由半导体芯片9生成的热量通过电接触材料13a、13b和封盖12直接导入主电路板2的散热装置16中。主电路板的电绝缘层14的热阻抗和在半导体芯片9和散热装置16之间的路径中的热过孔17的热阻抗由此不用考虑。
集成的电路模块3可以经过平行的场耦合21a或者经过通过重叠21b的场耦合与主电路板2相连接。在平行的场耦合21a的情况下，集成的电路模块3和主电路板2的对应的电端子以它们的端部直接彼此相对，而彼此不触碰和建立直接的电接触。在通过重叠21b的场耦合情况下，集成的电路模块和主电路板2的端子彼此重叠，而彼此不触碰。
图4中可以看到多芯片电路模块1的第四实施形式，其中集成的电路模块3又被引入主电路板2的电绝缘层14的凹部中。集成的电路模块与主电路板2的电触点接通在此借助键合连接22或借助通过重叠的端子23的直接触点接通及必要时借助直接触点接通18实现。
所示出的借助导热的封盖12密封的封闭的多芯片电路模块1由于所嵌入的半导体芯片9在多层载体衬底4中的密封封装而强健地抗环境影响。在集成的电路模块3安装在载体上之前已经进行的封装能够实现简单的储藏、进一步加工以及测试可能性，例如强化试验(Burn-In)。由于同时的良好的热导出，使得能够将功率半导体使用在集成的电路模块3中。此外，由于与标准工业过程的兼容，多芯片电路模块1还可以被低成本地制造。此外，由于在集成的电路模块3和主电路板2之间的接口的自由的构造可能性，与应用匹配的转换也是可能的。

Claims (13)

1.集成的电路模块(3)，其具有带有端子的载体衬底(4)，所述端子用于该载体衬底(4)与一个主电路板(2)电触点接通，以及具有至少一个与该载体衬底(4)电触点接通并且集成到该载体衬底(4)中的半导体芯片(9)，其中该载体衬底(4)具有至少一个与用于该主电路板(2)的安装表面(10)相邻接的、用于容纳至少一个半导体芯片(9)的腔(8)，并且在所述腔(8)中设置有用于所述至少一个半导体芯片(9)的对应的端子的端子触点，用于所述半导体芯片(9)与该载体衬底(4)的电触点接通，其特征在于，该载体衬底(4)是多层的，具有横向延伸穿过多个层的印制导线，并且所述腔(8)以一个密封的并且导热的封盖(12)封闭。
2.根据权利要求1的集成的电路模块(3)，其特征在于，在所述至少一个半导体芯片(9)和该封盖(12)之间设有导热的接触材料。
3.根据权利要求1或2的集成的电路模块(3)，其特征在于，在该封盖(12)的用于施加到该主电路板(2)上的表面上设有导热的接触材料。
4.多芯片电路模块(1)，其具有一个主电路板(2)、至少一个安装在该主电路板(2)上并且与该主电路板(2)电触点接通的载体衬底(4)，并且具有至少一个在所述载体衬底(4)上的半导体芯片(9)，所述半导体芯片与所述载体衬底(4)电触点接通，其中所述载体衬底(4)在用于所述主电路板(2)的安装表面(10)上具有至少一个腔(8)，用于容纳至少一个半导体芯片(9)，在所述腔(8)中设置有用于所述至少一个半导体芯片(9)的对应的端子的端子触点(11a，11b)，用于所述半导体芯片(9)与所述载体衬底(4)的电触点接通，并且所述载体衬底(4)的安装表面(10)被施加到该主电路板(2)的一个接触表面上，其特征在于，所述载体衬底(4)是多层的，具有横向延伸穿过多个层的印制导线，并且所述腔(8)以一个密封的并且导热的封盖(12)封闭。
5.根据权利要求4的多芯片电路模块(1)，其特征在于，在所述至少一个半导体芯片(9)和该封盖(12)之间设有导热的接触材料(13a，13b)。
6.根据权利要求4或5的多芯片电路模块(1)，其特征在于，在该封盖(12)和该主电路板(2)之间设有导热的接触材料(13a，13b)。
7.根据权利要求4至6之一的多芯片电路模块(1)，其特征在于，与该封盖(12)和/或在该封盖(12)上的该导热的接触材料(13a，13b)相邻接的热过孔(17)。
8.根据权利要求4至7之一的多芯片电路模块(1)，其特征在于，所述载体衬底(4)直接与该主电路板(2)触点接通，并且所述载体衬底(4)的安装表面(10)直接与该主电路板(2)邻接。
9.根据权利要求4至8之一的多芯片电路模块(1)，其特征在于，所述载体衬底(4)借助球栅阵列(19)与该主电路板(2)触点接通。
10.根据权利要求4至9之一的多芯片电路模块(1)，其特征在于，所述载体衬底(4)被引入该主电路板(2)中的一个凹部中，并且直接与该主电路板(2)的一个散热装置(16)邻接。
11.根据权利要求10的多芯片电路模块(1)，其特征在于，所述载体衬底(4)的端子与该主电路板(2)场耦合(21a，21b)。
12.根据权利要求11的多芯片电路模块(1)，其特征在于，所述场耦合(21a，21b)借助所述载体衬底(4)的以及该主电路板(2)的彼此平行竖立的或者彼此重叠的端子(23)来实现。
13.根据权利要求10的多芯片电路模块(1)，其特征在于，所述载体衬底(4)具有在该主电路板(2)的接触表面区域中的端子，及这些端子直接地或者借助键合连接与该主电路板(2)的对应的端子相连接。
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