CN104904009A - 穿过聚合物的通孔和制造这种通孔的方法 - Google Patents

穿过聚合物的通孔和制造这种通孔的方法 Download PDF

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CN104904009A
CN104904009A CN201380069223.7A CN201380069223A CN104904009A CN 104904009 A CN104904009 A CN 104904009A CN 201380069223 A CN201380069223 A CN 201380069223A CN 104904009 A CN104904009 A CN 104904009A
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R·H·波尔马
H·范泽尔
G·张
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Abstract

本发明涉及用于半导体层和晶圆的三维(3D)堆叠、封装和异构集成的通孔。特别地，本发明涉及用于制造通孔的工艺、通孔、3D电路和半导体装置。通孔是用于垂直地(即，在平面外方向上)互连芯片、装置、互连层和晶圆的互连件。

Description

穿过聚合物的通孔和制造这种通孔的方法
技术领域
本发明涉及用于半导体装置和/或晶圆的三维(3D)堆叠、封装和/或异构集成的通孔。特别地，本发明涉及用于制造通孔的工艺、通孔、3D电路以及包括但不限于MEMS(微电机系统)的半导体装置。
背景技术
通孔是用于垂直地(即在平面外方向上)互连芯片、装置、互连层和晶圆的互连件。这可以电子地、光学地或通过微流通道来完成。
现有技术的通孔包括穿过硅的通孔(TSV)。TSV是穿过硅晶圆以建立从芯片的活性侧至背部的电连接的通孔。TSV的缺点是显著的困难通常涉及TSV制造，诸如复杂表面的共形覆盖、窄的高深宽比结构的填充、晶圆减薄以及晶圆由于与用于形成电连接的中介层(例如铜)的材料性质不匹配而引起的破裂。此外，TSV中介层与互连层的准确放置和电连接本身就是一个挑战。
另一方法是穿过模具的通孔(TMV)。TMV通常使用环氧树脂模制复合物钻孔和残留物清除的工艺来形成。该工艺由于通孔的通道的大直径(d≥450μm)、低纵横比(1：1)和焊料的高电阻而非常不适于3D集成。
WO 2006/039633 A2叙述了制造互连元件和包括互连元件的多层连线板的结构和方法。
US 2006/0267213 A1叙述了包括预制高密度馈通的可堆叠层级结构。
US 2008/0170819 A1叙述了光学元件、封装基底和用于光学通信的装置。封装基底具有利用树脂填充的通孔和导体。
US 2003/0139032 A1叙述了金属柱制造方法。
US 2003/0173676 A1叙述了多层半导体装置及其制造方法。
US 2010/0218986 A1叙述了用于制造印刷线路板的方法和印刷线路板。
发明内容
本发明的目标是克服现有技术的通孔及其制造工艺的缺点和/或提供其替代。
在第一方面，本发明涉及一种用于制造通孔的工艺，所述通孔用于半导体装置和/或晶圆的三维堆叠、封装和/或异构集成，所述工艺包括：(a)在载体层或基底上提供聚合物的微结构；(b)将微结构涂布第一导电材料的层以提供涂布的微结构；(c)将涂布的微结构封装在第二电绝缘材料内以使得涂布的微结构形成第二电绝缘材料的上表面和下表面之间的互连。
制造用于半导体装置和/或晶圆的三维堆叠、封装和/或异构集成的通孔的该方法完全不同于现有技术的工艺，诸如用于制造TSV和TMV的工艺。本发明的工艺首先制造通孔，而现有技术的工艺最后制造通孔。
本发明的“通孔优先”方法的显著优点是该工艺具有用于在单一步骤中，即在提供第二电绝缘材料的步骤中将诸如半导体装置、微流体装置和/或MEMS的系统与通孔集成的空间。因此，该工艺对于低成本、大规模制造是有前途的。这从以下说明中将是清楚的。注意，另外的互连层可以放置在通孔的任一侧上或在第二电绝缘材料的顶部上。
在优选实施例中，聚合物是光刻胶。合适的光刻胶的例子包括SU-8和干膜光刻胶层压材料。
将光刻胶用于微结构的特定优点是即使是复杂的结构也可以以高的精确度和可再现性来制造并且尺寸匹配或胜过现有技术的穿过模具的通孔(TMV)或穿过硅的通孔的尺寸。此外，微结构可以同时以低成本并在短时间内制造。光刻胶的暴露和形成可耗费30到45分钟之间。
其中，聚合物是光刻胶，在载体层或基底上提供聚合物的微结构涉及：在载体层或基底上提供光刻胶的层；在光刻胶中图案化(根据使用正性和负性光刻胶而为正性或负性)微结构；将光刻胶暴露于合适波长的辐射(通常为UV或甚至X射线)；将光刻胶暴露于合适的光刻胶显影剂。
作为替换，预制(干膜)光刻胶微结构(诸如光刻胶的块)可以例如通过拾取和放置设备局部地放置，以进一步降低制造本发明的通孔的成本。
光刻胶的层优选地具有100μm至750μm的范围的厚度。在任何情况下，微结构在其最宽点处的高度和宽度优选地使得微结构的纵横比大于5，更优选地大于10，最优选地大于15。从包括通孔的装置等物的最小化的观点来看，高纵横比是有利的。
在优选实施例中，第一导电材料选自包括铜、镍、银和金的组。将微结构涂布铜、镍、银或金的层优选地通过电镀或化学镀、或者溅射和/或蒸镀或丝网印刷来实现。铜、镍、银和金是优良的导体并且易接受电镀和化学镀。
注意，根据本发明的工艺提供的最导电的材料将提供起作用的通孔。铜、镍、银和金的替代物包括特定金属和合金、导电聚合物、导电陶瓷等。本领域技术人员能够识别合适的示例。
在示例中，将微结构封装在第二电绝缘材料内以使得微结构形成第二电绝缘材料的上表面和下表面之间的互连包括在环氧树脂模制化合物中封装。环氧树脂模制化合物是诸如双酚A环氧树脂的环氧树脂。还可以使用陶瓷或硅材料，诸如用于可伸缩电子器件。用于本发明的目的的合适的电绝缘材料的例子对于本领域技术人员是已知的。这种材料在例如微电子领域的封装中是广泛使用的。
在优选实施例中，该工艺还包括步骤(a)在载体层或基底上提供聚合物的微结构与(b)将微结构涂布第一导电材料的层以提供涂布的微结构之间的步骤：诸如通过提供第三导电材料的种子层朝向第一导电材料激活聚合物的微结构。
通过朝向第一导电材料激活聚合物，将微结构涂布材料的步骤被加速。
朝向第一导电材料激活聚合物的微结构的目的是便于并改进层之间的粘附。
朝向第一导电材料激活聚合物的微结构可以采用许多形式并且依赖于特定聚合物和第一导电材料。优选的激活方法的示例在以下参考附图给出。可替代的激活方法包括例如表面制备、表面(化学)修饰和涂布。
在第二方面中，本发明涉及用于半导体层、半导体装置、微系统和/或晶圆的三维堆叠、封装和/或异构集成的通孔，包括在其表面具有第一导电材料的涂层的聚合物微结构，聚合物微结构被封装在第二电绝缘材料内以使得微结构形成第二电绝缘材料的上表面和下表面之间的互连。本发明的通孔适用于应用为电互连件，但还可以应用为光学或微流体互连件，或者一般地多域互连件。
用于3D集成的通孔的优点是：互连件的较短的总长度、低电阻、降低信号延迟以及避免寄生电容和电感。本发明的通孔的特定优点涉及微型化、减少的制造复杂性和成本、创建“复杂的”微结构的可能性。
在优选实施例中，通孔是根据本发明的工艺制备的通孔。
在优选实施例中，聚合物是光刻胶。
此外，微结构的纵横比优选地大于5，更优选地大于10，最优选地大于15。
在第三方面中，本发明涉及具有多个电路层的3D电路，其中，电路层通过根据本发明的一个或多个通孔连接。如所提到的，该连接可以是电子的、光学的或流体的。
在第四方面中，本发明涉及包括本发明的3D电路的装置。
附图说明
现在将参考图1和2的图来进一步说明本发明。附图仅提供用于示意性目的并且不被认为限制本发明或所附权利要求。
图1示出用于利用涂布有第一导电材料的微柱来制造通孔的工艺的优选实施例的详细示图。
图2示出具有本发明的通孔的集成系统的示意图。
具体实施方式
参考图1：
图1a
高纵横比的微柱2通过在基底1的层上图案化厚的光刻胶来创建。两种不同类型的厚的光刻胶薄膜已经被测试用于微柱制造。第一种类型是公知的SU-8负性光刻胶，其利用例如通过旋涂或注射成型来沉积的溶剂以高粘度液体的形式可用。第二种类型是来自SUEX的干膜光刻胶板。使用干膜光刻胶板的优点是将板应用至基底直接导致具有一致厚度的均匀的光刻胶层。光刻胶的合适厚度通常在100μm至750μm的范围内。光刻胶层的厚度根据要从其图案化的微柱的尺寸来确定。期望微柱具有高纵横比以便于最小化使用本发明的通孔制造的装置等的尺寸。
图1b
在微柱2上提供第一导电材料4的层之前，微柱2首先通过在微柱上提供层(合适地，提供种子层)来激活。
测试了用于层沉积的不同技术。该技术是：(i)物理气相沉积(PVD)或溅射；以及(ii)原子层沉积(ALD)。种子层被提供来利用铜(分别)朝向电镀和化学镀激活微柱。
诸如铜或铝的金属薄膜至柱上的物理气相沉积(PVD)或溅射用于在低温下创建半共形的种子层。PVD在超高真空进行以减少粒子污染并提供高质量薄膜。该方法的主要优点是其提供可以直接用于喷镀目的的种子层，因为其不需要诸如通过化学反应或通过与其他化合物相互作用来进一步激活。此外，溅射薄膜具有对溅射其上的基底的出色的粘附性。
原子层沉积是用于沉积超薄共形薄膜的自限制连续表面化学工艺。所使用的材料是氮化钛(TiN)。TiN是导电的、很好地粘附至金属并且具有低的加工温度(<400℃)。
两种不同的ALD技术被测试用于将TiN的薄的共形层施加在微柱2上。高温(400℃)ALD和可以在150℃的较低温度下进行的等离子体增强ALD。
结果产生TiN的共形层，即具有大约60nm的厚度的第三种子层3。在将TiN镀有第一导电材料之前，TiN进一步通过利用HF/Pd溶液的表面激活来激活。HF用于移除TiN上的表面氧化物层以用于Pd播种。
图1c
第一导电材料4的层提供在种子层3的顶部。
两种不同的方法之后用于在种子层3的顶部提供第一导电材料4的层。
针对通过物理气相沉积或溅射激活的微柱2，第一导电材料4(在该情况下为铜)通过电镀直接提供。为了防止腐蚀，通过化学镀将另一金的层提供在铜层的顶部。
针对通过ALD激活并且之后利用HF/Pd溶液进一步激活的微柱，使用化学镀来沉积镍层。在镀镍之后，再次添加金层以防止腐蚀。对于厚膜施加，铜层之后通过电镀沉积在镍和金层(具有5-10μm的厚度)的顶部，并且通过化学镀施加另一金膜以防止腐蚀。
图1d
一旦第一导电材料4的层被提供在微柱2(以及基底1)上，由此涂布的微柱之后封装在第二电绝缘材料5的层中。在该示例中，电绝缘材料5是环氧树脂模制化合物。微柱2被封装以使得涂布的微结构形成第二电绝缘材料5的上表面和下表面之间的互连。
图1e
完成的通孔A可选地从基底移除，并提供(沉积和图案化)背部6和顶部7的互连层。
图1f-i
微柱2可以具有各种形状，诸如2a-d。这种形状不能容易地利用现有技术的通孔制造技术创建。
参考图2，图2示出具有本发明的通孔的集成系统的示意图。
集成系统包括本发明的通孔A、顶部互连层B、底部互连层C、具有凸块的裸芯片D、焊料凸块E、裸芯片直接结合F、裸芯片线结合G、环氧树脂模制化合物H。环氧树脂模制化合物H是封装的第二电绝缘材料5。
本发明的通孔被称为穿过聚合物的通孔(TPV)。
TPV是用于3D集成、封装和堆叠的关键技术实现者。TPV提供用于3D集成的信号传输系统以及适于堆叠多个半导体部件、微系统(MEMS)或用于将部件和系统安装至下一级基底的接触件。此外，TPV适于高容量并行制造。其中，聚合物是光刻胶，TPV的位置可以是平版印刷定义的并且因此极为精确。因此，本发明提供用于3D异构集成和封装的微通孔的低成本、大规模并行制造。
TPV可以应用至：集成电路、半导体芯片、半导体装置、微处理器、微电机系统(MEMS)、固态照明、LED、OLED和其他(高功率)电子器件，其中需要高间距、高输入/输出密度、高纵横比、低成本、良好电迁移性能和低电阻的组合。TPV还可应用以提供微流体或光学性质的互连。

Claims (12)

1.一种用于制造用于半导体装置和/或晶圆的三维堆叠、封装和/或异构集成的通孔(A)的工艺，所述工艺包括：
(a)在载体层或基底(1)上提供聚合物的微结构(2)；
(b)将所述微结构涂布第一导电材料(4)的层以提供涂布的微结构；
(c)将所述涂布的微结构封装在第二电绝缘材料(5)内以使得所述涂布的微结构形成所述第二电绝缘材料(5)的上表面和下表面之间的互连。
2.根据权利要求1所述的工艺，其中，所述聚合物是光刻胶。
3.根据前述权利要求中的一个或多个所述的工艺，其中，所述微结构(2)的纵横比大于5，更优选地大于10，最优选地大于15。
4.根据前述权利要求中的一个或多个所述的工艺，其中，所述第一导电材料(4)选自包括铜、镍、银和金的组。
5.根据前述权利要求中的一个或多个所述的工艺，其中，所述工艺还包括在权利要求1的步骤(a)和(b)之间的步骤：诸如通过提供第三导电材料(3)的种子层朝向所述第一导电材料激活所述聚合物的微结构。
6.根据前述权利要求中的一个或多个所述的工艺，其中，所述第二电绝缘材料是诸如环氧树脂模制化合物的聚合物或陶瓷材料。
7.一种用于半导体装置和/或晶圆的三维堆叠、封装和/或异构集成的通孔(A)，包括在其表面具有第一导电材料(4)的聚合物的互连元件(I)，所述互连元件(I)被封装在第二电绝缘材料(5)内以使得所述互连元件(I)形成所述第二电绝缘材料(5)的上表面和下表面之间的互连，其特征在于，所述互连元件(I)由微结构(2)组成，其中所述第一导电材料被提供为在所述微结构(2)的表面处的涂层。
8.根据权利要求7所述的通孔，其中，所述聚合物是光刻胶。
9.根据权利要求7或8所述的通孔，其中，所述微结构(2)的纵横比大于5，更优选地大于10，最优选地大于15。
10.根据权利要求7-9中任一项所述的通孔，其中，所述第一导电材料(4)选自包括铜、镍、银和金的组。
11.一种具有多个电路层的3D电路，其中，所述电路层通过至少一个根据权利要求7-10中任一项所述的通孔(A)电子地、光学地或流体地连接。
12.一种包括根据权利要求11所述的3D电路的半导体装置。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5431328A (en) * 1994-05-06 1995-07-11 Industrial Technology Research Institute Composite bump flip chip bonding
CN1819169A (zh) * 2005-01-14 2006-08-16 精工爱普生株式会社 电子部件、电光学装置及电子机器
US20100218986A1 (en) * 2009-02-27 2010-09-02 Ibiden Co., Ltd Method for manufacturing printed wiring board and printed wiring board
CN101884258A (zh) * 2007-12-17 2010-11-10 原子能与替代能源委员会 用于实现两个导电层之间的电互连的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3651597B2 (ja) * 1999-06-15 2005-05-25 株式会社フジクラ 半導体パッケージ、半導体装置、電子装置及び半導体パッケージの製造方法
TW502422B (en) * 2001-06-07 2002-09-11 Ultra Tera Corp Method for encapsulating thin flip-chip-type semiconductor device
TW548816B (en) * 2002-01-23 2003-08-21 Via Tech Inc Formation method of conductor pillar
JP2003264253A (ja) * 2002-03-12 2003-09-19 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US7250712B2 (en) * 2004-01-21 2007-07-31 Lumera Corporation Polymer sustained microelectrodes
JP2006108211A (ja) * 2004-10-01 2006-04-20 North:Kk 配線板と、その配線板を用いた多層配線基板と、その多層配線基板の製造方法
US7919844B2 (en) * 2005-05-26 2011-04-05 Aprolase Development Co., Llc Tier structure with tier frame having a feedthrough structure
US7768113B2 (en) * 2005-05-26 2010-08-03 Volkan Ozguz Stackable tier structure comprising prefabricated high density feedthrough
US7907801B2 (en) * 2007-01-17 2011-03-15 Ibiden Co., Ltd. Optical element, package substrate and device for optical communication
KR101023950B1 (ko) * 2009-07-24 2011-03-28 한국과학기술원 전도성 폴리머 범프를 갖는 칩 및 그 제조방법과, 칩을 구비한 전자부품 및 그 제조방법
NL2010077C2 (en) 2013-01-02 2014-07-03 Univ Delft Tech Through-polymer via (tpv) and method to manufacture such a via.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5431328A (en) * 1994-05-06 1995-07-11 Industrial Technology Research Institute Composite bump flip chip bonding
CN1819169A (zh) * 2005-01-14 2006-08-16 精工爱普生株式会社 电子部件、电光学装置及电子机器
CN101884258A (zh) * 2007-12-17 2010-11-10 原子能与替代能源委员会 用于实现两个导电层之间的电互连的方法
US20100218986A1 (en) * 2009-02-27 2010-09-02 Ibiden Co., Ltd Method for manufacturing printed wiring board and printed wiring board

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