JP6490594B2 - ポリマー貫通ビア(tpv)及びそのようなビアを製造する方法 - Google Patents
ポリマー貫通ビア(tpv)及びそのようなビアを製造する方法 Download PDFInfo
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- JP6490594B2 JP6490594B2 JP2015551657A JP2015551657A JP6490594B2 JP 6490594 B2 JP6490594 B2 JP 6490594B2 JP 2015551657 A JP2015551657 A JP 2015551657A JP 2015551657 A JP2015551657 A JP 2015551657A JP 6490594 B2 JP6490594 B2 JP 6490594B2
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Description
図1a
高アスペクト比のマイクロピラー2は、基板1の層上に厚いフォトレジストをパターン化することにより作成される。2つの異なるタイプの厚膜感光性フィルムがマイクロピラー製造用途に試された。第1のタイプは、例えば、スピニング又は射出成型により堆積可能な溶剤を含む高粘性液体状で利用することができる公知のSU−8ネガ型フォトレジストである。第2のタイプは、SUEXからの乾燥フィルムフォトレジストシートである。乾燥フィルムフォトレジストシートを使用する利点は、基板にこのシートを適用することで安定した厚みを有する均一なフォトレジスト層を直接形成することになる点である。フォトレジストの適切な厚みは、通常100μmから750μmまでの範囲である。フォトレジスト層の厚みは、そこからパターン化されるマイクロピラーの寸法に応じて決定される。本発明のビアを使用して製造するデバイス等の寸法の最小化を容易にするために、ピラーは高アスペクト比を有することが望ましい。
マイクロピラー2上に第1の導電材料4の層を与える前に、マイクロピラー2上に1つの層、適切にはシード層3を与えることにより、マイクロピラー2が最初に活性化される。
第1の導電材料4の層をシード層3の上に与える。
第1の導電材料4をマイクロピラー2(及び基板1)上に設けた状態で、このように被覆されたマイクロピラーは、第2の絶縁材料5の層の中にカプセル封入された。この例では、絶縁材料5は、エポキシ成形化合物である。被覆された微細構造が第2の絶縁材料5の上下面間に相互接続部を形成するように、マイクロピラー2は、カプセル封入される。
完成したビアAは、任意的に、基板から取り外され、裏面側−6及び上面側−7の相互接続層が与えられる(堆積及びパターン化されたもの)。
マイクロピラー2は、2a−dのような様々な形状を有することができる。このような形状は、従来のビア製造技術では容易に作成することができない。
2 マイクロピラー
3 シード層
4 第1の導電材料
5 第2の絶縁材料
Claims (9)
- 半導体デバイス及び/又はウェーハの3次元積層、パッケージ化、及び/又は異種集積のためのビア(A)を製造する方法であって、
(a)キャリア層又は基板(1)上に微細構造(2)を与える段階と、
(b)該微細構造(2)をカプセル封入する段階と、
(c)該微細構造を、フォトレジストとして実現された、100μmから750μmの範囲の厚みを有し、5よりも大きいアスペクト比を有するポリマー微細構造(2)として与える段階と、
(d)前記ポリマー微細構造フォトレジスト(2)を導電材料の層(4)で被覆して被覆微細構造を与える段階と、
(e)該被覆微細構造フォトレジストが絶縁材料(5)の上面及び下面間に相互接続部を形成するように前記被覆微細構造フォトレジストを前記絶縁材料(5)内にカプセル封入する段階と、
を含むことを特徴とする方法。 - 前記ポリマーは、フォトレジストであることを特徴とする請求項1に記載の方法。
- 前記導電材料(4)は、銅、ニッケル、銀、及び金から構成される群から選択されることを特徴とする請求項1又は請求項2に記載の方法。
- 請求項1の段階(a)及び(b)の中間に、第3の導電材料(3)のシード層を与える段階により前記導電材料に向けて前記ポリマーの微細構造を活性化する段階を更に含むことを特徴とする請求項1から請求項3のいずれか1項に記載の方法。
- 前記絶縁材料は、ポリマー又はセラミック材料であることを特徴とする請求項1から請求項4のいずれか1項に記載の方法。
- 表面に導電材料(4)を有するポリマーの相互接続要素(I)を含み、絶縁材料(5)の上面及び下面間に相互接続部を形成されるように該相互接続要素(I)が、前記絶縁材料(5)内にカプセル封入される半導体デバイス及び/又はウェーハの3次元積層、パッケージ化、及び/又は異種集積のためのビア(A)であって、
前記相互接続要素(I)は、100μmから750μmの範囲の厚みを有し、5よりも大きいアスペクト比を有する微細構造フォトレジスト(2)から構成され、
前記導電材料は、前記微細構造フォトレジスト(2)の前記表面でのコーティングとして与えられる、
ことを特徴とするビア(A)。 - 前記導電材料(4)は、銅、ニッケル、銀、及び金から構成される群から選択されることを特徴とする請求項6に記載のビア。
- 複数の回路層を有する3D電気回路であって、
前記回路層は、請求項6又は請求項7に記載の少なくとも1つのビア(A)によって電気的に、光学的に、又は流体的に接続される、
ことを特徴とする3D電気回路。 - 請求項8に記載の3D電気回路、
を含むことを特徴とする半導体デバイス。
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NL2010077A NL2010077C2 (en) | 2013-01-02 | 2013-01-02 | Through-polymer via (tpv) and method to manufacture such a via. |
NL2010077 | 2013-01-02 | ||
PCT/NL2013/050888 WO2014107108A1 (en) | 2013-01-02 | 2013-12-11 | Through-polymer via (tpv) and method to manufacture such a via |
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EP (1) | EP2941785B1 (ja) |
JP (1) | JP6490594B2 (ja) |
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DE102018118765A1 (de) | 2018-08-02 | 2020-02-06 | Endress+Hauser SE+Co. KG | Hochfrequenzbaustein |
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US5431328A (en) * | 1994-05-06 | 1995-07-11 | Industrial Technology Research Institute | Composite bump flip chip bonding |
JP3651597B2 (ja) * | 1999-06-15 | 2005-05-25 | 株式会社フジクラ | 半導体パッケージ、半導体装置、電子装置及び半導体パッケージの製造方法 |
TW502422B (en) * | 2001-06-07 | 2002-09-11 | Ultra Tera Corp | Method for encapsulating thin flip-chip-type semiconductor device |
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US7250712B2 (en) * | 2004-01-21 | 2007-07-31 | Lumera Corporation | Polymer sustained microelectrodes |
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US7919844B2 (en) * | 2005-05-26 | 2011-04-05 | Aprolase Development Co., Llc | Tier structure with tier frame having a feedthrough structure |
US7768113B2 (en) * | 2005-05-26 | 2010-08-03 | Volkan Ozguz | Stackable tier structure comprising prefabricated high density feedthrough |
US7907801B2 (en) * | 2007-01-17 | 2011-03-15 | Ibiden Co., Ltd. | Optical element, package substrate and device for optical communication |
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US8153905B2 (en) * | 2009-02-27 | 2012-04-10 | Ibiden Co., Ltd. | Method for manufacturing printed wiring board and printed wiring board |
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EP2941785B1 (en) | 2019-06-19 |
US9576882B2 (en) | 2017-02-21 |
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JP2016505217A (ja) | 2016-02-18 |
CN104904009B (zh) | 2019-04-09 |
EP2941785A1 (en) | 2015-11-11 |
WO2014107108A1 (en) | 2014-07-10 |
HK1216121A1 (zh) | 2016-10-14 |
US20150303131A1 (en) | 2015-10-22 |
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