CN104810404A - 一种精细多晶硅硅化物复合栅结构及其制备方法 - Google Patents
一种精细多晶硅硅化物复合栅结构及其制备方法 Download PDFInfo
- Publication number
- CN104810404A CN104810404A CN201510161435.9A CN201510161435A CN104810404A CN 104810404 A CN104810404 A CN 104810404A CN 201510161435 A CN201510161435 A CN 201510161435A CN 104810404 A CN104810404 A CN 104810404A
- Authority
- CN
- China
- Prior art keywords
- gate
- sio
- polycrystalline silicon
- polysilicon
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 29
- 239000002131 composite material Substances 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 43
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 32
- 239000000956 alloy Substances 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims description 61
- 239000002184 metal Substances 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 150000003377 silicon compounds Chemical class 0.000 claims description 13
- 238000005260 corrosion Methods 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 11
- 238000005275 alloying Methods 0.000 claims description 9
- 238000004528 spin coating Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910019001 CoSi Inorganic materials 0.000 claims description 4
- 206010010144 Completed suicide Diseases 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明是一种射频LDMOS的晶体管的精细多晶硅硅化物复合栅结构及其工艺制备方法,其特征在于,对于亚微米栅的射频LDMOS器件,栅多晶硅表面有一层薄SiO2覆盖保护,通过胶回刻方法来控制栅多晶硅正面和侧面的窗口大小,然后通过各向同性刻蚀的方法去除多晶硅表面的薄SiO2,实现最大化的栅多晶硅表面和侧面的合金面积,本发明的有益效果是,1)通过干法回刻光刻胶方法,实现了栅合金窗口自对准,消除了光刻版的工艺套偏。2)增加了栅多晶硅有效合金面积,降低了栅极电阻。3)频率越高器件将需采用越细的栅,而本方法对细栅的适用性更强。4)与常规的LDMOS工艺制程完全兼容,不增加额外的工序。
Description
技术领域
本发明是涉及的是一种精细多晶硅硅化物复合栅结构及其制备方法,属于半导体微电子设计制造技术领域。
背景技术
在微波技术领域,射频LDMOS器件越来越广泛的应用于通讯基站、广播电视以及现代雷达系统上。为了不断提高LDMOS的频率性能,设计上包括以下几个技术措施:1)不断减薄栅氧化层的厚度,2)采用越来越小多晶硅栅的特征尺寸,3)进一步减小的多晶硅栅阻;由于随着多晶硅栅特征尺寸的减小,使得单位栅宽的栅阻越来越大,于是第2项措施和第3项措施技术有一定的矛盾。因此必须降低单位栅宽的栅阻,通常降低栅阻的做法有的主要方法有高掺杂多晶硅、多晶硅/硅化物复合栅、金属/多晶硅复合栅等,这三种方法所达到的栅方块电阻分别为10~20Ω/□、0.7~1.5Ω/□、0.1~0.3Ω/□。其中单纯高掺杂多晶硅作为栅的方法因其栅阻较大已经很少采用,金属/多晶硅复合栅作为栅的方法在亚微米工艺中由于制造兼容性的难度大也很少采用,因此当前射频LDMOS的小栅阻制作方法通常采用多晶硅/硅化物复合栅的方法。多晶硅/硅化物的制造方法包括:1)栅多晶硅表面淀积一层硅化物,2)栅多晶硅侧面介质保护后表面与金属合金形成硅化物,这些方法的共同特点是多晶硅/硅化物分为上下两层,多晶硅的特征尺寸决定硅化物的尺寸,其栅阻主要由硅化物的厚度决定,另外由于热匹配特性、金属化特性以及工艺制造上的难度存在使得硅化物的厚度很难进一步提升。有一种三面合金的技术(见图2),主要技术思想是多晶硅的两个侧面和上表面都进行硅化物合金,最大限度地降低栅阻大小,其实际实施过程中,如栅氧化层SiO2需要达到一定厚度,可以满足去除合金表面的前序高温工艺形成SiO2后仍有一定的冗余量,另外硅化物的应力较大,其根部直接接触于栅氧化层也使得氧化层的SiO2要保证一定的厚度缓冲,这些厚SiO2氧化层栅对提高射频LDMOS的频率性能是相背的,因此三面合金技术在高频LDMOS制作应用上有一定的局限性;还有一种栅多孔合金技术(见图3),主要技术思想是在多晶硅上打开需要孔或缝,增加内表面的合金面积,控制空洞所占的面积比,使得合金后多晶硅与金属刚好完全反应成硅化物,这可以大幅度增加硅化物的厚度,达到降低栅阻的目的,该技术由于当前工艺水平的限制,还没有得到实际应用。
发明内容
本发明提出的是一种精细多晶硅硅化物复合栅结构及其制备方法,其目的旨在克服现有多晶硅/硅化物技术存在的上述瓶颈,增加多晶硅侧面的合金窗口,进一步增加硅化物的固有尺寸从而降低栅阻的大小。
本发明的技术解决技术方案:一种射频LDMOS的精细多晶硅硅化物复合栅结构,其特征在于,精细多晶硅硅化物复合栅的两侧形成部分硅化物,其中多晶硅为正“凸”形状,表面硅化物为倒“凹”形状,凹凸交界于介质保护窗口。
本发明的有益效果是,器件参数设计于与原常规的参数设计完全兼容,通过增加了栅两侧多晶硅的有效合金面积形成了部分硅化物,使得整体栅阻进一步降低接近一倍, 大幅度提高了射频LDMOS的微波性能。
附图说明
附图1是栅三面合金的结构示意图。
附图2是栅多孔合金的构示意图。
附图3是精细多晶硅栅形成后结构示意图。
附图4是在栅表面用LPCVD工艺在硅片表面淀积300Å~800Å SiO2
钝化层的结构示意图。
附图5是在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度7000Å~12000Å的结构示意图。
附图6是使用选择等离子O2刻蚀方法大面积去除一定厚度的光刻胶,保证栅多晶硅的上表面高出光刻胶2000Å~3000Å的结构示意图。
附图7是用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有1000Å~2000Å厚度的SiO2结构示意图。
附图8是全部光刻胶去除后示意图。
附图9是淀积一层合金金属的结构示意图。
附图10是合金完成后选择性地去除表面残留的未合金金属示意图。
图中的1是栅多晶硅、2是栅氧化层、3是衬底、4是SiO2 钝化层、5是光刻胶、6是待合金金属、7是硅化物。
具体实施方式
一种射频LDMOS的精细多晶硅硅化物复合栅结构,其特征在于,精细多晶硅硅化物复合栅的两侧形成部分硅化物,其中多晶硅为正“凸”形状,表面硅化物为倒“凹”形状,凹凸交界于介质保护窗口。
对照附图1,栅三面合金的结构,此结构中栅多晶硅的上表面和两个侧面都参与硅化合金。
对照附图2,栅多孔合金的结构,此结构中栅多晶硅的从上表面开孔,让内部多晶硅也参与硅化合金。
对照附图3,精细多晶硅栅形成后的结构,此结构中是多晶硅在经过光刻、刻蚀工艺后形成的细栅。
对照附图4,在栅表面用LPCVD工艺在硅片表面淀积300Å~800Å SiO2
钝化层的结构,此结构使得多晶硅表面覆盖一层合适的SiO2 钝化层。
对照附图5,在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度7000Å~12000Å的结构,此结构的光刻胶在旋涂后,保持光刻胶水平高度一致。
对照附图6,使用选择等离子O2刻蚀方法大面积去除一定厚度的光刻胶,保证栅多晶硅的上表面高出光刻胶2000Å~3000Å的结构,此结构利用回刻光刻胶的方法,保证多晶硅栅上表面以及部分侧面的SiO2暴露。
对照附图7,用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有1000Å~2000Å厚度的SiO2结构,此结构形成了多晶硅栅上表面和部分侧面的SiO2被合理去除。
对照附图8,全部光刻胶去除后结构,此结构为去除光刻胶。
对照附图9,淀积一层合金金属的结构,此结构及将待合金的金属到覆盖到整个表面上。
对照附图10,合金完成后选择性地去除表面残留的未合金金属,此结构通过腐蚀待合金金属而不腐蚀硅化物的溶液去除未合金金属,留下硅化物。
精细多晶硅硅化物复合栅的制备方法,包括如下工艺步骤:
1)在一系列工艺形成LDMOS基本结构后,薄栅SiO2厚度100Å~300Å,多晶硅宽度0.25μm~0.5μm,多晶硅高度4000Å~6000Å (图3);
2)用LPCVD工艺在硅片表面淀积300Å~800Å SiO2 介质保护层(图4);
3)在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度7000Å~12000Å(图5);
4)使用选择等离子O2刻蚀方法大面积去除一定厚度的光刻胶,保证栅多晶硅的上表面高出光刻胶2000Å~3000Å(图6);
5)用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有1000Å~2000Å厚度的SiO2(图1);
6)去除表面残留的全部光刻胶(图8);
7)表面淀积一层待硅化合金的金属,进行相应条件的高温合金退火,无SiO2保护层的多晶硅与金属合金形成难融硅化物,表面有SiO2的部分不与金属反应(图9);
8)选择性地去除表面残留的未合金金属(图10);
实施例1:
1)在一系列工艺形成LDMOS基本结构后,薄栅SiO2厚度100Å,多晶硅宽度0.25μm,多晶硅高度4000Å;
2)用LPCVD工艺在硅片表面淀积300ÅSiO2
介质保护层;
3)在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度7000Å;
4)使用选择等离子O2刻蚀方法大面积去除一定厚度的光刻胶,保证栅多晶硅的上表面高出光刻胶上表面2000Å;
5)用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有1000Å厚度的SiO2;
6)用III液去除表面残留的全部光刻胶;
7)表面溅射一层Co金属,进行500℃退火合金,Co与Si形成CoSi硅化物;
8)用III液选择性地腐蚀表面残留的未合金Co金属;
实施例2:
1)在一系列工艺形成LDMOS基本结构后,薄栅SiO2厚度200Å,多晶硅宽度0.35μm,多晶硅高度5000Å;
2)用LPCVD工艺在硅片表面淀积500Å
SiO2 介质保护层;
3)在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度9000Å;
4)使用选择等离子O2刻蚀方法大面积去除一定厚度的光刻胶,保证栅多晶硅的上表面高出光刻胶上表面2500Å;
5)用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有1500Å厚度的SiO2;
6)用III液去除表面残留的全部光刻胶;
7)表面溅射一层Co金属,进行500℃退火合金,Co与Si形成CoSi硅化物;
8)用III液选择性地腐蚀表面残留的未合金Co金属;
实施例3:
1)在一系列工艺形成LDMOS基本结构后,薄栅SiO2厚度300Å,多晶硅宽度0.5μm,多晶硅高度6000Å;
2)用LPCVD工艺在硅片表面淀积800Å
SiO2 介质保护层;
3)在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度12000Å;
4)使用选择等离子O2刻蚀方法大面积去除一定厚度的光刻胶,保证栅多晶硅的上表面高出光刻胶上表面3000Å;
5)用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有2000Å厚度的SiO2;
6)用III液去除表面残留的全部光刻胶;
7)表面溅射一层Co金属,进行500℃退火合金,Co与Si形成CoSi硅化物;
8)用III液选择性地腐蚀表面残留的未合金Co金属。
Claims (4)
1.一种射频LDMOS的精细多晶硅硅化物复合栅结构,其特征在于,精细多晶硅硅化物复合栅的两侧形成部分硅化物,其中多晶硅为正“凸”形状,表面硅化物为倒“凹”形状,凹凸交界于介质保护窗口。
2.如权利要求1所述的精细多晶硅硅化物复合栅结构的制备方法,其特征是该方法包括如下工艺步骤:
1)在一系列工艺形成LDMOS基本结构后,薄栅SiO2厚度100Å~300Å,多晶硅宽度0.25μm~0.5μm,多晶硅高度4000Å~6000Å;
2)用LPCVD工艺在硅片表面淀积300Å~800Å SiO2 介质保护层;
3)在硅片表面旋涂形成一层均匀的光刻胶,光刻胶厚度7000Å~12000Å;
4)使用选择等离子O2刻蚀方法大面积去除光刻胶,保证栅多晶硅的上表面高出光刻胶上表面2000Å~3000Å;
5)用各向同性的湿法腐蚀去除栅多晶硅表面的SiO2保护层,控制好腐蚀参数,保证栅多晶硅侧面的根部仍留有1000Å~2000Å厚度的SiO2;
6)去除表面残留的全部光刻胶;
7)表面淀积一层待硅化合金的金属,进行相应条件的高温合金退火,无SiO2保护层的多晶硅与金属合金形成难融硅化物,表面有SiO2的部分不与金属反应;
8)选择性地去除表面残留的未合金金属。
3.如权利要求2所述的精细多晶硅硅化物复合栅结构的制备方法,其特征是所述步骤6)用III液去除表面残留的全部光刻胶。
4.如权利要求2所述的精细多晶硅硅化物复合栅结构的制备方法,其特征是所述步骤7)表面溅射一层Co金属,进行500℃退火合金,Co与Si形成CoSi硅化物。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510161435.9A CN104810404A (zh) | 2015-04-08 | 2015-04-08 | 一种精细多晶硅硅化物复合栅结构及其制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510161435.9A CN104810404A (zh) | 2015-04-08 | 2015-04-08 | 一种精细多晶硅硅化物复合栅结构及其制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104810404A true CN104810404A (zh) | 2015-07-29 |
Family
ID=53695086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510161435.9A Pending CN104810404A (zh) | 2015-04-08 | 2015-04-08 | 一种精细多晶硅硅化物复合栅结构及其制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104810404A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107086246A (zh) * | 2017-02-28 | 2017-08-22 | 中国电子科技集团公司第五十五研究所 | 一种射频ldmos的薄栅结构及其制备方法 |
US9741822B1 (en) | 2016-09-26 | 2017-08-22 | International Business Machines Corporation | Simplified gate stack process to improve dual channel CMOS performance |
CN107123672A (zh) * | 2017-02-28 | 2017-09-01 | 中国电子科技集团公司第五十五研究所 | 射频LDMOS的PolySi薄栅结构及其制备方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5783479A (en) * | 1997-06-23 | 1998-07-21 | National Science Council | Structure and method for manufacturing improved FETs having T-shaped gates |
JPH1174509A (ja) * | 1997-08-27 | 1999-03-16 | Samsung Electron Co Ltd | Mosfetトランジスタ及びその製造方法 |
US20020008291A1 (en) * | 1997-02-04 | 2002-01-24 | Satoshi Shimizu | Mis transistor and method of fabricating the same |
CN1497708A (zh) * | 2002-09-30 | 2004-05-19 | ��ʿͨ��ʽ���� | 半导体器件的制造方法及制成的半导体器件 |
CN101218667A (zh) * | 2005-07-07 | 2008-07-09 | 富士通株式会社 | 半导体器件及其制造方法 |
CN102403208A (zh) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | Rfldmos器件中栅极的制备方法 |
-
2015
- 2015-04-08 CN CN201510161435.9A patent/CN104810404A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020008291A1 (en) * | 1997-02-04 | 2002-01-24 | Satoshi Shimizu | Mis transistor and method of fabricating the same |
US5783479A (en) * | 1997-06-23 | 1998-07-21 | National Science Council | Structure and method for manufacturing improved FETs having T-shaped gates |
JPH1174509A (ja) * | 1997-08-27 | 1999-03-16 | Samsung Electron Co Ltd | Mosfetトランジスタ及びその製造方法 |
CN1497708A (zh) * | 2002-09-30 | 2004-05-19 | ��ʿͨ��ʽ���� | 半导体器件的制造方法及制成的半导体器件 |
CN101218667A (zh) * | 2005-07-07 | 2008-07-09 | 富士通株式会社 | 半导体器件及其制造方法 |
CN102403208A (zh) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | Rfldmos器件中栅极的制备方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9741822B1 (en) | 2016-09-26 | 2017-08-22 | International Business Machines Corporation | Simplified gate stack process to improve dual channel CMOS performance |
CN107086246A (zh) * | 2017-02-28 | 2017-08-22 | 中国电子科技集团公司第五十五研究所 | 一种射频ldmos的薄栅结构及其制备方法 |
CN107123672A (zh) * | 2017-02-28 | 2017-09-01 | 中国电子科技集团公司第五十五研究所 | 射频LDMOS的PolySi薄栅结构及其制备方法 |
CN107086246B (zh) * | 2017-02-28 | 2020-05-22 | 中国电子科技集团公司第五十五研究所 | 一种射频ldmos的薄栅结构及其制备方法 |
CN107123672B (zh) * | 2017-02-28 | 2020-07-24 | 中国电子科技集团公司第五十五研究所 | 射频LDMOS的PolySi薄栅结构及其制备方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104810404A (zh) | 一种精细多晶硅硅化物复合栅结构及其制备方法 | |
CN105977205B (zh) | 薄膜晶体管、阵列基板的制备方法、阵列基板及显示装置 | |
CN102789968B (zh) | 在半导体制造工艺中形成硬掩模的方法 | |
US20030228760A1 (en) | Method for forming pattern of stacked film | |
CN103219376A (zh) | 氮化镓射频功率器件及其制备方法 | |
CN103187288B (zh) | 一种带有静电保护功能的沟槽半导体功率器件的制备方法 | |
CN102543716B (zh) | 金属硅化物阻挡层的形成方法 | |
KR100971420B1 (ko) | 반도체 소자 제조 방법 | |
CN104934367A (zh) | 一种铜互连的制备方法 | |
CN102800587A (zh) | 一种肖特基二极管的制备工艺 | |
CN105097477A (zh) | 一种镍硅化物的制作方法 | |
US8535970B2 (en) | Manufacturing process for making photovoltaic solar cells | |
CN103137544B (zh) | 一种半导体芯片结构和芯片中金属熔丝的制作方法 | |
CN205248280U (zh) | 绝缘栅双极晶体管的背面结构 | |
CN103187291B (zh) | 一种制备沟槽半导体功率分立器件的方法 | |
CN105448981A (zh) | 一种vdmos器件及其漏极结构和制作方法 | |
CN104465349B (zh) | 沟槽栅半导体器件的制造方法 | |
CN103367133B (zh) | 高介电常数金属栅极制造方法 | |
CN104347373B (zh) | 横向双扩散金属氧化物半导体晶体管的制造方法 | |
CN102376756B (zh) | 多晶硅栅极结构 | |
CN103094188B (zh) | 一种制作芯片上熔丝窗口的方法及熔丝窗口 | |
CN205248281U (zh) | 一种沟槽型frd芯片 | |
CN101882575B (zh) | 防止金属横向扩展的SiC基体上制备欧姆接触的方法 | |
CN102437117B (zh) | 一种新的硅化物和金属前介质集成工艺及该形成的结构 | |
CN109192770A (zh) | 一种pn结终端制造工艺 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150729 |
|
WD01 | Invention patent application deemed withdrawn after publication |