CN104779212A - 半导体封装布置 - Google Patents

半导体封装布置 Download PDF

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Publication number
CN104779212A
CN104779212A CN201510010758.8A CN201510010758A CN104779212A CN 104779212 A CN104779212 A CN 104779212A CN 201510010758 A CN201510010758 A CN 201510010758A CN 104779212 A CN104779212 A CN 104779212A
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China
Prior art keywords
die pad
lead
wire
source electrode
conducting element
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Granted
Application number
CN201510010758.8A
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English (en)
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CN104779212B (zh
Inventor
J.赫格劳尔
R.奥特伦巴
K.希斯
X.施勒格尔
J.施雷德尔
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN104779212A publication Critical patent/CN104779212A/zh
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Publication of CN104779212B publication Critical patent/CN104779212B/zh
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Abstract

半导体封装布置。一种半导体封装布置包括：包括包含源电极和栅电极的第一面的晶体管器件、具有第一表面的管芯垫和具有第一表面的引线。第一导电元件布置在源电极和管芯垫的第一表面之间并且将源电极与管芯垫的第一表面隔开了大于栅电极和引线的第一表面之间的距离。

Description

半导体封装布置
背景技术
电子部件可以包括在具有外部接触的封装中的一个或多个半导体器件。外部接触用于将电子部件安装在再分配板（例如印刷电路板）上。封装可以包括外壳，其覆盖半导体器件和来自半导体器件的内部电连接。封装的外部接触可以具有不同的形式，例如，引脚、连接盘（land）或焊料球。
发明内容
在实施例中，一种半导体封装布置包括具有包括源电极和栅电极的第一面的晶体管器件、具有第一表面的管芯垫和具有第一表面的引线。第一导电元件布置在源电极和管芯垫的第一表面之间并且将源电极与管芯垫的第一表面隔开了大于栅电极和引线的第一表面之间的距离的距离。
在实施例中，一种半导体封装包括具有第一表面的管芯垫、至少两个引线和具有包括源电极和栅电极的第一面和与第一面相对的第二面的晶体管器件，所述第二面包括漏电极。第一导电元件布置在源电极和管芯垫的第一表面之间并且将源电极与管芯垫的第一表面隔开了大于栅电极和引线的第一表面之间的距离的距离。
附图说明
附图中的元件不必要相对于彼此按比例。相同的参考数字指定对应的相同部分。各种所示的实施例的特征可以被组合，除非它们互相排斥。实施例在附图中被描绘并且在接着的描述中被详述。
图1示出根据第一实施例的半导体封装布置。
图2示出根据第二实施例的半导体封装布置。
图3示出根据第三实施例的半导体封装布置。
图4示出根据第四实施例的半导体封装布置。
图5示出根据第五实施例的半导体封装的截面图。
图6示出根据第六实施例的半导体封装的顶部透视图。
具体实施方式
在下面的详细描述中，参考附图，这些附图构成了该详细描述的一部分，在这些图中借助图示示出了其中可以实施本发明的特定实施例。在这方面，方向性术语，例如"顶部"、"底部"、"前"、"后"、"前面"、"后面"等等，是参考所描述的一个或多个图的取向来使用的。由于实施例的部件可被定位在许多不同的取向上，因此方向性术语用于说明的目的，并且决不是限制性的。应当理解可以利用其它实施例，并且可以在不脱离本发明的范围的情况下做出结构或逻辑改变。因此，下面的详细描述不是以限制性意义进行的，并且本发明的范围由所附权利要求限定。
下面将解释多个实施例。在这种情况下，相同的结构特征在图中由相同或类似的参考符号标识。在本描述的上下文中，“横向”或“横向方向”应当理解为意指通常平行于半导体材料或半导体载体的横向伸展延伸的方向或伸展。由此横向方向通常平行于这些表面或面扩展。与此相比，术语“垂直”或“垂直方向”被理解为意指通常垂直于这些表面或面并由此垂直于横向方向延伸的方向。因此垂直方向在半导体材料或半导体载体的厚度方向上延伸。
如在该说明书中所采用的，术语"耦合"和/或"电耦合"并非意味着意指元件必须直接耦合在一起—可以在"耦合"或"电耦合"元件之间提供插入元件。
如这里所用的，“高电压器件”，例如高电压耗尽型晶体管，是被优化用于高电压开关应用的电子器件。也就是，当晶体管关断时，它能够阻挡高电压，例如大约300V或更高，大约600V或更高、或者大约1200V或更高，并且当晶体管导通时，它对于其中使用它的应用来说具有足够低的导通电阻（RON），即，当大量电流经过该器件时它经受足够低的导通损耗。高电压器件可以至少能够阻挡等于其所用于的电路中的高电压供应或最大电压的电压。高电压器件可以能够阻挡300V、600V、1200V或该应用所需的其它合适的阻挡电压。
如这里所用的，“低电压器件”，例如低电压增强型晶体管，是能够阻挡低电压（例如在0V和Vlow之间）、但是不能够阻挡高于Vlow的电压的电子器件。Vlow可以是大约10V，大约20V，大约30V，大约40V，或者在大约5V和大约50V之间，例如在大约10V和30V之间。
图1示出根据第一实施例的布置10，其包括半导体器件，尤其是晶体管器件11，该晶体管器件11具有包括源电极13和栅电极14的第一面12。该布置还包括具有第一表面16的管芯垫15、具有第一表面18的引线17和第一导电元件19。第一导电元件19布置在源电极13和管芯垫15的第一表面16之间并且将源电极13与管芯垫15的第一表面16隔开了大于栅电极14和引线17的第一表面18之间的距离d2的距离d1。
晶体管器件11可以是MOSFET或绝缘栅双极晶体管（IGBT）并且可以是高电压器件。晶体管器件11可以是垂直器件。晶体管器件11以所谓的源极向下布置被安装，其中源电极13面向管芯垫15。管芯垫15的第一表面16和引线17的第一表面18面向晶体管器件11的第一面12。引线17布置成邻近管芯垫15的侧面并且晶体管器件11在管芯垫15和引线17之间扩展使得它覆盖引线17和管芯垫15之间的间隙20。栅电极14可以被安装在引线17的第一表面18上并且例如通过焊料连接21与该第一表面18电耦合。
源极向下布置可以帮助减小源极连接的寄生电感，其又可以帮助改善开关效率。图1中所示的布置可以用于将具有源极向下布置的晶体管器件11安装在标准封装中，例如超级SO8（SuperSO8）、TO220 或TO247封装外形。在包括引线17的上表面18和管芯垫15的上表面16之间的高度差的封装外形中，该高度差可以由第一导电元件19的高度补偿。因此，虽有引线17的第一表面18和管芯垫15的第一表面16之间的高度差，但晶体管器件11的第一面12可以基本上是平面的。
晶体管器件11和管芯垫15之间的距离d1可以被选择来帮助获得期望的雪崩电压。例如，该距离可以被选择为每10V 1μm并且雪崩电压可以位于从10V到10kV的范围。另外，第一导电元件19可以具有一种形式和布置使得形成在晶体管器件11的第一面12和侧面24之间的晶体管器件11的边缘23与第一导电元件19的外表面25和管芯垫15的上表面16间隔开。
栅电极14可以被安装在引线17的第一表面18上并且例如通过焊料连接与该第一表面18电耦合。源电极13可以通过第一导电元件19电耦合到管芯垫15。引线17的第一表面18可以布置在与管芯垫15的第一表面16不同的平面内。引线17可以被形成为使得引线17的第一表面18的近端部分（其定位成邻近管芯垫15）布置在与管芯垫15的第一表面16不同的平面内。引线17的其余远端部分可以位于不同的平面内，例如，其余远端部分可以与管芯垫15基本上共面。
布置10还可以包括布置在栅电极14和引线17的第一表面18之间的第二导电元件21。第二导电元件21可以具有小于第一导电元件19的高度的高度。布置10还可以包括布置在源电极13和管芯垫15的第一表面16之间的多个第一导电元件19。该多个第一导电元件可以彼此隔开，并且以矩形布置定位在源电极13的横向区域上方。
第一导电元件19和第二导电元件21（如果存在）可以包括具有第一熔点的第一部分和具有低于第一熔点的第二熔点的第二部分。第一部分可以基本上被第二部分覆盖使得第一导电元件包括芯，该芯具有比围绕该芯的覆盖物（mantle）高的熔点。在一些实施例中，只有第一部分的侧面可以基本上被第二部分覆盖，并且第一部分与源电极和管芯垫直接接触或者与栅电极和引线直接接触。
第一部分可以包括球形凸块、楔形凸块或接合线环。球形凸块、楔形凸块或接合线环可以包括金属或合金，例如铝或金、或铝合金或金合金。第二部分可以包括焊料，例如软焊料、或导电粘合剂。焊料或导电粘合剂可以符合第一部分的外部轮廓使得焊料或导电粘合剂与形成在晶体管器件11的第一面12和侧面24之间的边缘23隔开。形成在晶体管器件11的第一面12和侧面24之间的晶体管器件11的边缘23可以与第一导电元件19的第二部分隔开一定距离。布置10以及尤其是第一导电元件19还可以包括布置在第一部分和第二部分之间的金属间相。第一部分可以包括金属或合金，第二部分可以包括焊料并且金属间相可以包括存在于第一部分中的至少一个元件和存在于第二部分中的至少一个元件。
该布置可以用在包括具有第一表面的管芯垫、至少两个引线和至少一个晶体管器件的半导体封装中。晶体管器件包括具有源电极和栅电极的第一面以及与第一面相对并且包括漏电极的第二面。第一导电元件布置在源电极和管芯垫的第一表面之间并且将源电极与管芯垫的第一表面隔开了大于栅电极和引线的第一表面之间的距离的距离。栅电极可以布置在引线上。半导体封装可以包括布置在栅电极和引线的第一表面之间的第二导电元件。第二导电元件可以将栅电极与引线的第一表面隔开小于源电极和管芯垫之间的距离的距离。在半导体封装内的引线最接近于管芯垫的一端和管芯垫之间的间隙小于在半导体封装的外表面处的引线的各部分和管芯垫之间的距离。引线可以被形成为使得引线最接近管芯垫的一端布置在半导体封装内并且引线远离管芯垫的一端至少部分地从半导体封装暴露。漏电极可以例如通过一个或多个接合线或接触夹电耦合到所述引线中的至少一个。形成在晶体管器件的第一面和至少一个侧面之间的晶体管器件的至少一个边缘可以与第一导电元件隔开一定距离。
半导体封装还可以包括第二管芯垫以及包括具有源电极和栅电极的第一面和与第一面相对的包括漏电极的第二面的第二晶体管器件。第二晶体管器件的漏电极可以布置在第二管芯垫上并且电耦合至第二管芯垫。可以以半桥布置来配置第一晶体管器件和第二晶体管器件。
图2示出包括具有第一面32的晶体管器件31的布置30，源电极33和栅电极34布置在该第一面32上。晶体管器件31包括包含漏电极36的相对的第二面35。该布置还包括具有上表面38的管芯垫37和包括上表面40的引线39。晶体管器件31被布置成使得第一面32面向管芯垫37的上表面38和引线39的上表面40。引线39与管芯垫37的侧面41隔开一定距离并且具有一种形式使得在邻近侧面41的近端部分中的引线39的上表面40布置在与管芯垫37的上表面38不同的平面内。特别地，引线39的近端42被定位于管芯垫37的上表面38上方。引线39可以被弯曲或者以其它方式形成使得引线39的远端43基本上与管芯垫37共面。
源电极33安装在管芯垫37上并且通过在源电极33和管芯垫37的上表面38之间扩展的第一导电元件44电耦合到管芯垫37。第一导电元件44具有将源电极33与管芯垫37的上表面38间隔开的高度和小于源电极33的横向伸展的横向伸展。形成在晶体管器件31的第一面32和侧面46之间的边缘45与管芯垫37和引线39隔开一定距离并且保持不被提供源电极33和管芯垫37之间的电耦合的第一导电元件44的材料覆盖。
布置30包括布置在引线39的近端42的上表面40和栅电极34之间的第二导电元件47。第二导电元件47具有小于第一导电元件44的高度的高度，使得晶体管器件31的第一面32基本上是平面的。
第一导电元件44包括被第二部分49围绕的第一部分48。第一部分48具有高于第二部分49的熔点的熔点。例如，第一部分48可以包括金属或合金，例如铝或铜或铝合金，并且第二部分49可以包括例如包括锡的焊料（例如铅锡银焊料）的软焊料、或者导电粘合剂。在该实施例中，第一部分48由球形凸块形成。球形凸块可以使用接合线形成装置来制造例如以将球形凸块附着到管芯垫37的上表面38。然后球形凸块48可以被焊料或焊料膏或导电粘合剂覆盖。第二部分49可以被熔化和重新固化以在机械上和电气上将源电极33连接到管芯垫37。
第一部分48可以与源电极33直接接触或者第二部分49的区域的小区域可以布置在第一部分48和源电极33之间。
第一部分48可以用于提供第一导电元件44的物理间隔性质，因为它在第二部分49被熔化以将源电极33粘附和电耦合到管芯垫37时保持固态。然而，第一部分48还提供由第一导电元件44提供的导电连接的一部分，因为它也是导电的。
第二导电元件47还包括具有第一熔点的第一部分50和具有低于第一熔点的第二熔点的第二部分51。第一部分50也可以是包括金属或合金的球形凸块，并且第二部分51可以包括软焊料或导电粘合剂。球形凸块50具有比球形凸块48小的高度和横向大小。
第一导电元件的第一部分48可以包括至少一个元件，当第二部分49熔化时该至少一个元件与第二部分49的至少一个元件反应以形成金属间化合物。金属间化合物的形成可以帮助在源电极33和管芯垫37之间提供良好的机械结合。金属间化合物在图2中由杂乱区域（hashed region）示意性地指示在第一部分48和第二部分49之间的界面处。第二导电元件47的第一部分50还可以包括至少一个元件，该至少一个元件与第二部分51的至少一个元件形成至少一个金属间相以帮助在栅电极34和引线39之间以及在第一部分50和第二部分51之间产生良好的机械结合。
在实施例中，第一部分48包括铜并且第二部分49包括含锡的焊料，例如铅锡银焊料。类似地，第二导电元件47的第一部分50可以包括铜并且第二部分51可以包括含锡的焊料，例如铅锡银焊料。
布置30还包括包含模塑料（例如环氧树脂）的外壳52。外壳52覆盖晶体管器件31和管芯垫37的上表面38以及引线39的上表面40。引线39的近端42被定位于外壳52内使得近端42的下表面53完全嵌入外壳52内。引线39的远端43的下表面54从外壳52暴露并且提供外部接触。管芯垫37的下表面55也从外壳52暴露并且提供外部接触。
在外壳内的侧面41和引线39的侧面56之间的间隙57在图2中由a1表示。引线39的远端43的暴露的下表面54和管芯垫37的下表面55之间的间隙58较大并且在图2中被表示为a2。引线39的弯曲布置使得引线39的侧面56和管芯垫37的侧面41之间的距离能够在外壳52内为小的，这在安装晶体管器件31时可能是有用的，因为晶体管器件31桥接该间隙57。由远端43的下表面54和管芯垫37的下表面55在外壳52的最外表面59处提供的邻近导电区域之间的间隙58较大，由此使得能够增大爬电距离，虽然在外壳52内的引线39和管芯垫37之间有较小间隙57。
图3示出根据第三实施例的布置60。布置60包括具有图2所示配置的引线39、晶体管器件31和管芯垫37。根据第三实施例的布置60与图2所示的布置不同之处在于布置在源电极33和管芯垫37的上表面38之间的第一导电元件44的结构。
第一导电元件44包括第一部分61和基本上覆盖第一部分61的第二部分62。第一部分61由接合线环63提供。接合线环63具有通过热压接合头附着到上表面38的第一端64并且以弧65扩展到与第一端64隔开一定距离的第二端66。第二端66通过例如楔形凸块附着到管芯垫37的上表面38。弧65可以用于提供间隔元件，该间隔元件具有适合于将源电极33与管芯垫37的上表面38隔开期望距离的高度。第一部分61被第二部分62覆盖，第二部分62具有比接合线环63的材料低的熔点。接合线环可以例如包括铝或铝合金或铜。第二部分62可以包括软焊料。
布置60还包括布置在栅电极34和引线39的近端42的上表面40之间的第二导电元件47。第二导电元件47包括被第二部分51围绕的第一部分50。第一部分可以包括接合线环或者可以包括不同的第一部分，例如球形凸块。
图4示出根据第四实施例的布置70。布置70包括具有图2和3所示配置的引线39、晶体管器件31和管芯垫37。根据第四实施例的布置70包括布置在源电极33和管芯垫37的上表面38之间的多个导电元件71，其中所述多个导电元件71中的两个可以在图4的截面图中看到。
在第四实施例中，每个第一导电元件71包括接合线环形式的第一部分72和覆盖第一部分72的第二部分73。所述多个第一导电元件71中的各个导电元件彼此横向间隔开并且均在源电极33和管芯垫37之间扩展。
所述多个第一导电元件71可以具有不同的结构，例如，每个第一导电元件可以包括被焊料覆盖的球形凸块或被焊料覆盖的楔形凸块。所述多个第一导电元件71可以均匀分布在源电极33的横向区域上以提供均匀的机械连接。所述多个第一导电元件的每一个可以具有相同结构或者所述第一导电元件中的一个或多个的结构可以不同。
布置70还包括布置在栅电极34和引线39的近端42的上表面40之间的第二导电元件74。第二导电元件74包括楔形接合形式的第一部分75，该第一部分75基本上被具有比楔形接合75的熔点低的熔点的第二部分76覆盖。楔形接合75可以包括铝或铜并且可以通过使用楔形接合工具在引线39的上表面40上制造楔形接合来被产生。然后楔形接合可以被具有较低熔点的导电材料（例如导电粘合剂或软焊料）覆盖。
引线39可以通过修剪平面引线39来形成以产生位于远端43上方的近端42。引线还可以通过将平面引线弯曲来形成，这在图2和3中所示的实施例中被说明。
图3到4中所示的布置可以用在具有标准外形的封装（例如超级SO8封装）中或者用在TO型封装（例如T0220或TO247封装）中。封装外形可以是所谓的直通孔封装，其中引线被安装在电路板的孔中，或者具有表面安装器件配置，其中引线被安装在电路板的表面上。
图5示出半导体封装80，其是具有标准封装外形（例如TO220封装外形）的直通孔封装。半导体封装80还包括包含晶体管器件82形式的半导体器件的布置81和引线框86，该晶体管器件82具有包括源电极84和栅电极85的第一面83。
引线框86包括管芯垫87和三个引线，其中仅一个引线88在图5的截面图中被看到。三个引线被定位成邻近管芯垫87的公共侧面89。所述引线中的两个与管芯垫87的侧面89隔开一定距离，并且第三引线（在图5的截面图中看不到）从管芯垫87扩展。所述多个引线具有被定位于比管芯垫87的上表面91高的平面内的第一表面90。
晶体管器件82被布置成使得它在引线88和管芯垫87之间扩展。源电极84面向管芯垫的上表面91并被定位于该上表面91上，并且栅电极85面向引线88的第一表面90并被定位于该第一表面90上。
布置81还包括布置在源电极84和管芯垫87的上表面91之间的第一导电元件92，该第一导电元件92将源电极84与管芯垫87的上表面91隔开。第一导电元件92在机械上和电气上将源电极84耦合到管芯垫87。第一导电元件92包括具有熔点T1的第一隔离物部分93和具有熔点T2的第二部分94，由此T2小于T1。这使得第二部分94能够在第一部分93保持固态并维持晶体管器件82的第一面83和管芯垫87之间的间隔的同时被熔化。
第一隔离物部分93由球形凸块提供，所述球形凸块在源电极84和管芯垫87的上表面91之间扩展并且将管芯垫87的上表面91上的源电极84隔开了距离D1。第二部分94至少围绕第一隔离物部分93的侧面并且包括导电材料，例如软焊料或导电粘合剂。第二部分94在源电极84和管芯垫87之间提供粘附连接。
布置81还包括布置在栅电极85和引线88的第一表面90之间的第二导电元件95。第二导电元件95布置在引线88邻近于管芯垫87的侧面89的近端96处。第二导电元件95包括在栅电极85和引线88的第一表面90之间扩展的第一隔离物部分97和至少覆盖第一隔离物部分97的侧面的第二部分98。第一隔离物部分97包括具有熔点T3的材料并且第二部分98包括具有熔点T4的材料，其中T4小于T3。第二导电元件95的第一隔离物部分97和第二部分98的材料可以与第一导电元件92的第一隔离物部分93和第二部分94的材料相同。在这种情况下，T3等于T1并且T4等于T2。这使得源电极84和栅电极85能够在同一工艺中并且在相同的温度下附着到引线框86。第一隔离物部分97可以由球形凸块提供，所述球形凸块在栅电极85和引线88的第一表面90之间扩展。
第二导电元件95具有比第一导电元件92的高度小的高度，使得栅电极85与管芯垫87的上表面91隔开一定距离D2。距离D2小于源电极84和管芯垫87的上表面91之间的距离D1。晶体管器件82的第一面83布置成基本上平行于引线88的第一表面90和管芯垫87的上表面91，并且基本上是平面的。栅电极85和引线88的第一表面90之间的距离D2与源电极84和管芯垫87的上表面91之间的距离D1的差由第一导电元件92和第二导电元件95的不同大小补偿。
晶体管器件82是垂直器件并且包括在背向管芯垫87的其上部第二面100上的漏电极99。漏电极99通过接触夹101电耦合到邻近引线88定位的所述引线之一，所述接触夹101通过例如焊料连接电耦合到漏电极99并且通过另外的焊料连接（其在图5的截面图中看不到）电耦合到引线。
半导体封装80还包括模塑料（例如环氧树脂）形式的外壳102。环氧树脂覆盖管芯垫87的上表面91和侧面89、晶体管器件82、第一导电元件92、第二导电元件95、接触夹101和引线的近端96。引线的近端96的下表面103也被嵌入外壳102的环氧树脂中使得引线从半导体封装80的外壳102的第一侧面104突出。管芯垫87从外壳102的相对面105扩展并且提供在外壳102外部的热沉区域106。热沉区域106还可以包括直通孔107，利用该直通孔107，热沉区域106和管芯垫87可以附着到另外的部件，例如电路板或其它支撑件的一部分。管芯垫87的下表面108从环氧树脂暴露。
第一导电元件92的使用使得晶体管器件82能够以所谓的源极向下布置被安装在标准封装外形内，其中引线的第一表面90布置在与管芯垫87的上表面91不同的平面内。第一导电元件92还将晶体管器件82的第一面83和形成在第一面83和晶体管器件82的侧面110之间的边缘109与管芯垫87的上表面91隔开。
第一导电元件92的横向区域可以被选择成使得边缘109被形成外壳102的环氧树脂围绕并且不与第一导电元件92接触。第一导电元件92的第二部分94可以在源电极84电耦合到管芯垫87时处于流体状态。在该流体状态，第二部分94可以符合第一隔离物部分93的外表面以便限定第一导电元件92的横向区域。
第一导电元件92的横向区域可以通过限定第二部分94和第一隔离物部分93的横向区域和/或通过选择形成第二部分94的材料的量而被限定。类似地，第二导电元件95的横向区域可以通过限定第二部分98和第一隔离物部分97的横向区域和/或通过选择形成第二部分98的材料的量而被限定。
栅电极85一般具有比源电极84小的横向区域，使得可以提供单个第二导电元件95，而可以提供多个第一导电元件92。
尽管在图5的截面图中示出了一个第一导电元件92，但是可以提供彼此间隔开的两个或更多个第一导电元件92。所述两个或更多个第一导电元件中的每一个在管芯垫87的上表面91和源电极84之间扩展。
第一导电元件92和/或第二导电元件95的结构可以不同于图5中所示的结构。例如，代替球形凸块，第一隔离物部分93可以由接合线环或楔形凸块提供。类似地，第二导电元件95的第一隔离物部分97可以包括楔形凸块或接合线环来代替球形凸块。
图6示出包括采用半桥配置的第一晶体管器件121和第二晶体管器件122的半导体封装120的顶部透视图。半导体封装120包括第一管芯垫123和第二管芯垫124，在第一管芯垫123上安装第一晶体管器件121，在第二管芯垫124上安装第二晶体管器件122。第二管芯垫124布置成邻近第一管芯垫123并且与第一管芯垫123共面。
半导体封装120还包括提供第一栅极接触端子的L形引线125。第一管芯垫123包括在一个角的切割体（cutout）并且提供近端部分127的引线125的腿被定位于该切割体中、邻近第一管芯垫123。引线125的近端部分127向上稍微弯曲并且被定位于比第一管芯垫123的上表面和第二管芯垫124的上表面的平面高的平面内。
半导体封装120还包括包含三个外部接触129的引线框部分128，该引线框部分128被定位成邻近在第一管芯垫123的第一面130上的引线125。第二管芯垫124布置成邻近第一管芯垫123的相对面131并且具有L形，该L形包括定位于L形的远端处的至少两个外部接触132。另外的两个引线133、134布置成邻近第二管芯垫124的突出部分并且与具有外部接触132的第二管芯垫124隔开一定距离。引线128、133、134基本上与第一管芯垫123和第二管芯垫124共面。
第一晶体管器件121以源极向下布置被安装并且具有布置在角区域中的栅电极126，所述栅电极126借助导电元件135安装在引线125的近端部分127上。源电极136也布置在第一晶体管器件121的下面137上，并且安装在第一管芯垫123上并通过多个导电元件138电耦合到第一管芯垫123。定位于栅电极126和引线125的近端部分127之间的导电元件135具有小于定位于源电极136和第一管芯垫123之间的导电元件138的高度的高度。导电元件138使得第一晶体管器件121的下面137能够布置成离第一管芯垫123的上表面一定距离。
第二晶体管器件122以漏极向下取向安装在第二管芯垫124上，使得第二晶体管器件122的漏电极耦合到第二管芯垫124。第二管芯垫124的外部接触132提供半桥配置的Vin端子。第二晶体管器件122包括在其上表面上的源电极139和栅电极140。源电极139通过接合线141电耦合到引线133并且提供源极感测功能。栅电极140通过接合线142电耦合到引线134。因此引线134提供半导体封装120的第二栅极端子。
布置在上表面144上的第一晶体管器件121的漏电极143通过导电元件145电耦合到第二晶体管器件122的源电极139，所述导电元件145可以是一个或多个接合线或接触夹。半导体封装120还包括在第一晶体管器件121的漏电极143和引线框部分128之间扩展的导电元件146。引线框部分128为半桥配置提供输出端子Vout。导电元件145可以例如由一个或多个接合线或由接触夹来提供。
半导体封装120还包括覆盖引线125、128、133、134的上面以及第一管芯垫123和第二管芯垫124的上面、第一晶体管器件121和第二晶体管器件122以及各接合线的外壳147。外壳可以由模塑料（例如环氧树脂）形成并且还可以将引线125、128、133、134和管芯垫123、124彼此电隔离。
第一晶体管器件121的下面137布置成离第一管芯垫123的上表面一定距离。形成在第一晶体管器件121的下面137和侧面之间的边缘布置成离第一管芯垫123的上表面一定距离并嵌入外壳147中。
第一晶体管器件121的源极向下布置可以帮助减小源极连接的寄生电感，其又可以帮助改善开关效率。第一晶体管器件121和第一管芯垫123之间的距离可以被选择来帮助获得期望的雪崩电压。
为了易于描述，使用例如"下方"、"以下"，"下部"，"上方"、"上部"等的空间相对术语来解释一个元件相对于第二个元件的定位。这些术语旨在除了包括不同于图中所描绘的那些取向之外的取向以外还包括器件的不同取向。
另外，还使用例如"第一"、"第二"等的术语来描述各种元件、区域、区段等，并且这些术语也并不旨在是限制性的。在整个描述中，类似的术语指代类似的元件。
如这里使用的，术语"具有"、"包括"、"包含"、"含有"等是开放式术语，其指示所声明的元件或者特征的存在，但并不排除附加的元件或者特征。冠词"一"、"一个"和"该"旨在包括复数和单数，除非上下文另有清楚指示。
应当理解的是，除非另外特别指出，否则这里所描述的各个实施例的特征可以相互组合。
虽然这里已经示出和描述了特定实施例，但本领域技术人员将认识到，在不脱离本发明的范围的情况下，多种替换和/或等效实施方式可替代所示出和描述的特定实施例。本申请旨在涵盖这里所讨论的特定实施例的任何改编或变型。因此，本发明旨在仅由权利要求及其等同物限定。

Claims (20)

1.一种半导体封装布置，包括：
包括第一面的晶体管器件，所述第一面包括源电极和栅电极；
包括第一表面的管芯垫，和
包括第一表面的引线，
其中第一导电元件布置在所述源电极和所述管芯垫的第一表面之间并且将所述源电极与所述管芯垫的第一表面隔开了大于所述栅电极和所述引线的第一表面之间的距离的距离。
2.根据权利要求1所述的布置，其中所述栅电极布置在所述引线的第一表面上。
3.根据权利要求1所述的布置，其中所述源电极通过所述第一导电元件电耦合到所述管芯垫。
4.根据权利要求1所述的布置，其中所述引线的第一表面布置在不同于所述管芯垫的第一表面的平面内。
5.根据权利要求1所述的布置，其中所述引线被形成为使得所述引线的第一表面中邻近所述管芯垫定位的部分被布置在与所述管芯垫的第一表面不同的平面内。
6.根据权利要求1所述的布置，还包括布置在所述栅电极和所述引线的第一表面之间的第二导电元件。
7.根据权利要求1所述的布置，还包括布置在所述源电极和所述管芯垫的第一表面之间的多个第一导电元件。
8.根据权利要求1所述的布置，其中所述第一导电元件包括包含第一熔点的第一部分和包含低于第一熔点的第二熔点的第二部分。
9.根据权利要求8所述的布置，其中所述第一部分基本上被所述第二部分覆盖。
10.根据权利要求8所述的布置，其中所述第一部分包括由下述构成的组中的至少一个：球形凸块、楔形凸块和接合线环。
11.根据权利要求8所述的布置，其中所述第二部分包括焊料和导电粘合剂中的至少一个。
12.根据权利要求11所述的布置，其中所述第二部分包括符合所述第一部分的外部轮廓的焊料，使得所述焊料与形成在所述晶体管器件的所述第一面和至少一个侧面之间的边缘隔开。
13.根据权利要求8所述的布置，还包括布置在所述第一部分和所述第二部分之间的金属间相。
14.根据权利要求9所述的布置，其中形成在所述晶体管器件的所述第一面和侧面之间的所述晶体管器件的边缘与所述第二部分隔开一定距离。
15.一种半导体封装，包括：
包括第一表面的管芯垫；
至少两个引线，和
一个或多个晶体管器件，其包括包含源电极和栅电极的第一面和与所述第一面相对的第二面，所述第二面包括漏电极，
其中第一导电元件布置在所述源电极和所述管芯垫的第一表面之间并且将所述源电极与所述管芯垫的第一表面隔开了大于所述栅电极和所述引线的第一表面之间的距离的距离。
16.根据权利要求15所述的半导体封装，其中在所述半导体封装内的所述引线最接近于所述管芯垫的一端和所述管芯垫之间的间隙小于在所述半导体封装的外表面处的所述引线的各部分和所述管芯垫之间的距离。
17.根据权利要求15所述的半导体封装，其中所述漏电极电耦合到所述引线中的至少一个。
18.根据权利要求15所述的半导体封装，其中形成在所述晶体管器件的第一面和至少一个侧面之间的所述晶体管器件的边缘与所述第一导电元件隔开一定距离。
19.根据权利要求15所述的半导体封装，还包括第二管芯垫和第二晶体管器件，所述第二晶体管器件包括包含源电极和栅电极的第一面和与所述第一面相对的第二面，所述第二面包括漏电极，其中所述漏电极布置在所述第二管芯垫上。
20.根据权利要求19所述的半导体封装，其中所述第一晶体管器件和所述第二晶体管器件以半桥布置配置。
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