CN104620373A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104620373A
CN104620373A CN201380048064.2A CN201380048064A CN104620373A CN 104620373 A CN104620373 A CN 104620373A CN 201380048064 A CN201380048064 A CN 201380048064A CN 104620373 A CN104620373 A CN 104620373A
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power semiconductor
resin
semiconductor chip
packing material
thermal conductivity
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三柳俊之
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

通过搭载在功率半导体模块内的功率半导体芯片的不与布线薄膜对置的表面、以及键合线表面由不含导热性填充材料的密封树脂A密封,并且密封树脂A由含导热性填充材料的密封树脂B密封,能够兼具功率半导体模块的冷却性能和长期可靠性。

Description

半导体装置
技术领域
本发明涉及半导体装置,特别涉及搭载了功率半导体芯片的功率半导体模块。
背景技术
搭载多个IGBT(绝缘栅双极型晶体管)和/或功率MOSFET、FWD(续流二极管)等功率半导体芯片,且利用变换器等用作电力控制的称为功率半导体模块的半导体装置在产业领域中被广泛使用。
在功率半导体模块中,为了保护配置在树脂壳体内的附有布线薄膜的绝缘基板和在该布线薄膜上用焊料等接合的功率半导体芯片,在树脂壳体内填充硅凝胶等密封树脂而密封。通过该硅凝胶确保树脂壳体内的绝缘性能(绝缘耐压)。
另一方面,由于功率半导体芯片在动作时产生高热,所以提高对功率半导体芯片冷却的性能在确保功率半导体模块的长期可靠性时至关重要。因此,在现有的功率半导体模块中,在用于保持功率半导体芯片的绝缘基板的背侧,用焊料等接合金属制的基体板,进而再设置散热片等,实现冷却性能的提高。
图4是现有的功率半导体模块100的主要部分剖视图。功率半导体芯片1使用焊料(未图示)等被接合在由氧化铝等绝缘性材料构成的绝缘基板3的表面上配置的布线薄膜2上。应予说明,布线薄膜2通常是由铜和/或铜合金构成。
另外,对于功率半导体芯片1而言,通过在半导体芯片的厚度方向流通电流而控制电力,从而存在芯片两个表面具有不同功能的电极。因此,需要对半导体芯片中的与布线薄膜相对的面的相反一侧的面实施不同的布线,作为该布线,一般使用由铜和/或铝、金等构成的键合线6。
进而,为了确保对由功率半导体芯片1发出的热进行冷却的性能,使绝缘基板3和由铜和/或铝等构成的金属基体板5密合。应予说明,作为密合材料使用焊料的情况下,如图4所示,在绝缘基板的背侧进一步需要由铜和/或铜合金等构成的金属薄膜4。
将上述构成和各种布线(未图示)组装于壳体框7中后,填充由硅凝胶构成的密封树脂A,进而安装壳体盖8而完成功率半导体模块100。
然而,现有的功率半导体模块100如图5所示绝缘基板3、金属基体板5由于导热率高,所以有助于散热,另一方面,由于密封用硅凝胶(密封树脂A)的导热率低,所以几乎对散热没有帮助。因此,在高耐压下使用功率半导体芯片1的情况等,当由功率半导体芯片1发出的热多时,无法确保充分的冷却性能,长期可靠性存在问题。
因此,如专利文献1和2所示那样,已知通过在密封用硅凝胶中添加具有绝缘性且高导热性的填充材料(填料)而改善冷却性能。具有添加了填充材料的硅凝胶的功率半导体模块110如图6所示,使用在密封材料的硅凝胶中添加二氧化硅和/或氧化铝、金刚石等填充材料,且在维持绝缘性能的同时改善了导热性的密封树脂B。由此,功率半导体模块110如图7所示能够确保从功率半导体芯片1的两个表面进行散热,因此冷却性能得到改善。
另一方面,在含有上述导热性填充材料的硅凝胶中,与以往的硅凝胶相比,无法忽视热应力的影响,由此在固定支撑在基板和/或半导体芯片的突起电极中会产生剥离的问题。因此,报道有像图8所示的功率半导体模块120那样,在突起电极11的周边使用由以往的硅凝胶构成的密封树脂A,在其上使用含填充材料的密封树脂B的方案(专利文献2)。
现有技术文献
专利文献
专利文献1:日本特开平5-129474号公報
专利文献2:日本特开昭62-21249号公報
发明内容
在专利文献1和2中,如图6和图8所示,为了对功率半导体芯片的不与布线薄膜对置的表面和/或键合线的表面进行密封,可使用含导热性填充材料的密封树脂B。
然而,经过本发明人的深入研究,其结果发现这样的情况下长期可靠性会产生问题。原因如下。
使功率半导体模块运行时,产生由发生的损耗引起的温度周期,其结果,会产生由绝缘基板和/或金属基体板的热收缩导致的功率半导体芯片的微振动和/或由键合线自身的热收缩导致的微振动。
另一方面,前述的导热性填充材料通常硬度高,所以功率半导体芯片和/或键合线因温度周期发生微振动时,硬度高的填充材料会产生磨耗,会产生键合线的断线和/或功率半导体芯片特性劣化等。
为了解决上述的课题,本发明的目的在于提供长期可靠性和冷却性能的均优异的半导体装置。
为了实现上述的目的,提供一种半导体装置,具备:在两个表面具有芯片电极的功率半导体芯片;在主表面具有布线薄膜的绝缘基板;键合线;金属基体板;不包含导热性填充材料的树脂A;包含导热性填充材料的树脂B,上述功率半导体芯片被载置在上述布线薄膜上,上述键合线将上述芯片电极与除上述芯片电极以外的电极电连接,上述绝缘基板被载置在上述金属基体板上,在上述功率半导体芯片的不与上述布线薄膜对置的表面和上述键合线的表面由上述树脂A密封,并且,该树脂A由上述树脂B密封。
有益效果
在本发明中,在安装于功率半导体模块的功率半导体芯片的不与布线薄膜对置的表面和键合线的表面由不含填充材料的密封树脂A密封,并且密封树脂A由含导热性填充材料的密封树脂B密封。
因此,能够将从功率半导体芯片产生的热向密封树脂侧释放,并且能够防止由硬度高的填充材料导致的部件的磨耗,能够同时实现长期可靠性和冷却性能。
附图说明
图1是本发明的第一实施例的半导体装置的剖视图。
图2是本发明的第二实施例的半导体装置的剖视图。
图3是本发明的第三实施例的半导体装置的剖视图。
图4是本发明的第一以往例的半导体装置的剖视图。
图5是表示本发明的第一以往例的半导体装置的散热特性的示意图。
图6是本发明的第二以往例的半导体装置的剖视图。
图7是表示本发明的第二以往例的半导体装置的散热特性的示意图。
图8是本发明的第三以往例的半导体装置的剖视图。
符号说明
1 功率半导体芯片
2 布线薄膜
3 绝缘基板
4 金属薄膜
5 金属基体板
6 键合线
7 壳体框
8 壳体盖
9 外部导出端子
11 突起电极
10、20、30、100、110、120 功率半导体模块
A 不含导热性填充材料的密封树脂
B 含导热性填充材料的密封树脂
具体实施方式
在以下的实施例中说明实施方式。
<实施例1>
图1是本发明的第一实施例的半导体装置的剖视图。
在图1所示的功率半导体模块10中,IGBT和/或功率MOSFET、FWD等功率半导体芯片1使用焊料(未图示)等被接合在由氧化铝和/或氮化铝等构成的绝缘基板3的表面上形成有图案的布线薄膜2上。应予说明,布线薄膜2由具有优异的导电性的铜和/或铜合金构成,能够利用所谓的DCB(DirectCopper Bonding:直接铜键合)法而形成。
另外,在功率半导体芯片1的两个表面,在IGBT中配置发射极、集电极以及栅极,在FWD中配置阴极和阳极这样的具有不同功能的芯片电极(未图示),所以除了配置于与利用焊接等接合的布线薄膜2对置的表面上的芯片电极之外,在其背面配置的芯片电极也需要施加布线。
因此,使用键合线6,从配置于上述相反面的芯片电极向除芯片电极以外的电极进行布线。这里出于导电率和/或键合时的操作性等考虑,键合线6由铜和/或铝、金等金属或其合金构成。另外,除芯片电极以外的电极是指,例如下面进行说明的其他图案电极、在实施例3中说明的外部导出端子9,以及除此之外的具有多个半导体芯片的情况下的其他的半导体芯片的电极。
这里,暂时在布线薄膜2的其他图案电极利用键合线6进行布线,再从该布线薄膜图案的另一端,重新进行外部导出端子(未图示)等所需要的布线。由此,能够使键合线6的长度为最小限值,因此对无法忽略键合线的材料成本等的情况下(例如使用金线的情况下)有益。
另外,为了确保对由半导体芯片1发出的热进行冷却的性能,使绝缘基板3经由金属薄膜4与由铜和/或铝等构成的金属基体板5密合。在将焊料(未图示)作为密合材料的情况下,使焊料直接与绝缘基板3的表面密合是较为困难的,所以在绝缘基板3的表面设置由铜和/或铜合金构成的金属薄膜4。金属薄膜4与布线薄膜2相同,能够利用DCB法形成。
应予说明,作为绝缘基板3和金属基体板5的密合材料使用粘接剂的情况下,不一定需要金属薄膜4。
上述构成和各种布线(未图示)被设置于壳体框7中,被设置的壳体内部局部地由不含导热性填充材料的密封树脂A密封。其理由是保护功率半导体芯片1的不与布线薄膜2对置的表面和键合线6的表面与含在密封树脂B中并用作填料的导热性填充材料等隔离。作为密封树脂A的密封材料,特别地,当使用硅凝胶时具有有益效果,因此优选除去不可避免的杂质且不含有导热性填充材料的硅凝胶。在功率半导体芯片1的不与布线薄膜2对置的表面至少包含连接有键合线6的形成有芯片电极的表面。
这里,作为密封材料使用硅凝胶的理由是,能够具有高耐久性和耐热性,并且由于为凝胶状而能够以图1所示那样的方式来控制填充范围。
另外,壳体内部由覆盖密封树脂A且含有导热性填充材料的密封树脂B密封。其理由是保护密封树脂A和壳体内部的其他部件与异物和/或水分等隔离,在确保绝缘性的同时,改善针对由功率半导体芯片1发出的热进行冷却的性能。作为密封树脂B的密封材料,特别是使用硅凝胶具有有益效果。
在密封树脂B的上述导热性填充材料中,使用由氧化铝、二氧化硅、碳化硅、氮化硅、氮化铝、氧化镁、金刚石、类金刚石碳等无机材料构成的粒状粉末。
应予说明,在产品成本优先的情况下,选择氧化铝和/或二氧化硅、类金刚石碳等廉价的材料,在冷却性能优先的情况下,选择碳化硅和/或氮化硅、氮化铝、氧化镁、金刚石等导热率高的材料具有有益效果。
对于功率半导体模块10而言,进一步使壳体盖8载置在上述壳体框7的开口面。其理由是防止异物和/或水分混入功率半导体模块10的内部,确保绝缘性。
如上说明,在本实施例中,功率半导体芯片1的不与布线薄膜2对置的表面、以及键合线6的表面局部地由不含导热性填充材料的密封树脂A密封,除此之外的部分由含导热性填充材料的密封树脂B密封。
由此,在将导热性填充材料最大限地有效利用的同时,保护功率半导体芯片1的不与布线薄膜对置的表面和键合线6的表面不受到由导热性填充材料引起的磨耗。因此,能够确保可靠性,并且进一步使冷却性能良好,所以在由功率半导体芯片1发出的热优先的情况下具有有益效果。此外,为了进一步提高冷却性能,在金属基体板5上设置散热片,用液体冷却金属基体板5和/或上述散热片具有有益效果。
<实施例2>
图2是本发明的第二实施例的半导体装置的剖视图。
对于该实施例的功率半导体模块20而言,关于填充到第一实施例的功率半导体模块10的壳体内部的密封树脂,将不含导热性填充材料的密封树脂A并非局部地,而是以键合线全部浸入为止均匀地填充到壳体内部键合线来进行密封。
并且,为了使密封树脂A的表面全部密封,以使含导热性填充材料的密封树脂B相互为层状的方式进行填充而密封。
如此,不需要局部填充不含导热性填充材料的密封树脂A,省略用于控制填充喷嘴位置的单元等,所以在功率半导体模块20的制造成本优先的情况下具有优益效果。
<实施例3>
图3是本发明的第3实施例的半导体装置的剖视图。
对于该实施例的半导体模块30而言,关于第二实施例的功率半导体模块100的布线,将键合线6直接从芯片电极向外部导出端子9实施布线。
如此,键合线6的长度变长,另一方面,向外部导出端子9键合的操作次数1次就能完成,所以与键合线6的材料成本相比,降低键合操作次数时更为有益的情况下具有优益效果。
权利要求书(按照条约第19条的修改)
1.一种半导体装置,其特征在于,具备:
功率半导体芯片,在两个表面具有芯片电极;
绝缘基板,在主表面具有布线薄膜;
键合线;
金属基体板;
树脂A,以硅凝胶为主成分而构成,且不包含导热性填充材料;
树脂B,以硅凝胶为主成分而构成,且包含导热性填充材料,
其中,所述功率半导体芯片被载置在所述布线薄膜上,
所述键合线将所述芯片电极与除所述芯片电极以外的电极进行电连接,
所述绝缘基板被载置于所述金属基体板,
所述功率半导体芯片的不与所述布线薄膜对置的表面、以及所述键合线的表面由所述树脂A密封,并且该树脂A由所述树脂B密封。
2.根据权利要求1所述的半导体装置,其特征在于,
所述树脂A与所述树脂B相互为层状。
3.根据权利要求1所述的半导体装置,其特征在于,
在由所述金属基体板、壳体框以及壳体盖构成的箱体的内部,填充所述树脂A和所述树脂B。
4.根据权利要求1至3所述的半导体装置,其特征在于,
所述导热性填充材料由选自氧化铝、二氧化硅、碳化硅、氮化硅、氮化铝、氧化镁、金刚石、类金刚石碳中的一种或两种以上的物质构成。
说明或声明(按照条约第19条的修改)
按照专利合作条约的第19条(1)的修改声明
权利要求1明确了树脂A和树脂B是以硅凝胶为主成分而构成。
权利要求3明确了在由所述金属基体板、壳体框以及壳体盖构成的箱体的内部,填充所述树脂A和所述树脂B。
权利要求1和权利要求3的修改是基于说明书第[0025]段~第[0027]段的记载。

Claims (4)

1.一种半导体装置,其特征在于,具备:
功率半导体芯片,在两表面具有芯片电极;
绝缘基板,在主表面具有布线薄膜;
键合线;
金属基体板;
树脂A,不包含导热性填充材料;
树脂B,包含导热性填充材料,
其中,所述功率半导体芯片被载置在所述布线薄膜上,
所述键合线将所述芯片电极与除所述芯片电极以外的电极进行电连接,
所述绝缘基板被载置于所述金属基体板,
所述功率半导体芯片的不与所述布线薄膜对置的表面、以及所述键合线的表面由所述树脂A密封,并且该树脂A由所述树脂B密封。
2.根据权利要求1所述的半导体装置,其特征在于,
所述树脂A与所述树脂B相互为层状。
3.根据权利要求1所述的半导体装置,其特征在于,
所述树脂A和所述树脂B以硅凝胶为主成分而构成。
4.根据权利要求1至3所述的半导体装置,其特征在于,
所述导热性填充材料由选自氧化铝、二氧化硅、碳化硅、氮化硅、氮化铝、氧化镁、金刚石、类金刚石碳中的一种或两种以上的物质构成。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106684057A (zh) * 2016-12-30 2017-05-17 华为技术有限公司 芯片封装结构及其制造方法
CN110447099A (zh) * 2017-04-20 2019-11-12 罗姆股份有限公司 半导体器件
CN110494977A (zh) * 2017-04-21 2019-11-22 三菱电机株式会社 电力用半导体模块、电子部件以及电力用半导体模块的制造方法
CN111630401A (zh) * 2018-01-26 2020-09-04 三菱电机株式会社 半导体装置以及电力变换装置
CN111725145A (zh) * 2020-06-16 2020-09-29 杰群电子科技(东莞)有限公司 一种半导体封装结构、封装方法及电子产品
CN111725160A (zh) * 2020-06-16 2020-09-29 杰群电子科技(东莞)有限公司 一种高功率半导体模组、封装方法及电子产品
CN112910287A (zh) * 2019-12-04 2021-06-04 三菱电机株式会社 功率用半导体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102335771B1 (ko) * 2014-12-01 2021-12-06 삼성전자주식회사 열전도 필름을 가진 반도체 패키지
JP6984155B2 (ja) * 2017-04-06 2021-12-17 株式会社デンソー 電子装置
US11233037B2 (en) 2017-04-20 2022-01-25 Rohm Co., Ltd. Semiconductor device
JP7131436B2 (ja) 2019-03-06 2022-09-06 三菱電機株式会社 半導体装置及びその製造方法
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US20220238459A1 (en) * 2019-08-20 2022-07-28 Mitsubishi Electric Corporation Semiconductor device, power conversion device and moving body
WO2022172351A1 (ja) * 2021-02-10 2022-08-18 三菱電機株式会社 半導体パワーモジュール

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040102023A1 (en) * 2002-08-13 2004-05-27 Fuji Electric Co., Ltd. Semiconductor device and method of relaxing thermal stress
JP2009212342A (ja) * 2008-03-05 2009-09-17 Kansai Electric Power Co Inc:The 半導体装置
JP2011222869A (ja) * 2010-04-13 2011-11-04 Kansai Electric Power Co Inc:The 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221249A (ja) 1985-07-22 1987-01-29 Hitachi Ltd 半導体装置
JP2927081B2 (ja) * 1991-10-30 1999-07-28 株式会社デンソー 樹脂封止型半導体装置
JP3223835B2 (ja) * 1997-03-28 2001-10-29 三菱電機株式会社 パワー半導体装置及びその製造方法
JPH10270608A (ja) * 1997-03-28 1998-10-09 Hitachi Ltd 樹脂封止型パワー半導体装置
JP3764687B2 (ja) * 2002-02-18 2006-04-12 三菱電機株式会社 電力半導体装置及びその製造方法
JP2008270469A (ja) * 2007-04-19 2008-11-06 Mitsubishi Electric Corp パワーモジュール及びその製造方法
JP5428512B2 (ja) * 2009-05-13 2014-02-26 日産自動車株式会社 半導体装置
JP5393373B2 (ja) * 2009-09-16 2014-01-22 関西電力株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040102023A1 (en) * 2002-08-13 2004-05-27 Fuji Electric Co., Ltd. Semiconductor device and method of relaxing thermal stress
JP2009212342A (ja) * 2008-03-05 2009-09-17 Kansai Electric Power Co Inc:The 半導体装置
JP2011222869A (ja) * 2010-04-13 2011-11-04 Kansai Electric Power Co Inc:The 半導体装置

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI663695B (zh) * 2016-12-30 2019-06-21 大陸商華為技術有限公司 晶片封裝結構及其製造方法
CN106684057B (zh) * 2016-12-30 2019-10-22 华为技术有限公司 芯片封装结构及其制造方法
US10903135B2 (en) 2016-12-30 2021-01-26 Huawei Technologies Co., Ltd. Chip package structure and manufacturing method thereof
CN106684057A (zh) * 2016-12-30 2017-05-17 华为技术有限公司 芯片封装结构及其制造方法
CN110447099A (zh) * 2017-04-20 2019-11-12 罗姆股份有限公司 半导体器件
CN110447099B (zh) * 2017-04-20 2023-11-07 罗姆股份有限公司 半导体器件
CN110494977A (zh) * 2017-04-21 2019-11-22 三菱电机株式会社 电力用半导体模块、电子部件以及电力用半导体模块的制造方法
CN110494977B (zh) * 2017-04-21 2023-04-18 三菱电机株式会社 电力用半导体模块、电子部件以及电力用半导体模块的制造方法
CN111630401B (zh) * 2018-01-26 2022-09-16 三菱电机株式会社 半导体装置以及电力变换装置
CN111630401A (zh) * 2018-01-26 2020-09-04 三菱电机株式会社 半导体装置以及电力变换装置
CN112910287A (zh) * 2019-12-04 2021-06-04 三菱电机株式会社 功率用半导体装置
CN112910287B (zh) * 2019-12-04 2024-04-05 三菱电机株式会社 功率用半导体装置
CN111725160A (zh) * 2020-06-16 2020-09-29 杰群电子科技(东莞)有限公司 一种高功率半导体模组、封装方法及电子产品
CN111725145A (zh) * 2020-06-16 2020-09-29 杰群电子科技(东莞)有限公司 一种半导体封装结构、封装方法及电子产品

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