CN104616979A - 半导体器件的形成方法 - Google Patents

半导体器件的形成方法 Download PDF

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Publication number
CN104616979A
CN104616979A CN201310542823.2A CN201310542823A CN104616979A CN 104616979 A CN104616979 A CN 104616979A CN 201310542823 A CN201310542823 A CN 201310542823A CN 104616979 A CN104616979 A CN 104616979A
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side wall
semiconductor device
grid structure
described side
semiconductor substrate
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CN201310542823.2A
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CN104616979B (zh
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何永根
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to US14/287,500 priority patent/US9362402B2/en
Publication of CN104616979A publication Critical patent/CN104616979A/zh
Priority to US15/147,397 priority patent/US10553719B2/en
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Abstract

一种半导体器件的形成方法，包括：提供半导体衬底，所述半导体衬底表面具有栅极结构；在所述半导体衬底表面形成侧墙，所述侧墙位于栅极结构两侧；对所述侧墙进行稳定性掺杂，提高所述侧墙抗腐蚀的能力；以所述侧墙为掩膜，刻蚀位于栅极结构两侧的半导体衬底，在所述栅极结构两侧的半导体衬底内形成凹槽；形成填充满所述凹槽的应力层。本发明提高了侧墙的抗腐蚀能力，从而降低后续刻蚀工艺对侧墙的刻蚀速率，避免暴露出栅极结构的侧壁，防止在形成应力层时在栅极结构侧壁形成缺陷膜，提高半导体器件的可靠性，优化半导体器件的电学性能。

Description

半导体器件的形成方法
技术领域
本发明涉及半导体制作领域，特别涉及半导体器件的形成方法。
背景技术
随着半导体技术的不断发展，载流子迁移率增强技术获得了广泛的研究和应用，提高沟道区的载流子迁移率能够增大半导体器件的驱动电流，提高器件的性能。
现有半导体器件制作工艺中，由于应力可以改变硅材料的能隙和载流子迁移率，因此通过应力来提高半导体器件的性能成为越来越常用的手段。具体地，通过适当控制应力，可以提高载流子（NMOS器件中的电子，PMOS器件中的空穴）迁移率，进而提高驱动电流，以此极大地提高半导体器件的性能。
目前，采用嵌入式锗硅（Embedded SiGe）技术，即在需要形成源区和漏区的区域先形成锗硅材料，然后再进行掺杂形成PMOS器件的源区和漏区；形成所述锗硅材料是为了引入硅和锗硅（SiGe）之间晶格失配形成的压应力，以提高PMOS器件的性能；采用嵌入式碳硅（Embedded SiC）技术，即在需要形成源区和漏区的区域先形成碳硅材料，然后再进行掺杂形成NMOS半导体器件的源区和漏区，形成所述碳硅材料是为了引入硅和碳硅（SiC）之间晶格失配形成的拉应力，以提高NMOS器件的性能。
嵌入式锗硅技术和嵌入式碳硅技术的应用可以提高半导体器件的载流子迁移率，但是在实际应用中发现，半导体器件的形成工艺仍存在电学性能差的问题。
发明内容
本发明解决的问题是提供一种优化的半导体器件的形成方法，提高侧墙的稳定性，从而提高侧墙的抗腐蚀能力，避免在形成应力层时暴露出栅极结构的侧壁，从而避免在栅极结构的侧壁形成缺陷膜，提高半导体器件的电学性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供半导体衬底，所述半导体衬底表面具有栅极结构；在所述半导体衬底表面形成侧墙，所述侧墙位于栅极结构两侧；对所述侧墙进行稳定性掺杂，提高所述侧墙的抗腐蚀能力；以所述侧墙为掩膜，刻蚀位于栅极结构两侧的半导体衬底，在所述栅极结构两侧的半导体衬底内形成凹槽；形成填充满所述凹槽的应力层。
可选的，所述稳定性掺杂为对所述侧墙进行碳掺杂。
可选的，在进行所述碳掺杂后，所述侧墙的材料中碳原子含量为0.5%至10%。
可选的，所述侧墙的材料中碳原子含量为均匀分布或呈现沿侧墙的内侧向外侧方向递增的趋势。
可选的，对所述侧墙进行碳掺杂的工艺为原位掺杂或非原位掺杂。
可选的，当对所述侧墙进行碳掺杂的工艺为原位掺杂时，所述侧墙的形成步骤包括：形成覆盖所述栅极结构和半导体衬底的侧墙膜，所述侧墙膜的形成工艺为低压化学气相沉积、热原子层沉积或等离子体原子层沉积，且所述形成工艺的反应气体包括硅源气体、氮源气体和碳源气体；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙。
可选的，当对所述侧墙进行碳掺杂的工艺为非原位掺杂时，对所述侧墙进行碳掺杂的工艺步骤包括：形成覆盖所述栅极结构和半导体衬底的侧墙膜；对所述侧墙膜进行碳掺杂；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙。
可选的，当对所述侧墙进行碳掺杂的工艺为非原位掺杂时，对所述侧墙进行碳掺杂的工艺步骤包括：形成覆盖所述栅极结构和半导体衬底的侧墙膜；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙；对所述侧墙进行碳掺杂。
可选的，所述侧墙膜为单层结构或多层结构；所述侧墙膜为单层结构时，所述侧墙膜为氮化硅层；所述侧墙膜为多层结构时，所述侧墙膜为依次形成的氧化硅层和氮化硅层。
可选的，采用低压化学气相沉积、热原子层沉积或等离子体原子层沉积工艺形成所述侧墙膜。
可选的，所述碳掺杂的工艺为离子注入或等离子掺杂。
可选的，采用离子注入工艺进行所述碳掺杂的工艺参数为：注入能量为6kev至10kev，注入剂量为1E16atom/cm2至5E17atom/cm2。
可选的，在进行碳掺杂后，还包括步骤：对所述侧墙进行退火处理。
可选的，所述凹槽的形状为U形、方形或sigma形；当所述凹槽的形状为sigma形时，所述凹槽的形成步骤包括：以所述侧墙为掩膜，刻蚀栅极结构两侧的半导体衬底，在所述栅极结构两侧的半导体衬底内形成预凹槽；刻蚀所述预凹槽，在所述栅极结构两侧的半导体衬底内形成凹槽。
可选的，采用干法刻蚀工艺形成所述预凹槽。
可选的，刻蚀所述预凹槽的工艺为湿法刻蚀，所述湿法刻蚀的刻蚀液体为氨水或四甲基氢氨酸。
可选的，所述应力层的材料为SiGe、SiGeB、SiC或SiCP。
可选的，采用选择性外延工艺形成所述应力层。
可选的，所述应力层的材料为SiGe时，所述选择性外延工艺的工艺参数为：反应气体包括硅源气体、锗源气体、HCl和H2，所述硅源气体为SiH4或SiH2Cl2，所述锗源气体为GeH4，其中，硅源气体流量为1sccm至1000sccm，锗源气体流量为1sccm至1000sccm，HCl流量为1sccm至1000sccm，H2流量为100sccm至50000sccm，反应腔室压强为1托至500托，反应腔室温度为400度至900度。
可选的，形成的半导体器件为NMOS晶体管、PMOS晶体管或CMOS晶体管。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案中，在栅极结构两侧形成侧墙，且对所述侧墙进行了稳定性掺杂，提高侧墙的抗腐蚀能力；后续刻蚀栅极结构两侧的半导体衬底形成凹槽时，降低了所述刻蚀工艺对侧墙的刻蚀速率，避免由于刻蚀工艺刻蚀去除侧墙，暴露出栅极结构的侧壁；因此，所述侧墙受到刻蚀工艺的影响小，后续在凹槽内形成应力层时，栅极结构的侧壁均被侧墙所覆盖，从而防止在栅极结构的侧壁形成缺陷膜，提高半导体器件的可靠性，优化半导体器件的电学性能。
进一步，本发明实施例中，所述稳定性掺杂为对所述侧墙进行碳掺杂，由于碳原子本身具有较强的稳定性，对所述侧墙进行碳掺杂后，侧墙的稳定性得到提高，进而提高侧墙的抗腐蚀能力。
再进一步的，本发明实施例中，在对所述侧墙进行碳掺杂后，对所述侧墙进行退火处理，所述退火处理激活侧墙中的碳原子，在侧墙的材料中形成Si-C键；所述Si-C键的键能比Si-N键的键能大，因此Si-C键的热稳定性和化学稳定性优于Si-N键的热稳定性和化学稳定性；因此，在对所述侧墙进行退火处理后，侧墙的抗腐蚀能力得到进一步提高，从而进一步降低后续刻蚀工艺对侧墙的刻蚀速率。
更进一步的，本发明实施例中，形成覆盖栅极结构和半导体衬底的侧墙膜，对所述侧墙膜进行碳掺杂，回刻蚀所述侧墙膜在栅极结构两侧形成侧墙；本发明达到对侧墙进行碳掺杂的目的的同时，位于栅极结构两侧半导体衬底表面的侧墙膜阻挡碳原子进入半导体衬底内，从而避免后续刻蚀半导体衬底的工艺难度增加，本发明实施例减小了形成半导体器件的工艺难度。
附图说明
图1为一实施例形成半导体器件的流程示意图；
图2至图11为本发明第一实施例半导体器件形成过程的剖面结构示意图；
图12至图17为本发明第二实施例半导体器件形成过程的剖面结构示意图。
具体实施方式
由背景技术可知，现有技术制作的半导体器件存在电学性能差的问题。
针对半导体器件的形成方法进行研究，发现半导体器件的形成工艺包括以下步骤，请参考图1：步骤S1、提供半导体衬底，所述半导体衬底包括第一区域和第二区域，所述第一区域半导体衬底表面具有第一栅极结构，所述第二区域半导体衬底表面具有第二栅极结构；步骤S2、在所述半导体衬底表面形成侧墙，且所述侧墙分别位于第一栅极结构两侧和第二栅极结构两侧；步骤S3、形成覆盖所述第一栅极结构、第二栅极结构、侧墙和半导体衬底的掩膜层；步骤S4、在所述掩膜层表面形成图形化的光刻胶层，所述图形化的光刻胶层覆盖第一区域的掩膜层；步骤S5、以所述图形化的光刻胶层为掩膜，刻蚀去除第二区域的掩膜层；步骤S6、刻蚀所述第二栅极结构两侧的半导体衬底，在第二栅极结构两侧的半导体衬底内形成凹槽；步骤S7、形成填充满所述凹槽的应力层。
上述方法形成的半导体器件，在凹槽内形成应力层时，所述第二栅极结构顶部区域的侧壁也形成了缺陷膜（所述缺陷膜为形成在第二栅极结构顶部区域的侧壁的应力层材料）；更严重的，在所述第二栅极结构的第二栅电极层侧壁均形成了缺陷膜，所述缺陷膜的形成降低了半导体器件的可靠性，使得半导体器件的电学性能恶化。
针对半导体器件的形成工艺进行进一步研究发现，所述缺陷膜的形成主要是如下原因造成的：在形成应力层之前，第二栅极结构两侧的侧墙经历了多次刻蚀工艺，所述刻蚀工艺包括：刻蚀去除第二区域的掩膜层、以及刻蚀第二栅极结构两侧的半导体衬底形成凹槽，所述刻蚀工艺会对侧墙进行刻蚀。所述刻蚀工艺多为干法刻蚀工艺，干法刻蚀的刻蚀气体具有垂直于半导体衬底的方向，侧墙顶部区域受到刻蚀工艺的刻蚀损伤最大，极易导致第二栅极结构顶部区域的侧墙被刻蚀去除，暴露出第二栅电极层顶部区域的侧壁；严重的，当刻蚀工艺时间较长时，对所述侧墙进行较长时间的刻蚀，导致暴露出的第二栅电极层侧壁面积增大；若第二栅电极层具有暴露出的侧壁，则在后续采用选择性外延工艺形成所述应力层，且所述应力层的材料中含有较多的Si原子时，根据选择性外延工艺的选择特性，当所述第二栅电极层的材料为多晶硅或掺杂的多晶硅时，在形成应力层的同时，所述暴露出的第二栅电极层侧壁也将形成缺陷膜。
所述第二栅极结构侧壁的缺陷膜，严重影响半导体器件的电学性能，导致半导体器件的可靠性降低。
为此，本发明提高一种半导体器件的形成方法，对所述侧墙进行稳定性掺杂，提高侧墙抗腐蚀能力，避免暴露出栅极结构的侧壁，从而避免在栅极结构侧壁形成缺陷膜，提高半导体器件的可靠性和电学性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
本发明制作的半导体器件为NMOS晶体管、PMOS晶体管和CMOS晶体管，本发明实施例以制作的半导体器件为CMOS晶体管作示范性说明。本发明实施例对侧墙进行稳定性掺杂，提高所述侧墙抗腐蚀的能力。
第一实施例
图2至图11本发明第一实施例半导体器件制作过程的剖面结构示意图。
请参考图2，提供半导体衬底100，所述半导体衬底100表面具有栅极结构。
所述第一区域I为NMOS区域或PMOS区域，所述第二区域II为NMOS区域或PMOS区域。其中，当所述第一区域I为NMOS区域时，所述第二区域II为PMOS区域，当所述第一区域I为PMOS区域时，所述第二区域II为NMOS区域。在本发明的实施例中，以所述第一区域I为NMOS区域，第二区域II为PMOS区域做示范性说明。
还需要说明的是，所述第一区域I和第二区域II可以为相邻或间隔，不应过分限制本发明的保护范围。
本实施例中，以所述第一区域I为NMOS区域，所述第二区域II为PMOS区域，形成的半导体器件为CMOS晶体管作示范性说明。
所述半导体衬底100为单晶硅、多晶硅、非晶硅或绝缘体上的硅；所述半导体衬底100也可以为Si衬底、Ge衬底、SiGe衬底或GaAs衬底；所述半导体衬底100表面还可以形成若干外延界面层或应变层以提高半导体器件的电学性能。
本实施例中，所述半导体衬底100为Si衬底。
所述半导体衬底100内还可以形成有隔离结构101，所述隔离结构101可以为浅沟槽隔离结构，防止第一区域I和第二区域II之间发生电学连接。所述隔离结构101的填充材料为氧化硅、氮化硅或氮氧化硅中的一种或几种。
本实施例中，所述栅极结构包括位于第一区域I半导体衬底100表面的第一栅极结构110以及位于第二区域II半导体衬底100表面的第二栅极结构120。
所述第一栅极结构110包括位于第一区域I半导体衬底100表面的第一栅氧化层111、位于所述第一栅氧化层111表面的第一栅电极层112以及位于第一栅电极层112表面的第一顶部掩膜层113。
所述第二栅极结构120包括位于第二区域II半导体衬底100表面的第二栅氧化层121、位于所述第二栅氧化层121表面的第二栅电极层122以及位于第二栅电极层122表面的第二顶部掩膜层123。
所述第一栅氧化层111或第二栅氧化层121的材料为氧化硅或高k介质材料，所述第一栅电极层112或第二栅电极层122的材料为多晶硅、掺杂的多晶硅或金属。
所述第一顶部掩膜层113或第二顶部掩膜层123的材料为氮化硅，所述第一顶部掩膜层113或第二顶部掩膜层123可以作为后续形成凹槽的掩膜，保护第一栅电极层112或第二栅电极层122顶部不被后续的工艺所破坏。
本实施例中，所述第一栅氧化层111或第二栅氧化层121的材料为氧化硅，所述第一栅电极层112或第二栅电极层122的材料为多晶硅或掺杂的多晶硅。
请参考图3，形成覆盖所述第一栅极结构110、第二栅极结构120和半导体衬底100的侧墙膜102。
所述侧墙膜102用于后续形成位于第一栅极结构110和第二栅极结构120两侧的侧墙。
所述侧墙膜102为单层结构或多层结构。所述侧墙膜102为单层结构时，所述侧墙膜102为氮化硅层；所述侧墙膜102为多层结构时，所述侧墙膜102为依次形成的氧化硅层和氮化硅层。
本实施例以所述侧墙膜102为单层结构作示范性说明，所述侧墙膜102的材料为氮化硅，所述侧墙膜102的厚度为50埃至1000埃。
采用低压化学气相沉积、热原子层沉积或等离子体原子层沉积工艺形成所述侧墙膜102。
作为一个实施例，采用热原子层沉积工艺形成所述侧墙膜102，所述热原子层沉积的工艺参数为：反应气体包括硅源气体、氮源气体和N2，其中，硅源气体为SiH2Cl2或SiH4，氮源气体为NH3，沉积腔室温度为400度至600度，沉积腔室压强为0.1托至0.5托。
需要说明的是，在形成所述侧墙膜102之前，还可以在第一栅极结构110两侧的半导体衬底100内形成第一轻掺杂区，在第二栅极结构120两侧的半导体衬底100内形成第二轻掺杂区。所述第一轻掺杂区和第二轻掺杂区可以缓解热载流子效应。
请参考图4，对所述侧墙膜102进行稳定性掺杂130，提高所述侧墙膜102的抗腐蚀能力。
本实施例中，所述稳定性掺杂130为对所述侧墙膜102进行碳掺杂。
对所述侧墙膜102进行碳掺杂的目的在于：后续会回刻蚀所述侧墙膜102形成侧墙，因此，本实施例中对所述侧墙膜102进行碳掺杂，以达到对所述侧墙进行稳定性掺杂，提高所述侧墙的抗腐蚀能力的目的。
碳掺杂改善侧墙膜102的抗腐蚀能力的原因较为复杂，作为一种解释，所述碳掺杂改善侧墙膜102抗腐蚀能力的机理为：碳原子本身具有较高的稳定性，在侧墙膜102中进行碳掺杂后，所述碳原子具有的较高稳定性能够提高侧墙膜102的稳定性，提高侧墙膜102的热稳定性和化学稳定性，稳定性的提高有利于提高抗腐蚀能力；因此后续形成的侧墙的抗腐蚀能力也得到提高，降低侧墙被后续刻蚀工艺刻蚀的速率。
所述碳掺杂的工艺为离子注入或等离子掺杂。
本实施例中，采用离子注入工艺进行所述碳掺杂，所述离子注入的工艺参数为：注入能量为6kev至10kev，注入剂量为1E16atom/cm2至5E17atom/cm2。所述注入能量过小，碳离子被注入到侧墙膜102中的深度不够深；所述注入能量过大，碳离子注入深度过深，导致碳离子被注入到第一栅极结构110、第二栅极结构120或半导体衬底100内。所述注入剂量过小，可能会导致侧墙膜102中碳离子含量过少而不足以降低后续刻蚀工艺对侧墙的刻蚀速率；所述注入剂量过大会增加工艺成本，降低工艺效率。
本实施例中，在进行所述碳掺杂后，侧墙膜102的材料中碳原子的含量为0.5%至10%。
需要说明的是，所述侧墙膜102材料中的碳原子含量可以为均匀分布，也可以呈现沿侧墙膜102内侧向外侧方向递增的趋势。
当所述侧墙膜102材料中的碳原子含量呈现沿侧墙膜102的内侧向外侧方向递增趋势时，后续形成的侧墙材料中碳原子含量呈现沿侧墙内侧向外侧方向递增的趋势，碳原子含量越多的区域抗腐蚀能力越强，满足提高侧墙抗腐蚀能力的需求；且当侧墙膜102的材料中碳原子含量呈现递增趋势时，能够降低对侧墙膜102进行碳掺杂的工艺难度。
本实施例中，对所述侧墙膜102进行碳掺杂，第一栅极结构110两侧和第二栅极结构120两侧的半导体衬底100表面被所述侧墙膜102覆盖，避免所述碳掺杂的碳原子进入半导体衬底100内，从而避免在半导体衬底100内掺杂了碳原子后，防止由于半导体衬底100的抗腐蚀能力提高，造成后续刻蚀半导体衬底100形成凹槽的工艺难度增加。
在本发明其他实施例中，所述稳定性掺杂不限于碳掺杂，其他能提高侧墙膜热稳定性和化学稳定性的掺杂离子也可为稳定性掺杂的掺杂离子。
请参考图5，回刻蚀所述侧墙膜102（请参考图4），分别在第一栅极结构110和第二栅极结构120两侧形成侧墙103。
采用各向异性刻蚀工艺回刻蚀所述侧墙膜102。
作为一个实施例，所述各向异性刻蚀工艺为干法刻蚀，所述干法刻蚀工艺的工艺参数为：刻蚀气体包括CHF3、O2和Ar，CHF3流量为10sccm至100sccm，O2的流量为30sccm至50sccm，Ar的流量为50sccm至70sccm，反应腔室压强为0毫托至5毫托，源功率为200瓦至1000瓦，偏置电压为200V至1000V。
在所述侧墙103形成之后，还可以对所述侧墙103进行退火处理。所述退火处理激活侧墙103中的碳原子，在所述侧墙103内形成Si-C键；所述Si-C键的键能大于Si-N键的键能，因此所述Si-C键的热稳定性和化学稳定性优于Si-N键的热稳定性和化学稳定性，从而进一步提高侧墙103的抗腐蚀能力，进一步降低后续工艺刻蚀侧墙103的刻蚀速率。
需要说明的是，对所述侧墙进行碳掺杂的工艺为原位掺杂或非原位掺杂。在本实施例中，对所述侧墙103进行碳掺杂的工艺为非原位掺杂。
在本发明其他实施例中，当对所述侧墙进行碳掺杂的工艺为原位掺杂时，所述侧墙的形成步骤包括：形成覆盖所述第一栅极结构、第二栅极结构和半导体衬底的侧墙膜，所述侧墙膜的形成工艺为低压化学气相沉积、热原子层沉积或等离子体原子层沉积，且所述形成工艺的反应气体包括硅源气体、氮源气体和碳源气体，在形成侧墙膜的同时对所述侧墙膜进行原位碳掺杂；回刻蚀所述侧墙膜，分别在第一栅极结构和第二栅极结构两侧形成侧墙。
请参考图6，形成覆盖隔离结构101、半导体衬底100、侧墙103、第一栅极结构110和第二栅极结构120的掩膜层104。
所述掩膜层104的材料为氮化硅。
所述掩膜层104用于保护第一区域I的半导体衬底100和第一栅极结构110。
请参考图7，在所述第一区域I掩膜层104表面形成光刻胶层105，以所述光刻胶层105为掩膜，刻蚀去除位于第二区域II的掩膜层104。
所述光刻胶层105的形成步骤包括：形成覆盖所述掩膜层104的初始光刻胶层；对所述初始光刻胶层进行曝光显影，去除位于第二区域II掩膜层104表面的初始光刻胶层，形成位于第一区域I掩膜层104表面的光刻胶层105。
采用干法刻蚀工艺去除位于第二区域II的掩膜层104。
本实施例中，所述干法刻蚀工艺为反应离子刻蚀，所述反应离子刻蚀工艺的工艺参数为：反应气体包括CF4、CHF3和Ar，CF4流量为50sccm至100sccm，CHF3流量为10sccm至100sccm，Ar流量为100sccm至300sccm，源功率为50瓦至1000瓦，偏置功率为50瓦至250瓦，压强为50毫托至200毫托，腔室温度为20度至90度。
本实施例中，所述第二栅极结构120两侧的侧墙103的抗腐蚀能力得到提高，因此，所述刻蚀去除位于第二区域II的掩膜层105的工艺对侧墙103的刻蚀速率低，从而有利于降低刻蚀工艺中第二栅极结构120两侧侧墙103宽度的损失，避免暴露出第二栅电极层122的侧壁。
请参考图8，去除所述光刻胶层105（请参考图7）。
采用灰化工艺或湿法刻蚀工艺去除所述光刻胶层105。本实施例中，采用灰化工艺去除所述光刻胶层105，可以最大程度的减小去除光刻胶层105的工艺对侧墙103造成的损伤。
作为一个实施例，所述灰化工艺的工艺参数为：所述灰化工艺采用的气体为氧气，氧气流量为10sccm至1000sccm，反应温度为40度至250度。
请参考图9，以所述第二栅极结构120两侧的侧墙103为掩膜，刻蚀位于第二栅极结构120两侧的半导体衬底100，在所述半导体衬底100内形成第一预凹槽106。
在刻蚀位于第二栅极结构120两侧的半导体衬底100时，第一区域I的掩膜层104保护第一区域I半导体衬底100和第一栅极结构110不被所述刻蚀工艺所破坏。
采用干法刻蚀工艺形成所述第一预凹槽106。作为一个实施例，所述干法刻蚀工艺为等离子刻蚀，所述等离子刻蚀工艺的刻蚀气体包括SF6、CF4、C2F6、SiCl4或Cl2。
本实施例中，由于在形成侧墙103之前，对侧墙膜102（请参考图4）进行了碳掺杂，因此，形成的侧墙103的抗腐蚀能力增强；采用等离子刻蚀工艺刻蚀形成所述第一预凹槽106时，所述等离子刻蚀工艺对侧墙103的损伤小；因此，当第一预凹槽106形成后，所述第二栅极结构120的侧壁依然被侧墙103所覆盖，防止暴露出第二栅电极层122的侧壁。
请参考图10，刻蚀所述第一预凹槽106（请参考图9），在第二栅极结构120两侧的半导体衬底100内形成第一凹槽107。
本实施例中，所述第一凹槽107的形成为sigma（Σ）形。Σ形的第一凹槽107侧壁向器件沟道方向内凹，这种形状可以有效缩短器件沟道长度，满足器件尺寸小型化的要求；且Σ形的第一凹槽107具有在栅极间隙体下方较大下切的特点，这种形状第一凹槽107内形成应力材料可以对器件沟道区产生更大的应力。
采用湿法刻蚀工艺刻蚀所述第一预凹槽106，作为一个实施例，所述湿法刻蚀的刻蚀液体为氨水或四甲基氢氨酸。
由于采用氨水或四甲基氢铵溶液作为湿法刻蚀的刻蚀液体时，湿法刻蚀对晶面（100）的刻蚀速率比对晶面（111）的刻蚀速率大，因此当湿法刻蚀工艺完成后，形成Σ形的第一凹槽107。
本实施例中，第二栅极结构120两侧的侧墙103的稳定性高，所述侧墙103的抗腐蚀能力较强；因此，形成所述第一凹槽107的湿法刻蚀工艺对侧墙103的刻蚀速率小，所述湿法刻蚀工艺对侧墙103造成的损伤小；当第一凹槽107形成后，所述第二栅极结构120的侧壁依然被侧墙103覆盖，从而防止暴露出第二栅极结构120的侧壁。
需要说明的是，在本发明其他实施例中，所述第一凹槽的形状可以为方形或U形。当所述第一凹槽的形状为方形或U形时，采用干法刻蚀工艺对第二栅极结构两侧的半导体衬底进行刻蚀，在所述第二栅极结构两侧的半导体衬底内形成第一凹槽。
请参考图11，形成填充满所述第一凹槽107的第一应力层108。
本实施例以所述第一应力层108的顶部与半导体衬底100表面齐平做示范性说明。在本发明其他实施例中，为了向第二区域沟道区施加适当的应力作用，所述第一应力层的顶部也可以高于半导体衬底表面。
所述第一应力层108的材料为SiGe、SiGeB、SiC或SiCP。其中，当第二区域II为NMOS区域时，所述第一应力层108的材料为SiC或SiCP，所述第一应力层108为NMOS区域的沟道区提供拉应力作用，从而提高NMOS区域载流子迁移率；当第二区域II为PMOS区域时，所述第一应力层108的材料为SiGe或SiGeB，所述第一应力层108为PMOS区域的沟道区提供压应力作用。本实施例以第二区域为PMOS区域作示范性说明，所述第一应力层108的材料为SiGe或SiGeB。
采用选择性外延工艺形成所述第一应力层108。
作为一个实施例，所述第一应力层108的材料为SiGe，所述选择性外延工艺的工艺参数为：反应气体包括硅源气体、锗源气体、HCl和H2，所述硅源气体为SiH4或SiH2Cl2，所述锗源气体为GeH4，其中，硅源气体流量为1sccm至1000sccm，锗源气体流量为1sccm至1000sccm，HCl流量为1sccm至1000sccm，H2流量为100sccm至50000sccm，反应腔室压强为1托至500托，反应腔室温度为400度至900度。
在本发明其他实施例中，所述第一应力层的材料为SiGeB，则反应气体还包括硼源气体，硼源气体流量为1sccm至1000sccm，所述硼源气体为B2H6。
本实施例中，所述侧墙103的抗腐蚀能力高，因此所述侧墙103受到刻蚀工艺的影响较小；当采用选择性外延工艺形成所述第一应力层108时，所述侧墙103覆盖第二栅极结构120的侧壁，避免第二栅电极层122的侧壁暴露在选择性外延反应腔室中，从而防止在第二栅电极层122侧壁形成缺陷膜，进而提高半导体器件的可靠性，优化半导体器件的电学性能。
后续的工艺包括：在所述第一栅极结构110两侧的第一区域I半导体衬底100内形成第二凹槽，所述第二凹槽的形成过程可参考第一凹槽107的形成过程，在此不再赘述；形成填充满所述第二凹槽的第二应力层，所述第二应力层的材料为SiC或SiCP，所述第二应力层的形成工艺可参考第一应力层108的形成工艺，在此不再赘述；对所述第一应力层进行第一掺杂，形成第一掺杂区；对所述第二应力层进行第二掺杂，形成第二掺杂区；在所述第一应力层表面形成第一金属硅化物层，在所述第二应力层表面形成第二金属硅化物层。
由于对所述第一栅极结构110两侧的侧墙103也进行了碳掺杂，因此，第一栅极结构110两侧的侧墙103的抗腐蚀能力也得到提高；在所述第一栅极结构110两侧的半导体衬底100内形成第二应力层时，所述第一栅极结构110的侧壁被侧墙103覆盖，防止在第一栅极结构110顶部两侧形成缺陷膜，从而提高半导体器件的电学性能。
图12至图17为本发明第二实施例半导体器件制作过程的剖面结构示意图。
请参考图12，提供半导体衬底200，所述半导体衬底200具有第一区域I和第二区域II，所述第一区域I的半导体衬底200表面具有第一栅极结构210，所述第二区域II的半导体衬底200表面具有第二栅极结构220。
所述半导体衬底200、第一栅极结构210和第二栅极结构220的形成工艺和材料请参考本发明第一实施例半导体衬底100（请参考图2）、第一栅极结构120（请参考图2）和第二栅极结构120（请参考图2）的形成工艺和材料，在此不再赘述。
所述半导体衬底200内还可以形成有隔离结构201。
请参考图13，形成覆盖所述半导体衬底200、隔离结构201、第一栅极结构210和第二栅极结构220的侧墙膜202。
所述侧墙膜202的形成工艺和材料请参考本发明第一实施例提供的侧墙膜102（请参考图3）的形成工艺和材料，在此不再赘述。
本实施例中，所述侧墙膜202为单层结构，所述侧墙膜202的材料为氮化硅。
请参考图14，回刻蚀所述侧墙膜202（请参考图13），分别在第一栅极结构210和第二栅极结构220两侧形成侧墙203。
所述回刻蚀形成侧墙203的工艺请参考本发明第一实施例提供的回刻蚀形成侧墙103（请参考图5）的工艺，在此不再赘述。
请参考图15，对所述侧墙203进行碳掺杂230。
具体的，向所述半导体衬底200暴露的表面形成光刻胶层204，以所述光刻胶层204为掩膜，对所述侧墙203进行碳掺杂230。
在本发明其他实施例中，所述第一栅极结构包括第一栅氧化层和第一栅电极层，所述第二栅极结构包括第二栅氧化层和第二栅电极层，则所述光刻胶层还形成于第一栅极结构顶部和第二栅极结构顶部。
所述碳掺杂230的工艺为离子注入或等离子掺杂。
本实施例中，所述碳掺杂230的工艺为离子注入。作为一个实施例，所述离子注入的工艺参数为：注入能量为6kev至10kev，注入剂量为1E16atom/cm2至5E17atom/cm2。所述注入能量过小，则碳离子注入深度不够深；所述注入能量过大，碳离子注入深度过大造成碳离子注入至不期望区域。所述注入剂量过小，会导致不足以降低后续工艺对侧墙203的刻蚀速率；所述注入剂量过大，会增加工艺成本，降低生产效率。
在所述碳掺杂230工艺完成后，还可以对所述侧墙203进行退火处理。所述退火处理激活碳掺杂230所掺入的碳原子，在所述侧墙203的材料中形成Si-C键，所述Si-C键的键能大于Si-N键的键能，因此所述Si-C键的热稳定性和化学稳定性优于Si-N键的热稳定性和化学稳定性，从而进一步提高侧墙203的抗腐蚀能力，进一步降低后续工艺刻蚀侧墙203的刻蚀速率。
所述退火处理为尖峰退火或毫秒退火。所述退火处理为尖峰退火时，所述退火处理的工艺参数为：退火温度为800度至1000度，退火气体为氮气或氦气；所述退火处理为毫秒退火时，所述退火处理的工艺参数为：退火温度为1100度至1300度，退火时长为0.25毫秒至20毫秒。
请参考图16，去除所述光刻胶层204（请参考图15）。
本实施例中，采用灰化工艺去除所述光刻胶层204。作为一个实施例，所述灰化工艺的工艺参数为：反应气体包括O2，O2流量为100sccm至500sccm，反应腔室温度为450度至600度。
在本发明其他实施例中，也可以采用湿法刻蚀工艺去除所述光刻胶层204，由于对侧墙203进行了碳掺杂230（请参考图15），侧墙203的抗腐蚀能力得到提高；当采用湿法刻蚀工艺去除所述光刻胶层104时，所述湿法刻蚀工艺刻蚀侧墙203速率小。
请参考图17，在所述第二栅极结构220两侧的半导体衬底200内形成第一应力层208。
所述第一应力层208的形成步骤包括：刻蚀所述第二栅极结构220两侧的半导体衬底200，在所述第二栅极结构220两侧的半导体衬底200内形成凹槽；形成填充满所述凹槽的第一应力层208。形成所述第一应力层208的工艺步骤可参考本发明第一实施例图6至图11提供的工艺步骤，在此不再赘述。
本实施例中，所述侧墙203经过碳掺杂230后，所述侧墙203的抗腐蚀能力得到提高，第二栅极结构220的侧壁被侧墙203所覆盖，从而防止第二栅电极层222暴露在形成第一应力层208的选择性外延腔室内，避免在第二栅电极层侧壁形成缺陷膜，从而提高半导体器件的可靠性，优化半导体器件的电学性能。
综上，本发明提供的技术方案具有以下优点：
首先，本发明实施例中，对侧墙进行了稳定性掺杂，提高侧墙的抗腐蚀能力，从而降低了所述侧墙被后续工艺刻蚀的速率；本发明减少后续刻蚀工艺对侧墙造成的损伤，进而避免暴露出栅极结构的侧壁，防止后续形成应力层时，在暴露出的栅极结构侧壁形成缺陷膜，从而提高半导体器件的电学性能。
其次，本发明实施例中，形成覆盖所述栅极结构和半导体衬底的侧墙膜；对所述侧墙膜进行碳掺杂；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙；形成的侧墙的抗腐蚀能力得到提高，且在进行碳掺杂时，位于半导体衬底表面的侧墙膜阻挡碳原子进入半导体衬底内，避免半导体衬底的抗腐蚀能力也得到提高，从而降低后续刻蚀半导体衬底的工艺难度。
再次，本发明实施例中，在对所述侧墙进行碳掺杂后，对所述侧墙进行退火处理，使得碳原子与侧墙中的材料发生化学反应形成Si-C键，所述Si-C键的热稳定性和化学稳定性优于Si-N键的热稳定性和化学稳定性，从而进一步提高侧墙的抗腐蚀能力，进一步提高半导体器件的可靠性和电学性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体器件的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底表面具有栅极结构；
在所述半导体衬底表面形成侧墙，所述侧墙位于栅极结构两侧；
对所述侧墙进行稳定性掺杂，提高所述侧墙的抗腐蚀能力；
以所述侧墙为掩膜，刻蚀位于栅极结构两侧的半导体衬底，在所述栅极结构两侧的半导体衬底内形成凹槽；
形成填充满所述凹槽的应力层。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述稳定性掺杂为对所述侧墙进行碳掺杂。
3.根据权利要求2所述的半导体器件的形成方法，其特征在于，在进行所述碳掺杂后，所述侧墙的材料中碳原子含量为0.5%至10%。
4.根据权利要求3所述的半导体器件的形成方法，其特征在于，所述侧墙的材料中碳原子含量为均匀分布或呈现沿侧墙的内侧向外侧方向递增的趋势。
5.根据权利要求2所述的半导体器件的形成方法，其特征在于，对所述侧墙进行碳掺杂的工艺为原位掺杂或非原位掺杂。
6.根据权利要求5所述的半导体器件的形成方法，其特征在于，当对所述侧墙进行碳掺杂的工艺为原位掺杂时，所述侧墙的形成步骤包括：形成覆盖所述栅极结构和半导体衬底的侧墙膜，所述侧墙膜的形成工艺为低压化学气相沉积、热原子层沉积或等离子体原子层沉积，且所述形成工艺的反应气体包括硅源气体、氮源气体和碳源气体；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙。
7.根据权利要求5所述的半导体器件的形成方法，其特征在于，当对所述侧墙进行碳掺杂的工艺为非原位掺杂时，对所述侧墙进行碳掺杂的工艺步骤包括：形成覆盖所述栅极结构和半导体衬底的侧墙膜；对所述侧墙膜进行碳掺杂；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙。
8.根据权利要求5所述的半导体器件的形成方法，其特征在于，当对所述侧墙进行碳掺杂的工艺为非原位掺杂时，对所述侧墙进行碳掺杂的工艺步骤包括：形成覆盖所述栅极结构和半导体衬底的侧墙膜；回刻蚀所述侧墙膜，在栅极结构两侧形成侧墙；对所述侧墙进行碳掺杂。
9.根据权利要求7或8所述的半导体器件的形成方法，其特征在于，所述侧墙膜为单层结构或多层结构；所述侧墙膜为单层结构时，所述侧墙膜为氮化硅层；所述侧墙膜为多层结构时，所述侧墙膜为依次形成的氧化硅层和氮化硅层。
10.根据权利要求7或8所述的半导体器件的形成方法，其特征在于，采用低压化学气相沉积、热原子层沉积或等离子体原子层沉积工艺形成所述侧墙膜。
11.根据权利要求7或8所述的半导体器件的形成方法，其特征在于，所述碳掺杂的工艺为离子注入或等离子掺杂。
12.根据权利要求11所述的半导体器件的形成方法，其特征在于，采用离子注入工艺进行所述碳掺杂的工艺参数为：注入能量为6kev至10kev，注入剂量为1E16atom/cm2至5E17atom/cm2。
13.根据权利要求7或8所述的半导体器件的形成方法，其特征在于，在进行碳掺杂后，还包括步骤：对所述侧墙进行退火处理。
14.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述凹槽的形状为U形、方形或sigma形；当所述凹槽的形状为sigma形时，所述凹槽的形成步骤包括：以所述侧墙为掩膜，刻蚀栅极结构两侧的半导体衬底，在所述栅极结构两侧的半导体衬底内形成预凹槽；刻蚀所述预凹槽，在所述栅极结构两侧的半导体衬底内形成凹槽。
15.根据权利要求14所述的半导体器件的形成方法，其特征在于，采用干法刻蚀工艺形成所述预凹槽。
16.根据权利要求14所述的半导体器件的形成方法，其特征在于，刻蚀所述预凹槽的工艺为湿法刻蚀，所述湿法刻蚀的刻蚀液体为氨水或四甲基氢氨酸。
17.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述应力层的材料为SiGe、SiGeB、SiC或SiCP。
18.根据权利要求17所述的半导体器件的形成方法，其特征在于，采用选择性外延工艺形成所述应力层。
19.根据权利要求18所述的半导体器件的形成方法，其特征在于，所述应力层的材料为SiGe时，所述选择性外延工艺的工艺参数为：反应气体包括硅源气体、锗源气体、HCl和H2，所述硅源气体为SiH4或SiH2Cl2，所述锗源气体为GeH4，其中，硅源气体流量为1sccm至1000sccm，锗源气体流量为1sccm至1000sccm，HCl流量为1sccm至1000sccm，H2流量为100sccm至50000sccm，反应腔室压强为1托至500托，反应腔室温度为400度至900度。
20.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成的半导体器件为NMOS晶体管、PMOS晶体管或CMOS晶体管。
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