CN104576619B - 电子器件以及电子器件的制造方法 - Google Patents

电子器件以及电子器件的制造方法 Download PDF

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Publication number
CN104576619B
CN104576619B CN201410571817.4A CN201410571817A CN104576619B CN 104576619 B CN104576619 B CN 104576619B CN 201410571817 A CN201410571817 A CN 201410571817A CN 104576619 B CN104576619 B CN 104576619B
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semiconductor substrate
structural parts
metal structural
solder layer
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CN104576619A (zh
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岛拔康夫
福冈昌和
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Sumida Corp
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Sumida Corp
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Abstract

本发明提供一种能够简化半导体基板与引线端子板等的板状金属构件之间的连接装配，并且能够降低成本的电子器件以及电子器件的制造方法。上述电子器件具有：树脂制框架(19)；半导体基板(15)，其被收容于树脂制框架中；板状金属构件(14)，其位于与半导体基板相间隔的位置，其至少一端被固定在树脂制框架中；电气连接区域部(27)，其由导电性材料所形成，位于半导体基板的朝向板状金属构件的一侧的表面上；焊料层(28)，其形成于上述电气连接区域部的朝向上述板状金属构件的一侧的表面；板状金属构件借助焊料层以及电气连接区域部非接触地支撑半导体基板，并且，与电气连接区域部电气连接。

Description

电子器件以及电子器件的制造方法
技术领域
本发明涉及一种电子器件以及电子器件的制造方法，尤其涉及一种能够简化半导体基板，与如引线端子板等的板状金属构件之间的连接装配的电子器件以及电子器件的制造方法。
背景技术
作为这种电子器件，例如可以列举汽车用防盗器，其他还可列举进行儿童放学后的活动场所管理、家畜的饲养管理、进出车站的管理等的ID认证用天线部件等(例如可参照，专利文献1、专利文献2以及专利文献3)。
专利文献1中记载的电子器件为IC封装，是利用导线将半导体基板(IC芯片)和引线端子连接后，利用树脂将周围进行密封而形成的IC封装。
专利文献2中记载的电子器件是带有IC芯片的发射天线，其用于非钥匙操作的遥控车门开关系统中，对汽车车门进行锁定和解锁。
专利文献3中记载的电子器件，是被设置于回转寿司店的盘子中的电子标签。
然而，这样的电子器件，通常是由被动元件、半导体基板构成的IC芯片以及用于设置上述被动元件和IC芯片的基座构件等构成。
如上所述的IC封装由被密封在封装外壳内的半导体基板(IC芯片)、从封装外壳内引出的具有引线的引线框架、设置在封装外壳内的半导体基板上的导电图形(Land)以及连接它们和引线框架之间的键合金线(bonding wire)而构成。
然而，在以往的IC封装等电子器件中，由于在引线框架和半导体基板的图形之间设置键合金线(bonding wire)，所以导致存在制造成本非常高、制造工时数多且操作性差的问题。
现有技术
专利文献
专利文献1：日本专利申请公开公报特开昭63-208236号(参照图1)
专利文献1：日本语国际申请再公表特许公报WO2011/024559号
专利文献3：日本专利申请公开公报特开2001-184471号
发明内容
发明要解决的技术问题
此处，本发明是鉴于上述存在的问题而完成的，其目的在于提供一种能够简化半导体基板，与如引线端子板等的板状金属构件之间的连接装配，并且能够降低成本的电子器件和电子器件的制造方法。
解决技术问题的技术手段
本发明是为了达成上述目的所提出的，本发明所涉及的实施方式通过以下所示的构成得以实现。
(1)本发明所涉及的第1种实施方式为一种电子器件，其特征在于具有：树脂制框架；半导体基板，其被收容于树脂制框架中；板状金属构件，其位于与半导体基板相间隔的位置，且至少一端被固定在树脂制框架中；电气连接区域部，其位于半导体基板的朝向板状金属构件的一侧的表面上，由导电性材料所形成；焊料层，其由导电性材料所形成，位于半导体基板的朝向板状金属构件的一侧的表面上；板状金属构件借助焊料层以及电气连接区域部非接触地支撑半导体基板，并且，与上述电气连接区域部电气连接。
(2)上述(1)所记载的电子器件中，板状金属构件能够具有弯曲部，其在与焊料层相连接的区域突出向焊料层。
(3)上述(1)或(2)所记载的电子器件中，树脂制框架能够具有收容半导体基板的中空部，板状金属构件在中空部内与半导体基板电气连接。
(4)上述(1)～(3)中任意一项所记载的电子器件中，板状金属构件的一端能够被埋设在树脂制框架内从而被固定，其另一端能够为开放，或者被埋设在树脂制框架内从而被固定。
(5)上述(1)～(4)中任意一项所记载的电子器件中，板状金属构件能够含有具有50HV以上300HV以下的维氏硬度的铜合金或者不锈钢。
(6)上述(3)～(5)中任意一项所记载的电子器件中，树脂制框架能够具有延伸到中空部的突出部，突出部具有与半导体的至少一处相接触的接触部，用于定位半导体基板。
(7)本发明所涉及的第2种实施方式为一种电子器件的制造方法，其特征在于具有下述工序：嵌件成型工序，将板状金属构件定位于模具内，向模具内射出注入树脂，形成为板状金属构件的至少一端被埋设的树脂制框架的嵌件成型工序；半导体基板准备工序，按照先在半导体基板的表面上由导电性材料形成电气连接区域，然后形成焊料层的顺序准备半导体基板的半导体基板准备工序；半导体基板载置工序，使半导体基板的具有焊料层的面向下，为了使焊料层和板状金属构件的一部分相接触，依靠半导体基板的自重将其载置于板状金属构件上的半导体基板载置工序；回流焊接工序，对焊料层加热使焊料层熔化，并使半导体基板和板状金属构件电气连接的回流焊接工序。
发明效果
根据本发明，能够提供一种简化了半导体基板与引线端子板等的板状金属构件之间的连接装配、并且能够降低成本的电子器件以及电子器件的制造方法。
附图说明
图1表示的是本发明的电子器件的实施方式的天线单元的立体图(从天线单元的顶端所观察的)。
图2表示的是说明构成图1的天线单元的仰视图(从天线单元的底端所观察的)。
图3表示的是图2中A-A线的扩大剖视图。
图4表示的是说明图1的天线单元的中空部内的构造和被收容于中空部内的半导体基板的构成的分解立体图。
图5表示的是说明本发明的电子器件的制造方法的一个例子的流程图。
图6表示的是说明本实施方式中的焊锡连接的示意图，其中，图6的(a)所示的回流焊接前的状态图，图6的(b)所示的回流焊接后的状态图。
图7表示的是说明本发明的电子器件的第1变形例的示意图，其中图7的(a)表示的是说明树脂制框架的构成示意图，图7的(b)表示的是说明半导体基板的背面的构成示意图。
图8表示的是说明本发明的电子器件的第2变形例的示意图，其中图8的(a)表示的是说明树脂制框架的构成示意图，图8的(b)表示的是说明半导体基板的背面的构成示意图。
图9表示的是说明本发明的电子器件的树脂制框架的中空部的第3变形例的示意图。
图10表示的是本发明的电子器件中的板状金属构件的弯曲部的多个变形例的示意图，其中图10的(a)是第4变形例的示意图，图10的(b)是第5变形例的示意图，图10的(c)是第6变形例的示意图，图10的(d)是第7变形例的示意图。
具体实施方式
以下，参照附图，对本发明所涉及的电子器件的实施方式进行详细说明。此外，本发明并不局限于这些实施方式。
图1～图4所表示的是本发明的电子器件的实施方式的示意图，以天线单元11作为电子器件一个例子进行说明。如图1和图2所示，天线单元11具有：单元主体12；安装于该单元主体12上的天线线圈13；半导体基板15；与半导体基板15相间隔的一对板状金属构件14、14以及安装板16等。
天线线圈13由棒状铁芯17和线圈18所构成，其中棒状铁芯17由铁氧体和金属材料等构成，线圈18是在该棒状铁芯17的外周表面借助绝缘片(图中未示出)将绕组按照预定的匝数卷绕所形成的。线圈18上设置有来自绕组的引线18a和18b。
单元主体12具有树脂制框架19，上述树脂制框架19是通过将树脂材料射出注入至模具(图中未示出)中，从而形成预定形状的树脂制框架。此外，在形成树脂制框架19时，将一对板状金属构件14、14以及安装板16分别配置于模具内的预定位置，并在该状态下将树脂射出注入至模具中，从而将板状金属构件14、14以及安装板16埋设于树脂内，即进行了所谓的嵌件成型，使树脂制框架19与一对板状金属构件14、14以及安装板16形成一体化。
该各板状金属构件14具有作为引线端子板的功能，其是通过对铜合金或者不锈钢等具有一定程度的强度以及硬度的金属板材进行冲压而形成的。此外，在本实施方式中，从制造的便利性以及降低成本的观点考虑，形成板状金属构件14的材料优选与半导体基板15中使用的引线框架相同的材料。尤其是，该板状金属构件14起到如后所述的支撑半导体基板15的作用，所以优选具有预定硬度的金属材料，在本实施方式中所使用的板状金属构件14的硬度在维氏硬度50HV以上300HV以下。
如图1以及图2所示，板状金属构件14、14的各一端侧具有作为接线端子的14a、14a，它们从树脂制框架19的一个侧面19a向外部突出。天线线圈13中的线圈18的引线18a，18b分别被缠绕在每一个接线端子14a、14a处，从而形成电气以及机械连接。此外，通过将天线线圈13的棒状铁芯17的一端侧固定在树脂制框架19的前面19b上，从而得以安装天线线圈13的棒状铁芯17。
此外，如图2所示，在树脂制框架19的背面(下面19c)一侧形成有中空部21，中空部21具有开口20。该中空部21如图2～图4所表示的那样，能够收容被配置为平面形状的半导体基板15。因此，本实施方式的中空部21的开口20形成为，大小与四角形的半导体基板15的面积几乎相同，深度为比半导体基板15的厚度深的凹陷部。
另外，如图4所示，在中空部21的底面21a上，有两个被分别贯穿设置了两块板状金属构件14、14的内侧面21b、21c，其中，在设置板状金属构件14、14的接线端子14a、14a的一侧的内侧面21b的两个角部，分别设置了自底面21a向开口20方向突出的底座22，以及在底座22上一体形成的突出部23。此外，如图3所示，在本实施方式中，突出部23的上表面23a至开口20的距离S1形成为与半导体基板15的厚度t0(该厚度t0，不包括后述的焊盘27以及焊料层28的厚度)大致相同。此外，中空部21并非必须形成为具有底面21a的有底状，也可以形成作为贯穿上下方向的孔。
在中空部21内分别与底座22、22相对应的位置，板状金属构件14、14的中间部分14c、14c被配置为沿左右方向横穿过中空部21的内部，并且，将接线端子14a、14a的相反侧的另一端14b、14b配置为埋设在树脂制框架19中的状态。此外，如图2以及图3所示，在被配置于中空部21内的中间部分14c、14c的，与突出部23保持间距的另一端14b、14b一侧形成弯曲部24，上述弯曲部24在向着半导体基板15被收容的方向，即，在本实施方式中，向着开口20一侧的方向突出形成横截面为倒V字状。此外，如图4所示，从弯曲部24的顶点24a至开口20的距离S2形成为略厚于图6的(a)所示的半导体基板15的厚度t1(该厚度t1是半导体基板15的厚度t0加焊盘27的厚度)。此处所显示的是将板状金属构件14的另一端14b、14b埋设在树脂制框架19中的方式，但并不局限于此，如后所述的第1变形例，也可以仅将板状金属构件14的一端14a、14a一端固定，而使另一端14b、14b一侧为开放状态，即，也可以是作为自由端的悬臂状。
安装板16用于下述情况，即，例如在采用遥控车门开关系统而非钥匙进行车门锁定和解锁的汽车中，安装板16用于将天线单元11安装于门把手内，如图1以及图2所示，安装板16的一端侧被埋设在树脂制框架19内从而被安装，在从树脂制框架19的后面19c引导出的另一端上，设置了插入安装螺丝(图中未示出)的安装孔25和安装孔26等。
在本实施方式中，半导体基板15是由单晶体或者多晶体Si基板、SiC基板以及GaN基板等半导体材料所构成，在其内部形成多层的集成电路。此外，如图2～图5所示，在被安装为朝向中空部21的底面21a的面(下表面15a)的一侧形成有一对焊盘27、27，上述焊盘用作电气连接区域部，它们分别形成为与板状金属构件14、14的弯曲部24相对应。上述一对焊盘27、27一般由能够导电的导电材料形成，上述导电材料由与半导体及金属都具有良好兼容性的合金或者化合物所形成。此外，在焊盘27、27的表面上有以锡为主要成分所形成的膏状焊料层。另外，此处为了避免发生半导体基板15被板状金属构件14所擦伤，优选焊料层28的高度h1为焊盘27的高度的5倍以上20倍以下。在本实施方式中，焊盘27的高度大约为0.008mm，焊盘27加上焊料层28的高度为0.06mm以上0.10mm以下。
而且，使半导体基板15的具有焊盘27的面(下表面15a)向下落入树脂制框架19的中空部21内，在中空部21内以埋设的状态被收容，上述焊盘27上设置有焊料层28。于是，焊料层28以及焊盘27与板状金属构件14、14的弯曲部24、24分别相对应，并且中空部21内的突出部23、23与半导体基板15的下表面15a相抵接。而且，半导体基板15被中空部21内的板状金属构件14、14的弯曲部24、24和突出部23、23以非常小的作用力(相当于半导体基板的自重)所支撑。此外，在该状态下，将天线单元11放入回流炉中(图中未示出)，通过施加热空气使焊料层28熔化，随后再冷却和凝固焊料层28，使半导体基板15和板状金属构件14形成一体化。
此外，在回流焊接前，依靠半导体基板15的自重，板状金属构件14能够进入至焊料层28中，但由于半导体基板15的重量轻，所以如图6的(b)所示，板状金属构件14的弯曲部24进入至焊料层28中但没有接触焊盘27，此外，如图6的(b)所示，焊盘27和弯曲部24之间在回流焊接处理后也不接触，即，未直接接触的状态。也就是说，在回流焊接时，焊料层28的焊锡熔化，但由于半导体基板的重量轻，所以板状金属构件14的弯曲部24没有戳破焊料层28直接与焊盘27相接触。此时，板状金属构件14也没有与半导体基板15的表面相接触。此外，除了如图6的(b)所示的方式以外，例如还可以为如下变形，即，板状金属构件14戳破焊料层28，但以不戳破焊盘27的程度与焊盘27相接触。也就是说，在不对半导体基板15与板状金属构件14造成破坏的范围内，可用进行各种变形。
此外，虽然图中没有示出，但天线单元11是以下述方式所形成的，即，安装板16的安装部分以外的全体被树脂密封而完成。
图5是用流程图来显示天线单元11的制造过程的一个例子。利用图5对天线单元的制造过程按照(1)～(5)的顺序进行说明。
(1)在嵌件成型工序中，首先，将一对板状金属构件14、14和安装板16分别配置在模具内的预定位置，然后，在该状态下向模具内射出注入树脂材料，以便将板状金属构件14、14和安装板16埋设在树脂内，即进行所谓的嵌件成型从而形成树脂制框架19。
(2)在半导体基板准备工序中，首先，使用导电性材料在半导体基板15的表面(下表面15a)形成作为电气连接区域部的焊盘27，然后，在该焊盘27的表面上设置以锡为主要成分的膏状焊料层28。
(3)在半导体基板的载置工序中，首先使具有焊料层28的面向下，为了使该焊料层28和弯曲部24的顶点24a相接触，半导体基板15依靠其自重落入中空部21中，从而，使半导体基板15载置于板状金属构件14上，上述弯曲部24是板状金属构件14的一部分。据此，通过半导体基板15的自重，使板状金属构件14的弯曲部24进入至焊料层28中，但由于半导体基板15的重量较轻，所以板状金属构件14的弯曲部24没有直接与焊盘27乃至半导体基板15的表面相接触。图6的(a)所表示的是该回流焊接之前的状态。此外，如果先对板状金属构件14的弯曲部24进行熔剂处理，然后再载置半导体基板，则能够形成更可靠的的连接。
(4)在回流焊接工序中，首先将天线单元11放入回流炉中，通过施加热空气使焊料层28熔化，从而使半导体基板15和板状金属部件14形成一体化。此时，焊料层28的焊锡熔化，流入到板状金属构件14的弯曲部24的周围，并且板状金属构件14的弯曲部24的凹陷部也浸入熔化的焊锡中。图6的(a)所表示的是该回流焊接处理之前的状态，图6的(b)所表示的是该回流焊接处理之后的状态。此外，回流焊接处理除了可以放入至回流炉中以外，也可以使用点回流装置，或者使用激光对焊料层28进行熔化处理。
(5)在密封工序中，利用树脂将除安装板16的安装部分以外的几乎整个天线单元11密封，从而形成天线单元11。另外，图1～图3中所示出的天线单元11是被树脂密封之前的状态。也就是说，天线单元11在没有被密封的情况下也可以使用。
因此，按如上所述的方法形成的电子器件的天线单元11，当组装板状金属构件14和半导体基板15时，板状金属构件14借助焊料层28支撑半导体基板15，焊料层28被设置在焊盘27的表面上，焊盘27是形成于半导体基板15的表面上的电气连接区域部，在该状态下，使焊料层28熔化时，熔化的焊料层的一部分流入至板状金属构件14和焊盘27之间，使得板状金属构件14与半导体基板15之间形成电气连接。此外，随后，冷却和凝固焊料层28时，能够容易获得板状金属构件14和焊盘27相互之间电气且机械地被固定的电子器件。
此外，在板状金属构件14的与半导体基板15的焊料层28相连接的区域，由于设置有突出向焊料层28弯曲的弯曲部24，所以在将半导体基板15配置于中空部21内时，弯曲部24的一部分易于浸入焊料层28内。此外，当焊料层28熔化时，焊料层28进入到突出的弯曲部24的周围，该熔化的焊锡流入弯曲部的周边，从而能够实现板状金属构件14和半导体基板15之间的稳定的电气连接和固定。
此外，由于树脂制框架19具有收容半导体基板15的中空部21，半导体基板15在被收容的中空部21内与板状金属构件14形成电气连接，所以相对于树脂制框架19，易于将半导体基板15进行定位，从而板状金属构件14和半导体基板15之间能够稳定地进行电气连接以及固定。
此外，本发明在按照如图7所示的变形后也能够实施。图7中示出的第1变形例用图7的(a)所表示，其为一种如下的构造，即，板状金属构件14为各两块，且自中空部21的左右内侧面21b、21c伸出形成共计4根的悬臂。此外，在延伸至中空部21内的4块板状金属构件14的自由端一侧分别设置了向着半导体基板15被收容的方向，即，向着开口20一侧(后述的半导体层)突出，弯曲形成截面为逆V字形的弯曲部24。此外，从弯曲部24的顶点24a到开口20的距离S2形成为比半导体基板15的厚度t1稍大。
另一方面，如图7的(b)所示，在被收容到中空部21内的半导体基板15的对应于4块板状金属构件14的弯曲部24的位置，分别设置了具有焊料层28的焊盘27。
而且，在该变形例中，使半导体基板15的设置了具有焊接层28的焊盘27的面(下表面15)向下，依靠其自重的落入树脂制框架19的中空部21内，以埋设在中空部21内的状态被收容。于是，焊料层28以及焊盘27分别与板状金属构件14的弯曲部24相对应，弯曲部24通过焊料层28以及焊盘27与半导体基板15的下表面15a相抵接。而且，在中空部21内，半导体基板15被4块板状金属14的弯曲部所支撑。此外，在该状态下，将天线单元11放入回流炉(图中未示出)中，施加热空气使焊料层28熔化，随后，通过使其冷却焊料层28凝固，从而半导体基板15和板状金属构件14被电气且机械地固定。
在该变形例中，省略了设置在上述实施方式中的底座22以及突出部23，通过分别设置在4块板状金属构件14上的弯曲部24支撑半导体基板15从而能够进行电气且机械地固定。此外，将2块板状金属构件14与线圈18的引线18a、18b相连接，将剩余的2块板状金属构件14与其它的电路相连接后也可以使用。
此外，本发明在按照如图8所示的变形后也能够实施。图8所示出的第2变形例如图8的(a)所示，在由中空部21的对角线所连接的2个角部，分别设置从底面21a向开口20突出的底座22，以及一体设置的形成于底座22上的突出部23。在该情况下，突出部23的上表面23a到开口20的距离S2形成为与半导体基板15的厚度t0略相同。进一步，在设置底座22的位置，板状金属构件14、14的中间部分14c、14c分别沿左右方向横穿过中空部21的内部，并且，接线端子14a、14a的相反侧的另一端14b、14b的一侧被配置为埋设在树脂制框架19中的状态。此外，在中空部21内所设置的中间部分14c、14c处形成有弯曲部24，上述弯曲部24的截面形成为逆V字状，向着半导体基板15被收容的方向，即，向本实施方式中的开口20一侧(换言之，半导体基板15的焊料层28侧)突出而形成。上述弯曲部24分别被设置在与底座22间隔预定距离的相互对称的位置。此外，从弯曲部24的顶点24a到开口20的面的距离S2形成为比半导体基板15的厚度略大。
另一方面，如图8的(b)所示，在被收容到中空部21内的半导体基板15的对应于2块板状金属构件14的弯曲部24的位置，设置了具有焊料层28的焊盘27。
而且，在该变形例中也使半导体基板15的设置了具有焊接层28的焊盘27的面(下表面15)向下，以其自重落入树脂制框架19的中空部21内，以埋设在中空部21内的状态被收容。于是，焊料层28以及焊盘27分别与板状金属构件14的弯曲部24相对应，并且，中空部21内的突出部23、23与半导体基板15的下表面15a相抵接。而且，在中空部21内，半导体基板15分别被2块板状金属构件14的弯曲部24和2个底座22上的突出部23同时支撑。此外，在该状态下，将天线单元11放入回流炉(图中未示出)中，施加热空气使焊料层28熔化，然后，使其冷却时，焊料层28凝固，从而，半导体基板15和板状金属构件14被电气且机械地固定。
图9所显示的是中空部21的第3变形例的示意图。图2～图8所示的内容公开了中空部21的一种结构，即，四个内侧面连续不间断地形成凹槽，而图9中所示出的中空部21为下述构造，即，在一个内侧面，设置有通向外侧面的切口部29。在这样的构造中，即使在中空部21的开口20的大小小于半导体基板15的面积的情况时，可以通过该切口部29扩大开口20，所以能够吸收与半导体基板的误差等。此外，还能够吸收半导体基板15和树脂制框架19的热膨胀。
图10所显示的是设置于板状金属构件14的弯曲部24的多个变形例的示意图。
图10的(a)所示是第4变形例的弯曲部24，在该变形例中，其形成为以下的结构，即，形成弯曲部24的V字形的顶部24b形成为平面状，并且该顶部24b与焊料层28的表面相搭接(搭焊)。在该形状中，能够调整弯曲部24浸入焊料层28的时间，使浸入的时间被延缓。
图10的(b)所示的是第5变形例的弯曲部24，它是图10的(a)所示的第4变形例的弯曲部24的变形产物，是在顶部24b设置了上下方向的贯通孔30而形成的。在该形状中，熔化的焊料层28能够进入到贯通孔30中，能够与弯曲部24形成一体化。
图10的(c)所示的是第6变形例中的弯曲部24，它也是图10的(a)所示的第4变形例的弯曲部24的变形产物，是在顶部24b设置了上下方向贯通的缺口部31而形成的。在该形状中，熔化的焊料层28能够进入到缺口部31中，能够与弯曲部24形成一体化。
图10的(d)所示的是第7变形例中的弯曲部24，其形成为弓状的弯曲面，焊料层28能够与该弯曲面相搭接(搭焊)。在该形状中，能够调整弯曲部24浸入焊料层28的时间，使浸入的时间被延缓。
此外，作为另一个变形例，实施方式中公开了在回流焊接处理中，弯曲部24在熔化的焊料层28内，依靠半导体基板15的自重浸入，从而进行连接，但相反，也可以利用树脂制框架19的自重进行连接。此外，半导体基板15和板状金属构件14也可以采用倒装芯片(Flip－Chip)等方法进行连接。在这种情况下，有必要在板状金属构件14上实施特殊电镀，例如，通过Au和Cu等预先实施厚膜电镀。
根据以上的实施方式所涉及的电子器件，当组装板状金属构件和半导体基板时，板状金属构件借助焊料层支撑半导体基板，焊料层被设置在焊盘的表面上，焊盘为形成于半导体基板的表面上的电气连接区域部，在该状态下，使焊料层熔化。于是，熔化的焊料层的一部分流入至板状金属构件和焊盘之间，从而使得板状金属构件与半导体基板之间形成电气连接。此外，随后，使焊料层凝固时，能够容易获得板状金属构件和电气连接区域部相互之间形成电气以及机械连接的电子器件。
在板状金属构件设置弯曲部的情况下，当焊料层熔化时，向着焊料层突出的弯曲部进入焊料层内，该熔化的焊料流入弯曲部的周边，此外，在焊料层凝固后，可以实现板状金属构件和半导体基板之间的稳定的电气连接以及固定。
在树脂制框架具有收容半导体基板的中空部的情况下，当将半导体基板收容配置于树脂制框架的中空部内时，半导体基板被定位于树脂制框架，从而，板状金属构件和半导体基板之间能够稳定地进行电气连接以及固定。板状金属构件的一端被埋设在树脂制框架内从而被固定，另一端根据该电子器件的设置场所和用途，可以选择为开放，也可以选择为被埋设在树脂制框架内而被固定。当将另一端作为自由端处于开放情况下，将该电子器件搭载至汽车等上时，能够缓和因车体等的震动所产生的应力。
在板状金属构件含有铜合金或者不锈钢，且维氏硬度在50HV以上300HV以下的情况下，通过使用这样的板状金属构件支撑半导体基板，使得板状金属构件能够稳定地支撑半导体基板。从而，板状金属构件和半导体基板之间能够稳定地进行电气连接以及固定。
在树脂制框架具有从中空部延伸出来的突出部的情况下，定位接触部和板状金属构件能够稳定地支撑被收容配置于中空部内的半导体基板，并且，板状金属构件和半导体基板之间能够稳定地进行电气连接以及机械固定。
根据以上的实施方式所涉及的电子器件的制造方法，在嵌件成型工序中，形成为板状金属构件的一端被埋设的树脂制框架，在半导体基板准备工序中，准备了如下所述的半导体基板，即，半导体基板的表面具有电气连接区域，并且在该电气连接区域部的表面具有焊料层，在半导体基板载置工序中，使半导体基板的具有焊料层的面向下，为了使焊料层和板状金属构件的一部分相接触，依靠半导体基板的自重将其载置于板状金属构件上的半导体基板载置工序，继而，在回流焊接工序中，当将焊料层加热熔化时，半导体基板由于自重向下运动，同时熔化的焊料的一部分流入至板状金属构件和电气连接区域部之间，从而使板状金属构件和半导体的电气连接区域部之间形成电气连接。此外，随后，当使焊料层凝固时，能够容易获得板状金属构件和电气连接区域部相互之间形成电气以及机械连接的电子器件。
符号说明
11 天线单元(电子器件)
12 单元主体
13 天线线圈
14 板状金属构件
14a 接线端子(板状金属构件的一端侧)
14b 另一端侧
14c 中间部分
15 半导体基板
15a 下表面
16 安装板
17 棒状铁芯
18 线圈
18a、18b 引线
19 树脂制框架
19a 侧面
19b 前面
19c 下表面
20 开口
21 中空部
21a 底面
21b 内侧面
22 底座
23 突出部
23a 突出部的上表面(接触部)
24 弯曲部
24a 顶点
24b 顶部
25、26 安装孔
27 焊盘(电气连接区域部)
28 焊料层
29 缺口部
30 贯通孔
31 缺口部
S1 距离
S2 距离
t0、t1 半导体基板的厚度
h 焊料层的高度

Claims (7)

1.一种电子器件，其特征在于具有：
树脂制框架，其具有中空部；
半导体基板，其被收容于上述树脂制框架的中空部中；
板状金属构件，其位于与上述半导体基板相间隔的位置，且至少一端被埋设从而固定在上述树脂制框架中；
电气连接区域部，其由导电性材料所形成，位于半导体基板的朝向板状金属构件的一侧的表面上；
焊料层，其形成于上述电气连接区域部的朝向上述板状金属构件的一侧的表面；
上述中空部具有开口，
在上述中空部中，以所述开口被堵塞的方式，而收纳有所述半导体基板，
在上述中空部内，上述板状金属构件借助上述焊料层以及上述电气连接区域部非接触地支撑上述半导体基板，并且，与上述电气连接区域部电气连接，
并且，所述板状金属构件的与所述焊料层连接的区域处于，不与形成所述中空部的面接触的状态。
2.根据权利要求1所述的电子器件，其特征在于，
上述板状金属构件在与上述焊料层相连接的区域具有突出向上述焊料层的弯曲部。
3.根据权利要求1所述的电子器件，其特征在于，
上述板状金属构件的一端被埋设在上述树脂制框架内从而被固定，其另一端被开放，或者被埋设在上述树脂制框架内从而被固定。
4.根据权利要求2所述的电子器件，其特征在于，
上述板状金属构件的一端被埋设在上述树脂制框架内从而被固定，其另一端被开放，或者被埋设在上述树脂制框架内从而被固定。
5.根据权利要求1至4中任一权利要求所述的电子器件，其特征在于，
上述板状金属构件含有具有50HV以上300HV以下的维氏硬度的铜合金或者不锈钢。
6.根据权利要求1至4中任一权利要求所述的电子器件，其特征在于，
上述树脂制框架具有延伸至上述中空部的突出部，上述突出部具有与上述半导体的至少一处相接触的接触部，用于定位上述半导体基板。
7.一种权利要求1至6中任一项所述的电子器件的制造方法，其特征在于具有下述工序，
嵌件成型工序，将板状金属构件定位于模具内，并向模具内射出注入树脂，形成上述板状金属构件的至少一端被埋设的树脂制框架的嵌件成型工序；
半导体基板准备工序，按照先在半导体基板的表面上由导电性材料形成电气连接区域，再形成焊料层的顺序准备半导体基板的半导体基板准备工序；
半导体基板载置工序，使上述半导体基板的具有上述焊料层的面向下，为了使上述焊料层和上述板状金属构件的一部分相接触，依靠上述半导体基板的自重将其载置于上述板状金属构件上的半导体基板载置工序；
回流焊接工序，对上述焊料层加热使上述焊料层熔化，并使上述半导体基板和上述板状金属构件电气连接的回流焊接工序。
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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
JP6201626B2 (ja) * 2013-10-23 2017-09-27 スミダコーポレーション株式会社 電子部品及び電子部品の製造方法
DE102013225905A1 (de) * 2013-12-13 2015-06-18 Bayerische Motoren Werke Aktiengesellschaft Anordnung aus einem Rahmenelement und einem Verbindungselement sowie Verfahren zur Befestigung einesVerbindungselementes an einem Rahmenelement
JP6515642B2 (ja) 2015-04-02 2019-05-22 スミダコーポレーション株式会社 コイル部品の製造方法およびコイル部品の製造に用いられる治具
US11081926B2 (en) 2016-09-01 2021-08-03 Sunonwealth Electric Machine Industry Co., Ltd. Inner-rotor motor and stator thereof
CN106298685B (zh) * 2016-09-29 2019-01-04 中国船舶重工集团公司第七一九研究所 一种采用超声波焊接的电子芯片封装结构
WO2019082343A1 (ja) * 2017-10-26 2019-05-02 新電元工業株式会社 半導体装置
CN112885744B (zh) * 2021-01-18 2022-12-23 深圳市华星光电半导体显示技术有限公司 用于smt工艺的固晶机

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101026110A (zh) * 2006-02-22 2007-08-29 三洋电机株式会社 电路装置的制造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024077A (zh) * 1973-07-05 1975-03-14
JPH0644585B2 (ja) 1987-02-25 1994-06-08 株式会社日立製作所 絶縁被覆ワイヤのワイヤボンデイング方法
JPH05218222A (ja) * 1992-02-03 1993-08-27 Toshiba Corp 樹脂封止型高周波用半導体装置及びその組立て方法
JPH06125032A (ja) * 1992-08-31 1994-05-06 Taiyo Yuden Co Ltd 混成集積回路装置及びその製造方法
JPH0682860U (ja) * 1993-04-28 1994-11-25 京セラ株式会社 表面実装型電子部品
JP2842355B2 (ja) * 1996-02-01 1999-01-06 日本電気株式会社 パッケージ
JPH09232368A (ja) * 1996-02-20 1997-09-05 Fujitsu Ltd 半導体装置
SG60099A1 (en) * 1996-08-16 1999-02-22 Sony Corp Semiconductor package and manufacturing method of lead frame
JP3420913B2 (ja) * 1997-06-13 2003-06-30 ミネソタ マイニング アンド マニュファクチャリング カンパニー 半導体チップ実装用回路基板、半導体チップ収納用パッケージ、及び半導体デバイス
JP3893440B2 (ja) 1999-12-24 2007-03-14 株式会社デンソーウェーブ 物流用容器のデータキャリアリードライトシステムおよびデータキャリア用リーダライタ
US6597059B1 (en) * 2001-04-04 2003-07-22 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package
TW540123B (en) * 2002-06-14 2003-07-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package with lead frame as chip carrier
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US7217594B2 (en) * 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
US7361531B2 (en) * 2005-11-01 2008-04-22 Allegro Microsystems, Inc. Methods and apparatus for Flip-Chip-On-Lead semiconductor package
EP2474842B1 (en) 2009-08-31 2019-03-27 Sumida Corporation Capacitance type detection device, sensor unit, and control system for detecting approach of object, and method for same
WO2012165434A1 (ja) * 2011-05-31 2012-12-06 京セラ株式会社 素子収納用パッケージ、半導体装置用部品および半導体装置
CN103534796B (zh) * 2011-08-10 2016-06-01 富士电机株式会社 半导体装置和半导体装置的制造方法
JP5893874B2 (ja) * 2011-09-02 2016-03-23 信越化学工業株式会社 光半導体装置
JP2013185232A (ja) * 2012-03-09 2013-09-19 Hitachi Cable Ltd 銅合金材及び銅合金材の製造方法
JP6201626B2 (ja) * 2013-10-23 2017-09-27 スミダコーポレーション株式会社 電子部品及び電子部品の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101026110A (zh) * 2006-02-22 2007-08-29 三洋电机株式会社 电路装置的制造方法

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