WO2012165434A1 - 素子収納用パッケージ、半導体装置用部品および半導体装置 - Google Patents
素子収納用パッケージ、半導体装置用部品および半導体装置 Download PDFInfo
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- WO2012165434A1 WO2012165434A1 PCT/JP2012/063779 JP2012063779W WO2012165434A1 WO 2012165434 A1 WO2012165434 A1 WO 2012165434A1 JP 2012063779 W JP2012063779 W JP 2012063779W WO 2012165434 A1 WO2012165434 A1 WO 2012165434A1
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- Prior art keywords
- region
- base body
- mounting
- conductor
- package
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/02—Details
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4256—Details of housings
- G02B6/4262—Details of housings characterised by the shape of the housing
- G02B6/4265—Details of housings characterised by the shape of the housing of the Butterfly or dual inline package [DIP] type
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
- G02B6/4279—Radio frequency signal propagation aspects of the electrical connection, high frequency adaptations
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4292—Coupling light guides with opto-electronic elements the light guide being disconnectable from the opto-electronic element, e.g. mutually self aligning arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
Definitions
- the present invention relates to a semiconductor element storage package for storing a semiconductor element, and a semiconductor device component and a semiconductor device including the same.
- a semiconductor element storage package for storing a semiconductor element and a semiconductor device component and a semiconductor device including the same.
- Such a package for housing a semiconductor element can be used for various electronic devices.
- a package described in Patent Document 1 is known as an element storage package (hereinafter also simply referred to as a package) for storing semiconductor elements.
- the package described in Patent Document 1 includes a package substrate (base), a via hole (connection conductor) provided from the upper surface to the lower surface of the package substrate, and a signal line metal thin film (circuit conductor) provided on the lower surface of the package substrate. ).
- the package described in Patent Document 1 is used by being attached to a mounting board.
- circuit conductor when the circuit conductor is provided on the lower surface of the base as in the package described in Patent Document 1, the circuit conductor may be misaligned when the package is mounted on the mounting substrate. It was.
- the substrate may be deformed by pressing the package against the mounting substrate in a state where the base is warped. For this reason, the circuit conductor attached to the lower surface of the base may be shifted to a position different from a desired position. As a result, impedance matching may be difficult between the package and the mounting substrate.
- An element storage package has a mounting area for mounting a semiconductor element, a base having a rectangular shape when viewed from above, and an upper surface of the base so as to surround the mounting area
- a circuit conductor having an end portion drawn laterally from the first side surface of the base body and a second side surface joined to the lower surface of the base body and adjacent to the first side surface are pulled sideways.
- a metal plate having a grounding conductor region drawn laterally from the first side surface of the base so as to be parallel to the circuit conductor.
- the metal plate further includes an outer peripheral region that is pulled out to the side of the base body from the ground conductor region to the attachment region along the outer periphery of the base body when viewed in plan.
- FIG. 1 is an exploded perspective view showing an element storage package according to a first embodiment, a semiconductor device component including the same, and a semiconductor device.
- FIG. 2 is a plan view of the element storage package shown in FIG. 1. It is a bottom view of the element storage package shown in FIG.
- FIG. 4 is a cross-sectional view of the element storage package shown in FIG. 3 taken along line X-X ′. It is a bottom view which shows the package for element storage concerning 2nd Embodiment.
- an element storage package (hereinafter also simply referred to as a package) according to each embodiment, a semiconductor device component including the same, and a semiconductor device will be described in detail with reference to the drawings.
- a package an element storage package
- the semiconductor device component and the semiconductor device according to the present invention can include arbitrary constituent members that are not shown in the drawings referred to in this specification.
- the element storage package 1 has a base 5 having a mounting area 5a for mounting the semiconductor element 3 and an upper surface of the base 5 so as to surround the mounting area 5a.
- a conductor 21 and two metal plates 35 are provided.
- the connection conductor 9 is electrically connected to the semiconductor element 3 via a bonding wire 31 at a portion located on the upper surface of the base body 5.
- the circuit conductor 21 has one end electrically connected to the connection conductor 9 and the other end pulled out from the first side surface 51 of the base body 5 to the side.
- the two metal plates 35 are respectively connected to a bonding region 35 a bonded to the lower surface of the base 5, a mounting region 35 b that is pulled out from the second side surface 52 of the base 5 and attached to the mounting substrate 17, and the circuit conductor 21.
- the grounding conductor region 35c drawn laterally from the first side surface 51 of the base 5 so as to be parallel, and the outer periphery drawn sideways of the base 5 from the grounding conductor region 35c to the mounting region 35b when viewed in plan. It has area
- the “second side surface 52” does not mean only one side surface among the side surfaces of the substrate 5, but means two side surfaces adjacent to the first side surface 51.
- the strength of the metal plate 35 can be improved by integrally forming the ground conductor region 35c, the attachment region 35b, and the outer peripheral region 35d. Since the metal plate 35 with improved strength is provided on the lower surface of the base body 5, the base body 5 can be made difficult to deform. Thereby, even if the package 1 is pressed against the mounting substrate 17, the possibility that the base body 5 is deformed can be suppressed. Therefore, the possibility that the circuit conductor 21 attached to the lower surface of the base body 5 is shifted to a position different from the desired position can be suppressed. As a result, impedance matching between the package 1 and the mounting substrate 17 can be facilitated.
- the attachment region 35b and the outer peripheral region 35d of the metal plate 35 are continuous. Thereby, when the package 1 is mounted on the mounting substrate 17, it is possible to suppress the possibility that stress is concentrated on a part of the base body 5. Specifically, if there is a gap between the outer peripheral region 35d and the attachment region 35b, the attachment region 35b of the peripheral portion of the substrate 5 when the attachment region 35b and the mounting substrate 17 are screwed together. Stress concentrates in the region where the is pulled out. However, in the package 1 according to the present embodiment, when the attachment region 35b and the mounting substrate 17 are screwed together, the attachment region 35b of the boundary portion between the attachment region 35b and the outer peripheral region 35d and the peripheral portion of the substrate 5 is secured. The stress is distributed in two regions, the region from which is drawn. Thereby, the possibility that the substrate 5 is deformed can be suppressed.
- the base body 5 in the present embodiment has a square plate shape and has a mounting region 5a on which the semiconductor element 3 is placed on the main surface.
- the mounting region 5a means a region overlapping with the semiconductor element 3 when the base 5 is viewed in plan.
- the size can be set to, for example, 5 mm or more and 50 mm or less on a side.
- substrate 5 it can set to 0.2 mm or more and 2 mm or less, for example.
- the mounting area 5a is formed at the center of the main surface.
- the mounting area 5a for example, at the end of the main surface of the base 5 There is no problem even if the mounting region 5a is formed.
- the base body 5 of this embodiment has one mounting area 5a, the base body 5 may have a plurality of mounting areas 5a, and the semiconductor element 3 may be placed in each of the mounting areas 5a. .
- the semiconductor element 3 is disposed in the mounting area 5 a on the main surface of the base body 5. Signals can be input / output between the semiconductor element 3 and an external electric circuit (not shown) via an input / output terminal or the like. As described above, since the semiconductor element 3 is disposed on the main surface of the base body 5, the base body 5 is required to have high insulation properties at least in a portion where the semiconductor element 3 is disposed. It is done.
- the base 5 according to the present embodiment is produced by laminating a plurality of insulating members. Then, the semiconductor element 3 is placed on the mounting area 5 a of the base body 5.
- the insulating member examples include a ceramic material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a silicon nitride sintered body, or a glass ceramic. Materials can be used.
- a mixing member is prepared by mixing raw material powder containing these glass powder and ceramic powder, an organic solvent, and a binder.
- a plurality of ceramic green sheets are produced by forming the mixed member into a sheet.
- a plurality of laminated bodies are produced by laminating the produced ceramic green sheets.
- the base body 5 is produced by integrally firing a plurality of laminated bodies at a temperature of about 1600 degrees.
- the base 5 is not limited to a configuration in which a plurality of insulating members are stacked.
- the base 5 may be composed of one insulating member.
- the semiconductor element 3 may be directly mounted on the upper surface of the base 5, but the semiconductor element 3 disposed on the mounting region 5 a of the base 5 is placed as in the package 1 of the present embodiment.
- the semiconductor element 3 may be mounted on the mounting substrate 19.
- the mounting substrate 19 it is preferable to use a member having good insulation like the insulating member.
- an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, and an aluminum nitride material are used. Ceramic materials such as sintered bodies and silicon nitride-based sintered bodies, or glass ceramic materials can be used.
- the package 1 of the present embodiment includes a frame body 7 disposed on the upper surface of the base 5 so as to surround the mounting area 5a.
- a frame body 7 for example, in the same manner as the base body 5, for example, an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a silicon nitride sintered body are used.
- Such ceramic materials or glass ceramic materials can be used.
- a metal member such as iron, copper, nickel, chromium, cobalt, and tungsten, or an alloy made of these metals can be used.
- the metal member constituting the frame body 7 can be manufactured by subjecting such an ingot of the metal member to a metal processing method such as a rolling method or a punching method. Further, the frame body 7 may be composed of one member, but may be a laminated structure of a plurality of members.
- the element storage package 1 of the present embodiment includes a joining member (not shown) that is positioned between the base body 5 and the frame body 7 and joins the base body 5 and the frame body 7.
- a joining member (not shown) that is positioned between the base body 5 and the frame body 7 and joins the base body 5 and the frame body 7.
- a brazing material can be used as the joining member.
- Exemplary brazing materials include silver brazing.
- the package 1 of the present embodiment includes a plurality of connection conductors 9 provided from the upper surface to the lower surface of the base body 5.
- the connection conductor 9 has a function of transmitting an electric signal generated by the semiconductor element 3 from the upper surface to the lower surface of the substrate 5 or a function of transmitting an electric signal input from the outside from the lower surface of the substrate 5 to the upper surface. .
- One end of each of the plurality of connection conductors 9 is exposed on the upper surface of the base 5.
- the other end of each of the plurality of connection conductors 9 is exposed on the lower surface of the base 5.
- connection conductor 9 in the present embodiment is electrically connected to the semiconductor element 3 through the bonding wire 31, but is not limited thereto.
- the connection conductor 9 may be routed to the mounting region 5 a on the upper surface of the base body 5 in the mounting region and directly connected to the semiconductor element 3 without using the bonding wire 31.
- connection conductor 9 a member having good conductivity is preferably used.
- a metal material such as tungsten, molybdenum, nickel, manganese, copper, silver and gold can be used as the connection conductor 9.
- the above metal materials may be used alone or as an alloy.
- connection conductor 9 As a method of forming the connection conductor 9, there is a method of forming a through hole penetrating between the upper surface and the lower surface of the base 5 and disposing a metal paste in the through hole. As a method of disposing the metal paste in the through hole, a known suction method or the like may be used.
- the connection conductor 9 may be formed so that the entire inside of the through hole is filled with a metal material. Moreover, it may be disposed so as to cover the inner wall of the through hole and form a cavity on the inner peripheral side.
- the circuit conductor 21, the metal plate 35, and the attachment member 13 are provided on the lower surface of the base body 5, respectively.
- the metal plate 35 in the present embodiment has a joining region 35a, a mounting region 35b, a ground conductor region 35c, and an outer peripheral region 35d.
- a plate-shaped metal member can be used.
- a metal material constituting the metal member a metal material such as copper can be used.
- thickness of the metal plate 35 it can set to 0.1 mm or more and 1 mm or less, for example.
- the package 1 of this embodiment has a pair of ground conductor regions 35c positioned so as to sandwich the circuit conductor 21 and the circuit conductor 21 therebetween.
- One end of the circuit conductor 21 is electrically connected to the connection conductor 9, and the other end is drawn out to the side of the base 5.
- the circuit conductor 21 is provided for electrically connecting the connection conductor 9 and the wiring circuit 25 disposed on the mounting substrate 17.
- the pair of ground conductor regions 35 c are electrically connected to the ground wiring 27 disposed on the mounting substrate 17.
- the pair of ground conductor regions 35 c are drawn from the first side surface 51 in the same direction as the circuit conductor 21.
- a coplanar line is formed together with the circuit conductor 21 and the pair of ground conductor regions 35c.
- ground and ground mean that they are electrically connected to an external reference potential (not shown) as a so-called ground potential, and the reference potential is not necessarily a potential. Need not be 0V.
- a strip-shaped metal member is used as the circuit conductor 21.
- the circuit conductor 21 is made of a metal material such as copper, for example.
- the circuit conductor 21 is attached to the lower surface of the base body 5 by joining the connection conductor 9 and the circuit conductor 21 with a brazing material or the like.
- the thickness of the circuit conductor 21 can be set to 0.05 mm or more and 0.5 mm or less, for example.
- the attachment region 35b in the present embodiment has a rectangular shape when viewed in plan.
- the attachment region 35 b has a through hole (screw fixing hole 29) for screwing to the mounting substrate 17.
- the package 1 can be fixed to the mounting substrate 17 by screwing the package 1 to the mounting substrate 17 through the screw holes 29. At this time, in order to firmly fix the package 1 to the mounting substrate 17, a pressing force is applied to the package 1 toward the mounting substrate 17.
- the bonding region 35a of the metal plate 35 is bonded to the lower surface of the substrate 5 by separately forming a metal film on the lower surface of the substrate 5 by a metallization method, and the bonding region 35a of the metal plate 35 is formed on the metal film by using a brazing material or the like. It is performed by using and joining.
- the mounting members 13 each have a rectangular shape when viewed in plan.
- the attachment member 13 has a through hole (screw fixing hole 29) for screwing to the mounting substrate 17.
- the package 1 can be fixed to the mounting substrate 17 by screwing the package 1 to the mounting substrate 17 through the screw holes 29. At this time, in order to firmly fix the package 1 to the mounting substrate 17, a pressing force is applied to the package 1 toward the mounting substrate 17.
- the attachment of the attachment member 13 to the lower surface of the substrate 5 is performed by separately forming a metal film on the lower surface of the substrate 5 by a metallization method and bonding the attachment member 13 to the metal film using a brazing material or the like.
- a plate-like metal member can be used.
- a metal material such as copper can be used as in the case of the circuit conductor 21 and the metal plate 35.
- thickness of the attachment member 13 it can set to 0.1 mm or more and 1 mm or less, for example.
- the package 1 is fixed to the mounting board 17 by the screwing holes 29 provided in the mounting region 35b and the mounting member 13, but the present invention is not limited to this.
- the lower surface of the attachment region 35b may be bonded to the upper surface of the mounting substrate 17 using a brazing material or the like.
- the thickness of the metal plate 35 is larger than the thickness of the circuit conductor 21.
- the thickness of the metal plate 35 is preferably 1.5 to 3 times the thickness of the circuit conductor 21.
- the difference between the thickness of the metal plate 35 and the thickness of the circuit conductor 21 is preferably 0.05 to 0.5 mm.
- the width of the outer peripheral area 35d in the laterally drawn direction is smaller than the width of each of the attachment area 35b and the ground conductor area 35c in the laterally drawn direction. Since the width of the outer peripheral area 35d in the direction pulled out to the side is smaller than the width of each of the mounting areas 35b in the direction pulled out to the side, the outer peripheral area 35d is obstructive when the mounting area 35b is attached to the mounting substrate 17. Can be prevented.
- the ground conductor region 35c is disposed on the mounting substrate 17 because the width of the outer peripheral region 35d in the laterally drawn direction is smaller than the width of the grounded conductor region 35c in the laterally drawn direction.
- the semiconductor device component 100 includes the package 1 typified by the above embodiment, and the mounting substrate 17 to which the package 1 is attached by the attachment region 35b. As already shown, the package 1 is fixed to the mounting substrate 17 by the screwing holes 29 provided in the attachment region 35 b and the attachment member 13.
- the semiconductor device 101 according to the present embodiment is bonded to the semiconductor device component 100, the semiconductor element 3 mounted on the mounting region 5 a of the package 1 in the semiconductor device component 100, and the upper surface of the frame body 7.
- a lid 33 that seals the semiconductor element 3 is provided.
- the semiconductor element 3 is mounted on the mounting region of the substrate.
- the semiconductor element 3 and the circuit conductor 21 are connected by bonding wires 31.
- a desired output can be obtained from the semiconductor element 3 by inputting an external signal to the semiconductor element 3 through the connection conductor 9 or the like.
- the semiconductor element 3 include a light emitting element that emits light to an optical fiber, typified by an LD element, and a light receiving element that receives light to an optical fiber, typified by a PD element.
- the lid body 33 is joined to the frame body 7 so as to seal the semiconductor element 3.
- the lid body 33 is joined to the upper surface of the frame body 7.
- the semiconductor element 3 is sealed in a space surrounded by the base body 5, the frame body 7, and the lid body 33.
- a metal member such as iron, copper, nickel, chromium, cobalt, and tungsten, or an alloy made of these metals can be used.
- the frame body 7 and the lid body 33 can be joined by, for example, a seam welding method. Further, the frame body 7 and the lid body 33 may be joined using, for example, gold-tin solder.
- the two attachment members 13 and the two metal plates 35 are provided separately, but the present invention is not limited to this.
- the attachment member 13 and the metal plate 35 may be integrally formed.
- the attachment member 13 and the metal plate 35 are integrally formed, whereby the strength of the metal plate 35 can be further improved. Thereby, even if the package 1 is pressed against the mounting substrate 17, the possibility that the base body 5 is deformed can be further suppressed. Therefore, the possibility that the circuit conductor 21 attached to the lower surface of the base body 5 is shifted to a position different from a desired position can be further suppressed.
- the package 1 according to the second embodiment includes a plurality of circuit conductors 21. Furthermore, the package 1 according to the second embodiment further includes an auxiliary ground conductor region 35 e in which the metal plate 35 is located between the plurality of circuit conductors 21. Thereby, the isolation characteristic between the some circuit conductors 21 can be improved. Further, since the metal plate 35 has the auxiliary ground conductor region 35e, the area of the region where the metal plate 35 and the base 5 are in contact with each other can be increased. Thereby, possibility that the base
- auxiliary grounding conductor region 35e is drawn out from the first side surface 51 to the side. Thereby, the isolation characteristic between the several circuit conductors 21 can further be improved.
- the auxiliary grounding conductor region 35e is pulled out from the first side surface 51 to the side, but the present invention is not limited to this. Specifically, the auxiliary ground conductor region 35e may be provided only between the regions of the circuit conductor 21 that are joined to the lower surface of the base 5.
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Power Engineering (AREA)
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Abstract
Description
3・・・半導体素子
5・・・基体
5a・・・搭載領域
7・・・枠体
9・・・接続導体
13・・・取付け部材
17・・・実装基板
19・・・載置基板
21・・・回路導体
25・・・配線回路
27・・・グランド配線
29・・・ネジ止め孔
31・・・ボンディングワイヤ
33・・・蓋体
35・・・金属板
100・・・半導体装置用部品
101・・・半導体装置
Claims (6)
- 半導体素子を搭載するための搭載領域を上面に有する、平面視したときの形状が矩形状の基体と、
前記搭載領域を囲むように前記基体の上面に設けられた枠体と、
前記基体の上面のうち前記枠体の内側から下面にかけて設けられた、前記半導体素子が電気的に接続される接続導体と、
前記基体の下面に設けられた、一方の端部が前記接続導体に電気的に接続されるとともに、他方の端部が前記基体の第1の側面から側方に引き出された回路導体と、
前記基体の下面に接合された、前記基体の前記第1の側面と隣接する第2の側面から側方に引き出されて実装基板に取り付けられる取付け領域および前記回路導体に平行となるように前記基体の前記第1の側面から側方に引き出された接地導体領域を有する金属板とを備え、
該金属板は、平面視した場合に、前記基体の外周に沿って、前記接地導体領域から前記取付け領域にかけて前記基体の前記第1の側面および前記第2の側面から側方に引き出された外周領域をさらに有することを特徴とする素子収納用パッケージ。 - 前記金属板が、前記取付け領域に、前記実装基板にネジ止めするための貫通孔を備えていることを特徴とする請求項1に記載の素子収納用パッケージ。
- 前記金属板の厚みが前記回路導体の厚みよりも大きいことを特徴とする請求項1に記載の素子収納用パッケージ。
- 前記回路導体を複数備えるとともに、前記金属板が複数の前記回路導体の間に位置する補助接地導体領域をさらに有することを特徴とする請求項1に記載の素子収納用パッケージ。
- 請求項1~4のいずれかに記載の素子収納用パッケージと、該素子収納用パッケージが前記取付け領域によって取り付けられた実装基板とを備えた半導体装置用部品。
- 請求項5に記載の半導体装置用部品と、
該半導体装置用部品の前記素子収納用パッケージの前記搭載領域に搭載された半導体素子と、
前記枠体の上面に接合された、前記半導体素子を封止する蓋体とを備えた半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013518105A JP5518260B2 (ja) | 2011-05-31 | 2012-05-29 | 素子収納用パッケージ、半導体装置用部品および半導体装置 |
CN201280003985.2A CN103250240B (zh) | 2011-05-31 | 2012-05-29 | 元件收纳用封装、半导体装置用部件以及半导体装置 |
EP12792890.1A EP2717309B1 (en) | 2011-05-31 | 2012-05-29 | Element housing package, component for semiconductor device, and semiconductor device |
US13/980,552 US9491873B2 (en) | 2011-05-31 | 2012-05-29 | Element housing package, component for semiconductor device, and semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-121243 | 2011-05-31 | ||
JP2011121243 | 2011-05-31 |
Publications (1)
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WO2012165434A1 true WO2012165434A1 (ja) | 2012-12-06 |
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PCT/JP2012/063779 WO2012165434A1 (ja) | 2011-05-31 | 2012-05-29 | 素子収納用パッケージ、半導体装置用部品および半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9491873B2 (ja) |
EP (1) | EP2717309B1 (ja) |
JP (1) | JP5518260B2 (ja) |
CN (1) | CN103250240B (ja) |
WO (1) | WO2012165434A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2018021209A1 (ja) * | 2016-07-28 | 2019-05-09 | 京セラ株式会社 | 半導体素子実装用基板および半導体装置 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9078347B2 (en) * | 2010-07-30 | 2015-07-07 | Kyocera Corporation | Electronic component housing unit, electronic module, and electronic device |
US9237662B2 (en) * | 2010-09-28 | 2016-01-12 | Kyocera Corporation | Device housing package and electronic apparatus employing the same |
JP6201626B2 (ja) * | 2013-10-23 | 2017-09-27 | スミダコーポレーション株式会社 | 電子部品及び電子部品の製造方法 |
US9935025B2 (en) * | 2014-03-13 | 2018-04-03 | Kyocera Corporation | Electronic component housing package and electronic device |
CN110087851B (zh) * | 2016-12-22 | 2024-04-12 | 日立安斯泰莫株式会社 | 电子控制装置 |
JP6829303B2 (ja) * | 2017-02-23 | 2021-02-10 | 京セラ株式会社 | 絶縁基体、半導体パッケージおよび半導体装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04336702A (ja) | 1991-05-14 | 1992-11-24 | Mitsubishi Electric Corp | パッケージ |
JP2002368322A (ja) | 2001-06-06 | 2002-12-20 | Kyocera Corp | 光半導体素子収納用パッケージおよび光半導体装置 |
JP2003046180A (ja) * | 2001-07-26 | 2003-02-14 | Kyocera Corp | 入出力端子および光半導体素子収納用パッケージならびに光半導体装置 |
JP2004055570A (ja) * | 2002-07-16 | 2004-02-19 | Kyocera Corp | 高周波用パッケージ |
JP2004088067A (ja) * | 2002-06-27 | 2004-03-18 | Kyocera Corp | 高周波信号伝送用積層構造およびそれを用いた高周波半導体パッケージ |
JP2007287916A (ja) * | 2006-04-17 | 2007-11-01 | Fujitsu Ltd | 電子部品パッケージ |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4518982A (en) * | 1981-02-27 | 1985-05-21 | Motorola, Inc. | High current package with multi-level leads |
US5767447A (en) * | 1995-12-05 | 1998-06-16 | Lucent Technologies Inc. | Electronic device package enclosed by pliant medium laterally confined by a plastic rim member |
US6384478B1 (en) * | 1998-05-06 | 2002-05-07 | Conexant Systems, Inc. | Leadframe having a paddle with an isolated area |
JP3346752B2 (ja) * | 1999-11-15 | 2002-11-18 | 日本電気株式会社 | 高周波パッケージ |
JP3667274B2 (ja) * | 2001-11-12 | 2005-07-06 | 京セラ株式会社 | 高周波用パッケージ |
US6933450B2 (en) | 2002-06-27 | 2005-08-23 | Kyocera Corporation | High-frequency signal transmitting device |
US20040080917A1 (en) * | 2002-10-23 | 2004-04-29 | Steddom Clark Morrison | Integrated microwave package and the process for making the same |
US6936921B2 (en) * | 2002-11-11 | 2005-08-30 | Kyocera Corporation | High-frequency package |
US6921971B2 (en) * | 2003-01-15 | 2005-07-26 | Kyocera Corporation | Heat releasing member, package for accommodating semiconductor element and semiconductor device |
US7446411B2 (en) * | 2005-10-24 | 2008-11-04 | Freescale Semiconductor, Inc. | Semiconductor structure and method of assembly |
KR101037229B1 (ko) * | 2006-04-27 | 2011-05-25 | 스미토모 베이클리트 컴퍼니 리미티드 | 반도체 장치 및 반도체 장치의 제조 방법 |
CN102017132B (zh) * | 2008-05-02 | 2013-05-08 | 株式会社新王材料 | 气密密封用盖 |
-
2012
- 2012-05-29 JP JP2013518105A patent/JP5518260B2/ja not_active Expired - Fee Related
- 2012-05-29 CN CN201280003985.2A patent/CN103250240B/zh not_active Expired - Fee Related
- 2012-05-29 US US13/980,552 patent/US9491873B2/en active Active
- 2012-05-29 EP EP12792890.1A patent/EP2717309B1/en not_active Not-in-force
- 2012-05-29 WO PCT/JP2012/063779 patent/WO2012165434A1/ja active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04336702A (ja) | 1991-05-14 | 1992-11-24 | Mitsubishi Electric Corp | パッケージ |
JP2002368322A (ja) | 2001-06-06 | 2002-12-20 | Kyocera Corp | 光半導体素子収納用パッケージおよび光半導体装置 |
JP2003046180A (ja) * | 2001-07-26 | 2003-02-14 | Kyocera Corp | 入出力端子および光半導体素子収納用パッケージならびに光半導体装置 |
JP2004088067A (ja) * | 2002-06-27 | 2004-03-18 | Kyocera Corp | 高周波信号伝送用積層構造およびそれを用いた高周波半導体パッケージ |
JP2004055570A (ja) * | 2002-07-16 | 2004-02-19 | Kyocera Corp | 高周波用パッケージ |
JP2007287916A (ja) * | 2006-04-17 | 2007-11-01 | Fujitsu Ltd | 電子部品パッケージ |
Non-Patent Citations (1)
Title |
---|
See also references of EP2717309A4 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2018021209A1 (ja) * | 2016-07-28 | 2019-05-09 | 京セラ株式会社 | 半導体素子実装用基板および半導体装置 |
US10777493B2 (en) | 2016-07-28 | 2020-09-15 | Kyocera Corporation | Semiconductor device mounting board and semiconductor package |
JP2021101475A (ja) * | 2016-07-28 | 2021-07-08 | 京セラ株式会社 | 半導体素子実装用基板および半導体装置 |
JP7049500B2 (ja) | 2016-07-28 | 2022-04-06 | 京セラ株式会社 | 半導体素子実装用基板および半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5518260B2 (ja) | 2014-06-11 |
US9491873B2 (en) | 2016-11-08 |
EP2717309A1 (en) | 2014-04-09 |
US20130322036A1 (en) | 2013-12-05 |
JPWO2012165434A1 (ja) | 2015-02-23 |
EP2717309A4 (en) | 2015-05-06 |
CN103250240B (zh) | 2016-01-06 |
CN103250240A (zh) | 2013-08-14 |
EP2717309B1 (en) | 2019-01-09 |
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