CN101026110A - 电路装置的制造方法 - Google Patents
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Abstract
本发明提供一种电路装置的制造方法,提高引线固定位置的精度且简化引线固定的工序。其具有:准备与在表面上形成包括焊盘(13A)的导电图形(13)的多个电路基板(11)连结成一体的基板(50)的第一工序;把电路元件电连接到各个电路基板(11)的导电图形(13)上的第二工序;通过把多个引线(25)组成的引线框(40)重叠到基板(50)上、使引线(25)的端部位于焊盘(13A)的上方并把引线(25)固定到焊盘(13A)的第三工序;在引线(25)被固定到电路基板(11)的焊盘(13A)上的状态下,从基板(50)分离电路基板(11),且从引线框(40)分离引线(25)的第四工序。
Description
技术领域
本发明涉及一种电路装置的制造方法,特别是涉及具有作为外部端子功能的引线的电路装置的制造方法。
背景技术
参照图5,对现有技术的混合集成电路装置100的构成进行说明(参照下述的专利文献1)。在矩形的基板101的表面上,经由绝缘层102形成导电图形103。在导电图形103的所希望的位置固定电路元件,形成所定的电路。在这里,作为电路元件的半导体元件105A及芯片元件105B连接到导电图形103上。引线104连接到在基板101的周边部形成的导电图形103形成的焊盘109上,具有外部端子的功能。封固树脂108具有封固在基板101的表面上形成的电路的功能。这样构成的混合集成电路装置100,由于可以把从半导体元件105A等产生的热量经由基板101积极地排到外部,所以散热性优良。
所述的混合集成电路装置100的制造方法如下。首先,在由铝等的金属组成的基板101的表面上形成导电图形103。接着,在导电图形103的所定的位置,固定半导体元件105A及芯片元件105B并进行电连接。进一步,在由导电图形103组成的焊盘109上固定引线104。最后,在基板101的表面上形成封固树脂108,以覆盖半导体元件105A等的电路元件。
专利文献1:特开平5-102645号公报
但是,在上述的混合集成电路装置的制造方法中,有引线104的对位等花费时间的问题。
具体地,固定引线104的工序的详细内容如下。首先,在基板101的表面形成的焊盘109的表面上涂布焊料等的接合材料。接着,使引线104的顶端部的位置与焊盘109的表面一致。进一步,使用回流炉等,熔化焊盘109上的焊料,把引线104固定到焊盘109上。
因此,在上述工序中,使各个引线104的顶端与焊盘109的上部进行对位,而且,一直到焊料熔化、凝固,需要保持引线104的所定位置。因此,引线104的固定非常花费时间。
另外,当使用多个引线104连结状态的引线框时,由于对引线104的对位可以一次进行,所以可以简单地进行引线104的对位。但是,在使用引线框时,需要电路基板101与引线框的对位等,所以,引线104的对位的成本就很高。
发明内容
本发明是鉴于上述问题而开发的,本发明的主要目的是提供一种简化在电路基板的焊盘上固定引线的工序、降低制造成本的电路装置的制造方法。
本发明的电路装置的制造方法,在电路基板的表面上装入由导电图形与电路元件组成的电路、把引线固定到由所述导电图形组成的焊盘的电路装置的制造方法,其特征在于,准备与在表面上形成包括所述焊盘的所述导电图形的多个所述电路基板连结成一体的基板的第一工序;把所述电路元件电连接到各个所述电路基板的所述导电图形上的第二工序;通过把多个所述引线组成的引线框重叠到所述基板上、使所述引线的端部位于所述焊盘的上方、把所述引线固定到所述焊盘的第三工序;在把所述引线固定到所述电路基板的所述焊盘的状态下、从所述基板分离所述电路基板、且从所述引线框分离所述引线的第四工序。
而且,本发明的电路装置的制造方法,其特征在于,在第三工序中,把所述引线框重叠到所述基板上,通过在贯通所述引线框设置的第一定位孔与贯通所述基板设置的第二定位孔中嵌合定位销,对所述基板和引线框进行对位,且连结。
而且,本发明的电路装置的制造方法,其特征在于,所述基板和所述引线框具有大致相同的平面大小。
而且,本发明的所述的电路装置的制造方法,其特征在于,在所述第四工序中,通过冲压加工,使所述电路基板及所述引线分离。
而且,本发明的所述的电路装置的制造方法,其特征在于,在所述第三工序中,经由覆盖所述基板的表面的B阶段状态的绝缘层,所述引线框粘合到所述基板上。
而且,本发明的所述的电路装置的制造方法,其特征在于,在所述基板与所述引线框连结的状态,至少封固所述电路基板的表面。
依据本发明,可以简化在电路基板上的焊盘上进行对位引线的工序,制造电路装置,所以,能降低制造成本。具体地,在本发明中,准备多个电路基板形成的基板,进一步,准备由所定的引线组成的多个单元形成的引线框。而且,通过把基板与引线框重叠,可以对各个电路基板上的焊盘与引线框上包括的各个引线的端部进行对位。因此,没有必要对于各个引线框分别进行定位。而且,不需要另外设置用于机械地支承引线框的夹具等。由此,可以大大减小引线对位所花费的时间、降低制造成本。另外,也能提高引线的对位精度。
附图说明
图1是表示本发明的电路装置的图、图1(A)及图1(B)是立体图;
图2是表示本发明的电路装置的制造方法的图、图2(A)~(C)是平面图、(D)是剖面图;
图3是表示本发明的电路装置的制造方法的图、图3(A)是平面图、图3(B)是剖面图;
图4是表示本发明的电路装置的制造方法的图、图4(A)是剖面图、图4(B)是平面图;
图5是表示现有技术的混合集成电路装置的剖面图。
附图标记
10:混合集成电路装置 11:电路基板 12:绝缘层 13:导电图形14:封固树脂 15A、15B:半导体元件 15C:芯片元件 17:金属细线13A:焊盘 22A:上模 22B:下模 23:模腔 25:引线 40:引线框 41:外框 42:第一定位孔 46:单元 50:基板 51:外框 52:连结部 53:第二定位孔 54:定位销
具体实施方式
第一实施方式
在本实施方式中,对作为电路装置的一个实例的混合集成电路装置10的构造进行说明。
参照图1,说明本发明的混合集成电路装置10。图1(A)是从斜上方观察到的混合集成电路装置的10的立体图。图1(B)是省略了封固全部的封固树脂14的混合集成电路装置10的立体图。
参照图1(A)及图1(B),本实施方式的混合集成电路装置10具有:电路基板11;在电路基板11的表面上形成的导电图形13;固定在导电图形13上的半导体元件15A等的电路元件;固定在由导电图形13形成的焊盘13A上的引线25。即,在电路基板11的上面,装入由导电图形13及电路元件组成的、具有所定功能的电路。另外,与在电路基板的表面上形成的电路连接的引线25、从封固树脂14引出到外部。
电路基板11是以铝(Al)或铜(Cu)等的金属为主要材料的金属基板。电路基板11的具体大小为例如、长×宽×厚=60mm×30mm×1.5mm左右。作为电路基板11当使用由铝组成的基板时,在电路基板11的两个主面上形成有氧化膜进行氧化铝膜处理。
电路基板11的侧面根据制造方法形成不同的形状。即,根据使用冲压机进行冲压制造电路基板11时,电路基板11A的侧面变为直线形状。另一方面,通过形成V字形的切割槽制造电路基板11时,电路基板11A的侧面变为向外侧突出的倾斜面。
绝缘层12覆盖电路基板11的上面整个区域而形成。绝缘层12由AL2O3等的填充物进行高填充的环氧树脂组成,热电阻降低。因此,内置的电路元件产生的热量经由热电阻降低的绝缘层12可以积极地传导到电路基板11上。绝缘层12的具体的厚度为例如50μm左右。另外,电路基板11的背面也可以由绝缘层12覆盖。这样,即使电路基板11的背面从封固树脂14露出外部,也可以使电路基板11的背面与外部绝缘。
导电图形13由铜等的金属组成,并在绝缘层12的表面形成以使所定的电路形成。另外,在引线25导出的一边由导电图形13组成的焊盘13A形成。而且,在半导体元件15A的周围,也有由导电图形13组成的多个焊盘形成,该焊盘与半导体元件15A通过金属细线17连接。在这里,单层的导电图形13在图中表示出来,但也可以经由绝缘层在电路基板11的上面形成层叠两层以上的导电图形13。
作为在电路基板11上组装的电路元件,可以全部采用有源元件或者无源元件。具体地,可以采用晶体管、LSI芯片、二极管、芯片电阻、芯片电容、电感、热敏电阻、天线及振荡器等作为电路元件。并且另外,树脂封固型的封装件等也作为电路元件可以固定到导电图形13上。在图中,芯片元件15C和半导体元件15A、15B作为电路元件表示出来。
引线25,其一端与电路基板11上的焊盘13A电连接,另一端从封固树脂14引出到外部。引线25由铜(Cu)、铝(A1)或者Fe-Ni的合金等为主要成分的金属组成。在这里,引线25连接到沿着相对电路基板11的两个侧边设置的焊盘13A上。但是沿着电路基板11A的1个侧边或者4个侧边设置有多个焊盘13A,也可以把引线25连接到该焊盘13A上。
封固树脂14由使用热固性树脂的传递模或者使用热塑性树脂的注射模形成。在这里,也可以通过封固树脂14覆盖包括背面的电路基板11的全部,也可以使电路基板11的背面从封固树脂14露出。
而且在本实施方式中,参照图1(A),电路基板11的一部分的连结部52从封固全部的封固树脂14的侧面露出。例如,参照图2(C),为了使多个电路基板11与大型的基板50的外框51连接而设置该连结部52。该项的详细内容参照图2详细叙述。
第二实施方式
在本实施方式中,参照图2~图4说明混合集成电路装置的制造方法。
参照图2,首先,关于在本实施方式中使用的引线框40及基板50进行说明。
首先,参照图2(A)及图2(B),说明在本实施方式中使用的引线框40的构成。图2(A)是在引线框40上设置的一个单元46的放大的平面图,图2(B)是引线框40的整体的剖面图。
引线框40通过对厚度例如0.5mm左右的铜或铝为主要材料的金属板进行冲压加工或蚀刻加工而形成。参照图2(A),单元46是由位于载置电路基板1 1的区域内一端的多个引线25组成。在图中,载置电路基板11的区域的周边用虚线表示。在这里,引线25在纸面上从左右两个方向朝向载置电路基板的区域延伸。而且,由于多个引线25通过从外框41延伸的连杆44互相连结,可以防止在制造工序的中途阶段的变形。在本实施方式中,由于引线25的端部固定在电路基板11的上面,所以引线25的顶端部延伸到电路基板11的内部区域。
参照图2(B),在长方形的引线框40上,如上所述构成的单元46多个分离进行配置,在这里,3个单元46配置在引线框40上。在本实施方式中,通过在引线框40上设置多个单元46而制造混合集成电路装置,引线25的固定或模具工序等一次进行,提高生产率。
并且,在引线框40的外框41上,在厚度方向贯通引线框40的第一定位孔42穿通设置。在这里,引线框40的4个角附近形成有4个第一定位孔42。该第一定位孔42具有后述的定位销54可以插入的大小,为了进行基板50与引线框40的对位而使用。在这里,圆形的第一定位孔42进行图示,但是该形状也可以是例如四边形等的多边形。
参照图2(C),对设置多个电路基板11的基板50进行说明。基板50的平面外形形状是与上述的引线框40大致相同大小的长方形状。而且,基板50通过对厚度例如1.5mm左右的铜或铝为主要材料的金属进行冲压加工或蚀刻加工而形成。多个电路基板11位于基板50的内侧,各个电路基板11经由连结部52与外框51连接成一体。在这里,纸面上的电路基板11的上侧的侧边经由两个连结部52固定在外框51上。而且,电路基板11的下侧的侧边也经由两个连结部52固定在外框51上。
在这里,与图2(B)所示的引线框40相同,在基板50的内侧设置有3个电路基板11。另外,电路基板11的位置与在引线框40设置的单元46的位置正确对应。即,当引线框40与基板50重叠时,在引线框40的单元46上设置的引线25的顶端部位于基板50的电路基板11的上面。
而且,在基板50的4个角附近,形成有贯通基板50设置的第二定位孔53。第二定位孔53的平面位置及大小与在引线框40上设置的第一定位孔42相同。
参照图2(D),在本实施方式中,上述构成的引线框40与基板50重叠连结。而且,在引线框40的第一定位孔42与基板50的第二定位孔53的两孔中,插入(嵌合)由铁或铝等金属组成的定位销54。定位销54插入全部的4个的第一定位孔42及第二定位孔53中。
这样,通过在第一定位孔42及第二定位孔中嵌合定位销54,就可以正确地调整基板50与引线框40的相对位置。即,在基板50的电路基板11的表面上,可以使引线框40的引线25的顶端部位于配置未图示的焊盘的位置。
而且,在本实施方式中,通过定位销54,可以使引线框40与基板50处于连结状态。因此,由于引线框40与基板50成为一体化的板状体,所以容易地搬运引线框40及基板50,而且,通过仅仅重叠引线框40与基板50,由于引线25的顶端部位于电路基板11上的焊盘上,所以可以正确且容易地进行引线25的对位。
而且,基板50的表面通过由铝等的无机填充物填充的环氧树脂组成的绝缘层12覆盖。另外,在引线框40与基板50的重叠工序中,优选绝缘层12处于B阶段(半固化)的状态。原因是使用B阶段的绝缘层12的粘着力、引线框40与基板50的粘结成为可能。
参照图3,对引线框40与基板50重叠后的单元46的构成进行说明。图3(A)是从上方观察到的1个单元46的平面图、图3(B)是图3(A)的B-B线的剖面图。
在1个单元46的内部,配置有1个电路基板11,从单元46的左右两侧向内侧延伸的引线25的顶端位于在电路基板11的表面上形成的焊盘13A的上部。
另外,上述的引线框40与基板50的重叠、也可以在电路基板11的表面上配置半导体元件等的电路元件、通过金属细线连接电路元件与导电图形13之后进行。而且,在电路基板11的表面进行配置半导体元件等之前,也可以使引线框40与基板50重叠。
而且,引线25与焊盘13A按照下面的方法进行连接。首先,把引线框40与基板50重叠,使引线25的顶端部位于焊盘13A的上部。接着,熔化在焊盘13A的表面上预先形成的焊料或者焊料膏,把引线25的顶端部固定在焊盘13A的表面上。在本实施方式中,如上所述,通过重叠引线框40与基板50,在多个单元46中,可以使引线25的顶端部位于焊盘13A的上部。因此,在熔化焊料连接引线25与焊盘13A的工序中,不需要用于保持引线25的夹具。
在上述的背景技术中,在每个电路基板11中,需要电路基板11与引线25的对位。在本实施方式中,如上所述,通过1组的引线框40与基板50重叠,对于多个电路基板11,可以在所定的位置配置、固定引线25。因此,可以大幅减少引线25的对位及固定所需要的时间、降低制造成本。
参照图4,接着,形成封固树脂14以至少覆盖电路基板11的表面,而且,分离固定引线25的电路基板11。图4(A)是本工序的剖面示意图,图4(B)是经过封固工序后的单元46的平面图。
参照图4(A),通过使上模22A及下模22B与引线25抵接,固定在模腔23的内部的电路基板11的位置。而且,从设置在模的浇口(未图示)向模腔23中注入树脂,封固电路基板11。另外,伴随着向模腔23的内部注入封固树脂,模腔23内部的空气经由未图示的浇口排到外部。在本工序中,使用热固性树脂的传递模或者使用热塑性树脂的注射模进行。而且,在本工序中,采用通过浇注封装封固树脂、仅在电路基板11的表面形成封固树脂14的方法,也可采用通过壳材进行封固。
而且,在本工序中,由于图2(C)所示的基板50上形成的多个电路基板11进行一次封固,所以可以简化封固工序。另外,通过把图2(C)所示的基板50的外框51夹持在上模22A及下模22A之间,可以固定在模腔23的内部的电路基板11的位置。因此,即使向模腔23中高压注入树脂,也可以防止由树脂的压力引起电路基板11的移动。
参照图4(B),上述的铸型工序完毕之后,把引线25从引线框40分离。而且,各个电路基板11也从基板50分离。在这里,由于形成多个电路基板11的基板50位于引线框40的下方,在图4(B)中未图示。
具体地,在设置连杆44处个别分离引线25。而且,例如,在由点划线表示的分离线L1的位置,分离连接部25,如图1所示的混合集成电路装置10从引线框40及基板50(未图示)分离。在这里,引线25的分离及电路基板11的分离可以通过使用冲压机进行冲压加工。另外,连接部52的切断也可以在封固树脂14的端面的部分进行。由此,连接部52露出面与封固树脂14表面成为同一表面,可以实现没有突起部的结构。
而且,在上述说明中,在进行电路基板11的封固后,分离各个电路基板11,但是,也可以从基板50分离电路基板11之后,进行封固工序。
Claims (6)
1.一种电路装置的制造方法,其是在电路基板的表面上装入由导电图形与电路元件组成的电路、把引线固定到由所述导电图形组成的焊盘的电路装置的制造方法,其特征在于,包括:准备与在表面上形成包括所述焊盘的所述导电图形的多个所述电路基板连结成一体的基板的第一工序;把所述电路元件电连接到各个所述电路基板的所述导电图形上的第二工序;通过把多个所述引线组成的引线框重叠到所述基板上、使所述引线的端部位于所述焊盘的上方、把所述引线固定到所述焊盘的第三工序;在把所述引线固定到所述电路基板的所述焊盘的状态下、从所述基板分离所述电路基板、且从所述引线框分离所述引线的第四工序。
2.如权利要求1所述的电路装置的制造方法,其特征在于,在所述第三工序中,把所述引线框重叠到所述基板上,通过在贯通所述引线框而设置的第一定位孔与贯通所述基板而设置的第二定位孔中嵌合定位销,对所述基板和引线框进行对位、且连结。
3.如权利要求1所述的电路装置的制造方法,其特征在于,所述基板和所述引线框具有大致相同的平面大小。
4.如权利要求1所述的电路装置的制造方法,其特征在于,在所述第四工序中,通过冲压加工,使所述电路基板及所述引线分离。
5.如权利要求1所述的电路装置的制造方法,其特征在于,在所述第三工序中,经由覆盖所述基板的表面的B阶段状态的绝缘层,所述引线框粘合到所述基板上。
6.如权利要求1所述的电路装置的制造方法,其特征在于,在所述基板与所述引线框连结的状态下,至少封固所述电路基板的表面。
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CN (1) | CN101026110B (zh) |
Cited By (3)
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CN102437061A (zh) * | 2011-11-30 | 2012-05-02 | 深圳市威怡电气有限公司 | 电子元件及其封装方法 |
CN104576619A (zh) * | 2013-10-23 | 2015-04-29 | 胜美达集团株式会社 | 电子器件以及电子器件的制造方法 |
WO2021063267A1 (zh) * | 2019-09-30 | 2021-04-08 | 华为技术有限公司 | 引线框架、封装集成电路板、电源芯片及电路板封装方法 |
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US9408301B2 (en) | 2014-11-06 | 2016-08-02 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9397017B2 (en) | 2014-11-06 | 2016-07-19 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US11437304B2 (en) | 2014-11-06 | 2022-09-06 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
EP3653027A4 (en) | 2017-07-13 | 2021-04-28 | CelLink Corporation | CONNECTING METHODS AND DEVICES |
JP2019067950A (ja) * | 2017-10-02 | 2019-04-25 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
US20190103342A1 (en) | 2017-10-04 | 2019-04-04 | Infineon Technologies Ag | Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same |
US11516921B2 (en) * | 2019-09-20 | 2022-11-29 | Manaflex, Llc | Reel-to-reel lamination methods and devices in FPC fabrication |
WO2022072886A1 (en) | 2020-10-02 | 2022-04-07 | Cellink Corporation | Forming connections to flexible interconnect circuits |
WO2022072338A1 (en) | 2020-10-02 | 2022-04-07 | Cellink Corporation | Methods and systems for connecting a flexible interconnect circuit |
US20220311103A1 (en) | 2021-03-24 | 2022-09-29 | Cellink Corporation | Multilayered flexible battery interconnects and methods of fabricating thereof |
WO2023164486A1 (en) | 2022-02-22 | 2023-08-31 | Cellink Corporation | Flexible interconnect circuits and methods of fabrication thereof |
DE102022202928A1 (de) * | 2022-03-24 | 2023-09-28 | Brose Fahrzeugteile SE & Co. Kommanditgesellschaft, Würzburg | Elektronikeinheit für einen elektromotorischen Kältemittelverdichter |
WO2023201030A2 (en) | 2022-04-15 | 2023-10-19 | Cellink Corporation | Flexible interconnect circuits for battery packs |
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- 2006-02-22 JP JP2006044882A patent/JP4969113B2/ja active Active
- 2006-12-05 CN CN2006101531751A patent/CN101026110B/zh not_active Expired - Fee Related
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2007
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102437061A (zh) * | 2011-11-30 | 2012-05-02 | 深圳市威怡电气有限公司 | 电子元件及其封装方法 |
CN104576619A (zh) * | 2013-10-23 | 2015-04-29 | 胜美达集团株式会社 | 电子器件以及电子器件的制造方法 |
US9646948B2 (en) | 2013-10-23 | 2017-05-09 | Sumida Corporation | Electronic component and method for manufacturing electronic component |
CN104576619B (zh) * | 2013-10-23 | 2018-01-09 | 胜美达集团株式会社 | 电子器件以及电子器件的制造方法 |
WO2021063267A1 (zh) * | 2019-09-30 | 2021-04-08 | 华为技术有限公司 | 引线框架、封装集成电路板、电源芯片及电路板封装方法 |
US11887918B2 (en) | 2019-09-30 | 2024-01-30 | Huawei Technologies Co., Ltd. | Lead frame, packaged integrated circuit board, power chip, and circuit board packaging method |
Also Published As
Publication number | Publication date |
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US20070193027A1 (en) | 2007-08-23 |
JP2007227502A (ja) | 2007-09-06 |
US7521290B2 (en) | 2009-04-21 |
CN101026110B (zh) | 2011-03-23 |
JP4969113B2 (ja) | 2012-07-04 |
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