CN104517952B - 功率半导体模块和用于制造功率半导体模块的方法 - Google Patents
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Abstract
本发明涉及一种功率半导体模块。根据本发明的一个示例该功率半导体模块具有电路板,该电路板具有布置在电路板的顶面上的结构化的第一金属结构和至少一个第二金属结构。在电路板的顶面上布置至少一个无壳体的半导体芯片,半导体芯片具有多个接触电极,这些接触电极又通过焊线与第一金属结构的相应的接触片在电路板的顶面上相连接。接触电极和相应的接触片的第一部分在运行时是高电压接通的。所有高电压接通的接触片通过内层连接与第二金属结构导电地连接。绝缘层完全覆盖芯片和围绕该芯片的电路板的分隔区域,其中所有高电压接通的接触片和内层连接被该绝缘层完全覆盖。多个接触电极和相应的接触片的第二部分在运行时处于低电压。
Description
技术领域
本发明涉及功率半导体模块领域、其构造和制造方法。
背景技术
现代功率半导体模块除了包括功率电子半导体元件(尤其是功率半导体开关)外还包括作为主要构件的集成电路(ICs)。其例如用于接通功率半导体开关或者用于测量电流或者温度。在这种情况下通常被称为“智能功率半导体模块”(“智能功率模块”,缩写:IPM)。这种IPM包括通常附加于功率电子器件所需的驱动电路(栅极驱动器)等。功率半导体模块中的常见工作电压能够处于从几百伏到几千伏的范围。这些高电压施加在集成电路(例如栅极驱动器)的外部触点(高电压触点)上,所以这些集成功能块需要有效的绝缘。因此分别根据应用且由此附带的标准,必须维持集成电路的高电压触点和处于低电位的通电部分之间的间距(所谓的空气间隙和漏电间隙),从而确保了充分绝缘。多个供以高电压的集成功能块的彼此绝缘同样确定相互间隔。如果在电路板(印刷电路板)上布置多个这种集成电路,那么电路板上的功能块的横向间距需要很大的需求空间。而追求越来越紧凑的模块需要减少电路板表面积。
在维持相等的绝缘的情况下(即在维持相等的漏电间隙的情况下)确保所需电路板表面积的可能性在于,通过具有小间隔(间隔=导线间距)或者BGA(BGA=球栅阵列)的壳体来使用常规的SMD(SMD=表面贴装器件)集成电路壳体。
当然,该方法需要额外的绝缘层,这些芯片壳体必须通过该绝缘层被遮盖,这将产生一个额外的操作步骤。此外在集成电路之下实现制作绝缘层只能是昂贵的。由该方法获得的电路板上的表面积相比于起始位置只是微小的且因此与该绝缘要求的明显更高的费用(附加的绝缘层)相对。
发明内容
基于本发明的任务在于,提供一种在功能性相同的情况下具有降低的空间需求的功率半导体模块以及一种相应的制造方法。通过根据本发明功率半导体模块和用于制造功率半导体模块的方法实现该任务。
本发明的一个方面涉及一种功率半导体模块。根据本发明的一个示例该功率半导体模块具有电路板,所述电路板在包括布置在所述电路板的顶面上的结构化的第一金属结构(Metallisierung)和至少一个第二金属结构,所述第二金属结构在垂直的方向处于第一金属结构下方、平行于所述第一金属结构布置并与所述第一金属结构绝缘。在所述电路板的所述顶面上布置至少一个无壳体的半导体芯片,所述半导体芯片具有多个接触电极,所述多个接触电极又通过多条焊线与第一金属结构的相应的接触片在所述电路板的所述顶面上相连接。接触电极和相应的接触片的第一部分在运行期间是高电压接通的。所有高电压接通的接触片通过内层连接与第二金属结构导电地连接。绝缘层完全覆盖该芯片和围绕该芯片的电路板的分隔区域,其中,所有高电压接通的接触片和内层连接被绝缘层完全覆盖。所述多个接触电极和相应的接触片的第二部分在运行时处于低电压。
本发明的第二个方面涉及一种用于制造功率半导体模块的方法。根据本发明的一个示例该方法包括为电路板提供顶面和底面,其中,在该顶面和底面上布置结构化的金属结构,以及为至少一个布置在电路板的顶面上的无壳体的半导体芯片提供多个接触电极,所述多个接触电极通过多条焊线与结构化的金属结构的相应接触片在电路板的顶面上相连接。所述接触电极和所述相应的接触片的第一部分在运行时是高电压接通的,并且所有高电压接通的接触片通过内层连接与所述结构化的金属结构在所述底面上在内层中导电地连接。如此施加绝缘层,以使得其完全覆盖芯片和围绕所述芯片的所述电路板的分隔区域,其中,所有高电压接通的接触片和内层连接被该绝缘层完全覆盖。
附图说明
下文根据附图中所示的示例进一步阐述本发明。附图中所示的图不一定按照比例绘制且也不意味着限制本发明。相反重点在于,阐述本发明所基于的原理。
图1A示出了带有功率半导体衬底和控制电路板的功率半导体模块的一个实施例的纵剖图;
图1B示出了带有功率半导体衬底和控制电路板的功率半导体模块的另一个实施例的纵剖图;
图2示出了包括多个其上以标准的SMD技术布置有具有壳体的半导体芯片的控制电路板的示例的俯视图;
图3说明了相比于图2的示例的空间节省,由此实现了,使用具有无壳体的驱动器集成电路和附加的绝缘的控制电路板;
图4A示出了通过具有根据图2的标准SMD驱动器的控制电路板(水平的绝缘间距)的部分的截面图;
图4B示出了通过根据图3的控制电路板(在垂直方向上通过该电路板绝缘)的部分的剖视图;以及
图5示出了具有多层的电路板实施例的剖视图。
具体实施方式
在附图中相同的附图标记表示相同的构件或者具有相同或者相似含义的信号。
在以下所述的描述中涉及所附的图,其中示出了多个专门的实施例以用于阐述。除非另有说明,在此所述的多个不同的实施例的标记当然能够相互结合。
图1A示出了通过根据本发明的示例的功率半导体模块1的截面图。通过控制电路板10的具体设计方案可能的是,不仅多个功率电子构件而且该电子控制装置集成在紧凑的壳体中(例如英飞凌的2B),其至今仅能容纳功率电子构件(不包括控制电路板)。该电路板10和功率半导体衬底5在图1中所示的示例中重叠地布置。其中模块1包括带有其上安装多个电子构件的电路板10,这些电子构件根据之后的图在下面进一步阐明,以及还包括功率半导体衬底5,该功率半导体衬底5能够布置在冷却体7上。该功率半导体衬底5在其顶面5o具有结构化金属结构12,其中该顶面在该衬底面向该电路板10的那侧。在该功率半导体衬底5上能够布置不同的多个功率半导体元件(例如,多个IGBT或者多个二极管)。
该功率半导体衬底5尤其能够是DCB衬底(DCB=直接铜键合)、DAB衬底(DAB=直接铝键合)或者AMB衬底(AMB=活性金属钎焊),其具有由陶瓷构成的绝缘载体。另一个功率电子衬底是所谓的IMS衬底(IMS=绝缘金属衬底),其中金属载体通过薄的绝缘层与其金属结构绝缘。在该载体的两侧(绝缘金属或者陶瓷)布置金属结构。顶面的金属结构(顶面5o)是结构化的且因此具有多个导体电路、焊盘和焊点等。底面的金属结构(底面5u)通常为整个区域的。不同于功率半导体衬底该电路板10不具有陶瓷载体而是具有对印刷电路板(印刷电路板,PCB)来说常规的基材,例如FR1到FR5,其中FR4和FR5(两者均是玻璃纤维增强的环氧树脂)是很常用的。
在该功率半导体衬底5的顶面5o上安装另一个接触销18(例如通过连接件19),其中在封闭的模型壳体中该电子器件在模型中通过这种接触销被接触。因此该接触销从壳体顶面伸出并且作为模块1的外部负载连接端(“电源端子”)。接触销18能够穿过电路板10地实施,为此在该电路板中设置相应的穿孔。如果需要该接触销18与电路板金属结构导电地接触,则金属化该孔眼且其中的接触销18处于与该金属结构电接触的状态。于是该穿孔被称作接触穿孔17。如果需要通过该电路板10不导通该接触销18,那么不金属化该穿孔,而是设计为绝缘的。于是该穿孔被称作通孔16。除了安装在该功率半导体衬底5上的接触销18外,在该电路板10上同样能够通过连接件19’安装接触销18’,连接件19’同样能够从封闭的模块中伸出。其中这些接触销能够如此设置,于是其在该模块外部都伸出相同的距离。因此在该模块中存在两个电压区,高电压区40和低电压区41。电压区40和41相互分离,如图1A中由点划线所示。该分离可能通过绝缘层30,其在后面还会详细描述。
以图1A中所示的方式布置该(驱动器)电路板10的优点在于,即该模块壳体不需要外部改变就能够装备得非常密封。这样该控制电路板可以安装在小的模块壳体中,其中到目前为止只有功率半导体衬底空间(其中该控制电路板从外部连接该模块)。为了该构造的机械稳定性还能够选择在功率半导体衬底5和电路板10之间嵌入加强板。模块壳体的顶面能够由壳体罩构成,穿过该壳体罩地实施接触销。此外该罩能够具有开口,通过该开口能够往该完成的模块中填充填料(例如硅凝胶),以在必要时在该功率半导体衬底5上覆盖独立的构件。该填料还用于提高绝缘电阻。
图1B示出了通过根据本发明的另一个实施例的类似于图1A所构建的功率半导体模块1的截面图。但是在此其区别存在于,即该电路板10的所有高电压导通的部分都铺有绝缘层,由此在该电路板10的顶面10o上不存在其他裸露的高电压导通的部分。因此该高电压区40限制在该电路板10的底面10u上,从而高电压区和低电压区通过该电路板本身相互分离或者绝缘。于是在电路板顶面上不再必须保留水平的绝缘间距。
下文进一步阐述电路板的设计方案的具体示例。为此图2中示出了一种已知的方案的实施例(以俯视图的方式),其中具有壳体25的半导体芯片25布置在电路板10(PCB)上。在此这些半导体芯片25布置在壳体(芯片封装)中,例如型号SOIC-16(SOIC意味着“小外形集成电路(small outline IC)”并表示SMD壳体形式)。这些芯片的电子连接触点26(还有引脚和端子)从芯片壳体中伸出且焊接在电路板的顶面金属结构12上。在这些触点上部分地施加高电压,因此需要有效的绝缘。在该实施例中如此实现绝缘,即这些彼此具有相应的足够横向绝缘间距DISO的集成电路布置在该电路板上。该横向的绝缘间距避免过高的泄露电流。因此所需的最小间距以及芯片25的壳体大小为电路板10确保必须存在的最小尺寸,以保持集成电路的横向绝缘间距。此外示意性地示出了可选的半导体元件6(例如二极管)。
图3示出了根据本发明的示例的电路板10的顶面10o上的俯视图。其中该具有壳体25的传统芯片由无壳体的芯片20(英文“裸露的芯片”)代替。芯片20具有接触片22,其通过多条焊线14与相应的接触片23在电路板10的顶面上的结构化金属结构11上连接。此外在电路板10上能够布置另一个可选的半导体元件。该无壳体的芯片20具有比图1的芯片25的芯片壳体小得多的尺寸。但是使用“裸露的芯片”需要另一种确保绝缘的方案。
由绝缘层30提供所需的绝缘,该绝缘层30不仅封装整个无壳体的芯片20,还完全封装包括接触电极22、接触片23、焊线14以及孔13(见图4B)的连接。绝缘层30沿着包围无壳体芯片20的分隔区域31延伸且例如通过已知的“围坝与填充(Dam and Fill)”方法来制造。绝缘和具有其接触点(Ankontaktierung)的芯片的共同体被称作“绝缘的半导体芯片”21。该绝缘层30实际上是芯片和其接触点的封装。如此封装的“裸露的芯片”远远比图1中的半导体芯片的壳体(例如,SOP或者SOPP封装)紧凑。由此在这些封装的半导体芯片21之间维持相同的绝缘间距的情况下该电路板大小显著减小,因为不再需要占用空间的芯片壳体。
图4A和4B中示出了根据图2或者图3的示例的剖视图。其中图4A示出了电路板10,该电路板10具有顶面10o和底面10u,其中该顶面10o和/或底面10u具有结构化金属结构12。在顶面10o上安装至少一个具有壳体25的芯片,该壳体的电触点26与该电路板10导电地连接。除了具有壳体25的芯片以外在顶面10o上能够安装可选的其他的多个半导体元件6(例如二极管)。在该电路板10的底面10u上同样能够安装可选的半导体元件6。具有在该电路板10的顶面10o上的壳体25的芯片能够通过孔13与该底面10u导电地连接。因为在具有壳体25的芯片的电触点26的部分上施加高电压(在芯片的右侧上的实施例)且其没有绝缘,产生了高电压区40,在高电压区40内不允许与低电压接触。该高电压区40在图4A中以阴影示出。在此,具有壳体25的芯片通过该孔13由该电路板10的底面10u提供高电压,因此该底面10u同样是高电压区40的部分。与之相对存在低电压区41,其位于具有低电压的电触点6。该低电压区41在图4A中以波浪图案示出。两个电压区适用于有效分离来避免泄露电流或者短路。此外该方案与具有壳体25的多个芯片相互存在一定的间距DISO(参考图2),这导致过大的电路板大小。
图4B示出了图3的俯视图的纵剖图,只是具有更多细节。图4B示出了具有顶面10o和底面10u的电路板10。不仅该顶面10o而且该底面10u能够具有结构化金属结构12。在顶面10o上布置至少一个无壳体的芯片20。该芯片20具有一个或者多个具有相应的接触片23的公共焊片(Kon-Bondpads)22,其与处于电路板10上的相应的接触片23通过焊线14电连接。所有高电压导通的接触片23通过孔13与电路板10的底面10u的结构化金属结构12电连接。在多层电路板上该电势还在中间层上而不是底面上接通(参考图5)。不仅在该电路板10的顶面10o上而且在该电路板10的底面10u上能够布置其他多个功率半导体元件6。为了对“裸露的芯片”绝缘,在有限的区域31上安装绝缘层30,该区域包括无壳体的芯片20和其触点(即接触电极22、接触片23、焊线14和所用的孔13)。因此绝缘芯片21的所有高电压导通的部分由该绝缘层封装。
在图4A中已经提到的电压区现在显示出不同。通过该绝缘层30的绝缘在电路板10的整个顶面10o上没有裸露的高电压导通的部分,因此该高电压区40限制在该电路板10的底面10u上(在多层电路板的情况下必要时在中间层上)。因此电路板10的所有顶面10o能够归为低电压区41,因为所有高电压导通的部分都是封装的。那么图4A中的实施例需要的用于分离电压区的横向绝缘间距在图4B中的实施例中不再需要。相反该电路板10本身构成电压区的绝缘或者分离介质,这整体来说允许明显更为紧凑的构建方式。
图5示出了如图4B已经示出的电路板10的侧剖面。在该实施例中该电路板是所谓的多层电路板,其在当前情况下具有三个金属化层。于是该电路板10具有由印刷电路板基材(例如FR4)组成的第一层11a以及同样由印刷电路板基材组成的第二层11b。这两个层11a和11b通过(结构化的)金属化层10z连接。因此共提供了三个金属化层(顶面、内部、底面)。该电路板10还能够包括超过三层。电路板10的顶面10o与其底面10u或者内层10z的内部连接如前述实施例中通过孔13实现。如在图4A和4B已经示出的一样该绝缘层包括所有的无壳体半导体芯片20以及其触点和为此所使用的一个或者多个孔13,从而在电路板10的顶面10o上没有暴露无封装的高电压导通的构件。
Claims (8)
1.功率半导体模块(1),其包括:
电路板(10),所述电路板具有布置在所述电路板的顶面(10o)上的结构化的第一金属结构(12)和至少一个第二金属结构,所述第二金属结构在垂直的方向处于所述第一金属结构的下方、平行于所述第一金属结构布置并与所述第一金属结构绝缘;
至少一个无壳体的半导体芯片(20),所述半导体芯片布置在所述电路板(10)的所述顶面(10o)上,具有多个接触电极(22),所述多个接触电极(22)通过多条焊线(14)与所述第一金属结构(12)的相应的接触片(23)在所述电路板(10)的所述顶面(10o)上相连接,其中,所述多个接触电极(22)和所述相应的接触片(23)的第一部分在运行时为高电压导通的,并且其中,高电压导通的接触片通过内层连接与所述第二金属结构导电地连接;
绝缘层(30),所述绝缘层(30)完全覆盖所述芯片(20)和围绕所述芯片(20)的所述电路板(10)的分隔区域(31);
其中,所述高电压导通的接触片(23)和所述内层连接被所述绝缘层(30)完全覆盖;并且
其中,所述多个接触电极(22)和所述相应的接触片(23’)的第二部分在运行时处于低电压。
2.根据权利要求1所述的功率半导体模块,其中,所述电路板(10)安装在具有至少一个布置在其上的功率半导体元件(6)的功率半导体衬底(5)上,其中,处于所述电路板(10)的底面(10u)上的结构化的金属结构与所述功率半导体衬底(5)和/或所述功率半导体元件(6)导电地连接。
3.根据前述权利要求中任一项所述的功率半导体模块,其中,至少另一个SMD元件布置在所述电路板(10)的所述顶面(10o)和/或所述底面(10u)上。
4.根据权利要求3所述的功率半导体模块,其中,多个附加的元件安装在所述电路板(10)的所述顶面(10o)上,并且围绕所述多个元件的所述电路板(10)的分隔区域(31)被所述绝缘层(30)完全覆盖。
5.用于制造功率半导体模块的方法,其包括以下步骤:
为电路板(10)提供顶面(10o)和底面(10u),其中,在所述顶面和所述底面上布置结构化的金属结构(12);
为至少一个布置在所述电路板(10)的顶面(10o)上的无壳体的半导体芯片(20)提供多个接触电极(22),所述多个接触电极(22)通过多条焊线(14)与所述结构化的金属结构(12)的相应的接触片(23)在所述电路板(10)的所述顶面(10o)上相连接,其中,所述接触电极(22)和所述相应的接触片(23)的第一部分在运行时为高电压导通的,并且其中,所有高电压导通的接触片(23)通过内层连接与所述结构化的金属结构(12)在所述底面(10u)上或者内层上导电地连接;以及
施加绝缘层(30),所述绝缘层(30)完全覆盖所述芯片和围绕所述芯片(20)的所述电路板(10)的分隔区域(31),其中,所有高电压导通的接触片(23)和所述内层连接被所述绝缘层(30)完全覆盖。
6.根据权利要求5所述的方法,进一步包括:
提供功率半导体衬底(5);
提供功率半导体元件(6)并且将所述功率半导体元件(6)施加在所述功率半导体衬底(5)上;
在所述功率半导体衬底(5)上施加所述电路板(10),其中,处于所述电路板(10)的所述底面(10u)上的所述结构化的金属结构(12)与所述功率半导体衬底(5)和/或所述功率半导体元件(6)导电地连接。
7.根据前述权利要求中任一项所述的方法,进一步包括:
提供至少另一个功率半导体元件(6)并且将其施加在所述电路板(10)的所述顶面(10o)和/或所述底面(10u)上。
8.根据权利要求7所述的方法,进一步包括:
施加绝缘层(30),所述绝缘层(30)完全覆盖所述另一个功率半导体元件(6)和围绕所述功率半导体元件(6)的所述电路板(10)的分隔区域(31)。
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DE102017101185B4 (de) | 2017-01-23 | 2020-07-16 | Infineon Technologies Ag | Ein Halbleitermodul umfassend Transistorchips, Diodenchips und Treiberchips, angeordnet in einer gemeinsamen Ebene, Verfahren zu dessen Herstellung und integriertes Leistungsmodul |
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US5444297A (en) * | 1992-06-17 | 1995-08-22 | Mitsubishi Denki Kabushiki Kaisha | Noise resistant semiconductor power module |
US6359331B1 (en) * | 1997-12-23 | 2002-03-19 | Ford Global Technologies, Inc. | High power switching module |
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US20150092376A1 (en) | 2015-04-02 |
US9924594B2 (en) | 2018-03-20 |
DE102013219780A1 (de) | 2015-04-02 |
CN104517952A (zh) | 2015-04-15 |
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