CN104319268B - 一种晶片型二极体封装元件及其制法 - Google Patents

一种晶片型二极体封装元件及其制法 Download PDF

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CN104319268B
CN104319268B CN201410605779.XA CN201410605779A CN104319268B CN 104319268 B CN104319268 B CN 104319268B CN 201410605779 A CN201410605779 A CN 201410605779A CN 104319268 B CN104319268 B CN 104319268B
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diode
chip
lead frame
coated
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CN104319268A (zh
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连清宏
黄兴祥
黄兴材
许鸿宗
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SFI Electronics Technology Inc
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SFI Electronics Technology Inc
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
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Abstract

本发明公开了一种晶片型二极体封装元件及其制法，晶片型二极体封装元件不具有外引脚，包括一封胶体，其内部包裹一颗以上的二极体晶片，每颗二极体晶片的底部及顶部，分别与两片呈180度镜射的导线架联结，除构成晶片型二极体封装元件的内电极之外，与该封胶体的外部两侧的外端电极，也构成电性接触，使得每颗二极体晶片通过此结构而产生半导体二极体特性；所述晶片型二极体封装元件的制法，使用不含铅制程，制得不具有外引脚的晶片型二极体封装元件，可满足国际上各项环保要求，不但可解决外引脚的尺寸精度问题，而且可提高封装速度与封装稳定度。

Description

一种晶片型二极体封装元件及其制法
技术领域
本发明涉及一种二极体封装元件，尤指一种不具外引脚的晶片型二极体封装元件及其制法。
背景技术
如图1所示，完成封装的IC或半导体封装元件(下文泛称半导体封装元件)80，在封装制程中，导线架81、金线或导线(下文泛称金线)82、封装胶83是三项重要原料。
将封装前的IC或半导体晶片(下文泛称半导体晶片)84黏结固定于导线架81的晶片座上之后，半导体晶片84与导线架81间必须联结金线82，使半导体晶片84与导线架81形成电性联结，再使用封装胶83进行封胶，使得导线架81和半导体晶片84与外界隔绝后，半导体封装元件80的两端(或底部)将留下从导线架81延伸出来的外引脚(或接触点)85，经测试可用于将半导体晶片84内部功能传输至外部衔接的电路板，即制成引脚插入型或表面黏着型封装的半导体封装元件80。
封装制程中使用的导线架81，是半导体封装元件80完成封装的关键，对不同型式的半导体晶片84进行封装，就需要使用不同形式的导线架81。
例如，如图2所示，当所述半导体晶片84是一种由P型半导体与N型半导体结合成的PN型半导体二极体晶片(下文简称二极体晶片)时，使用不同形式的导线架81封装完成半导体二极体封装元件(下文简称二极体封装元件)90，就具有各种不同形态的外引脚85。
所以，现有技术中的二极体封装元件90都是具有外引脚85，但二极体封装元件90具有外引脚85的缺点，却在于外引脚85的尺寸精度往往会影响后续进行表面黏着技术(SMT)制程的稳定度。
发明内容
鉴于现有技术存在的上述问题，本发明要解决的问题是，提供一种芯片型二极管封装元件，解决现有技术中的二极体封装元件外引脚的尺寸精度问题。
为解决上述问题，本发明提供一种不具外引脚的晶片型二极体封装元件，其结构，至少包括：一颗二极体晶片；一个封胶体，将所述二极体晶片包裹在其内部；两片相同结构的导线架电极，也包裹在该封胶体的内部，且以180度镜射布置方式，将其中一端各自连接于所述二极体晶片的上端部或下端部，另一端各自延伸到该封胶体的其中一侧的侧端面表面；两个外端电极，各自被覆在该封胶体其中一侧的侧端部，且与所对应的导线架电极分别构成电性连接。
作为优选实施例，本发明的晶片型二极体封装元件，可使用多颗二极体晶片且制成具阵列(Array)型态的晶片型二极体封装元件。
作为优选实施例，所述二极体晶片选自瞬态电压抑制二极体(TVS Diode)、肖特基二极体(Schottky Diodes)、开关二极体(Switch Diode)、齐纳二极体(Zener Diode)或整流二极体(Rectifiers Diode)中的一种。
作为优选实施例，所述封胶体为陶瓷材料或塑胶材料。
作为优选实施例，所述二极体晶片及其所对应的两片导线架电极之间，以无铅导电膏构成一导电胶层，且将所述二极体晶片及每片导线架电极联结到一起。
作为优选实施例，所述无铅导电膏的成分，选自银(Ag)、锡(Sn)、铜(Cu)、金(Au)、镍(Ni)、钯(Pd)或铂(Pt)中的单一成分或其两种以上成分的混合。
作为优选实施例，所述外端电极的材质，选自银(Ag)、金(Au)、铜(Cu)、镍(Ni)、钯(Pd)或铂(Pt)中的单一成分或其两种以上成分的混合，或其金属合金。
作为优选实施例，所述外端电极是以涂布、沾覆、蒸镀薄膜或溅镀薄膜制程制作。
本发明的另一主要目的在于提供一种晶片型二极体封装元件的制法，适用于制成不具外引脚的二极体封装元件，包括以下步骤：
1)使用两片呈180度镜射且相同结构的导线架冲制件，该导线架冲制件设有一片以上导线架，且设有两个或以上的定位孔，供两片相同结构的导线架冲制件翻转180度后利用定位孔对位；
2)对步骤1)的导线架冲制件的导线架，在联结二极体晶片的特定区域印上或点上无铅导电膏；
3)采用固晶机对二极体晶片植晶，经烘烤使两片呈180度镜射的导线架分别结合于二极体芯片的底部和顶部；
4)进行封胶及制得内部包裹二极体晶片及两片呈180度镜射的导线架的封胶体，且使得所述导线架成为所述封胶体的内电极；
5)施以涂布、沾银或薄膜制程，使得所述封胶体的两侧端部各自形成一外端电极，且与该封胶体的内电极构成电性连接；从而制得无外引脚的晶片型二极体封装元件。
本发明的晶片型二极体封装元件，是首创于封装后不留外引脚的二极体封装元件，具有以下有益效果：
1.二极体封装元件的外观，呈不留外引脚的晶片型结构，解决现有技术的外引脚的尺寸精度问题；
2.二极体封装元件产生半导体二极体特性的结构，在于二极体封装元件的内部，首创由两片相同结构的导线架以180度镜射的布置方式构成内电极，而二极体封装元件的外部两侧，具有外端电极，且与内电极电性接触，通过此结构而产生半导体二极体特性，具结构简单的特点；
3.不使用含铅锡膏的有铅制程，以无铅导电膏作为连接半导体二极体与导线架的连接材料，且制成无铅晶片型二极体封装元件；
4.二极体封装元件的外端电极，是以涂布、沾银、薄膜制程等方式制作，具制程简单及节省成本的特点；
5.二极体封装元件的制法，可使用单颗二极体晶片制成，或使用多颗二极体晶片且布置成阵列(Array)制成SMD型二极体封装元件，具多样用途晶片型二极体封装元件供选用的特点。
附图说明
图1为完成封装的IC或半导体封装元件的局部剖面图。
图2为现有技术中的二极体封装元件具有各种不同形态外引脚的说明图。
图3为本发明的晶片型二极体封装元件示意图。
图4为本发明的晶片型二极体封装元件在封装制程中使用两个相同导线架固定二极体的示意图。
图5为本发明的晶片型二极体封装元件在未制作外部端电极之前的半成品局部剖面图。
图6为本发明的晶片型二极体封装元件的局部剖面图。
图7为本发明的另一种型态晶片型二极体封装元件示意图。
附图标记
10 二极体封装元件 20 二极体晶片
30 导线架冲制件 31 导线架
33 导线架电极 35 定位孔
40 无铅导电膏 41 导电胶层
50 封胶体 60 外端电极
80 IC或半导体封装元件 81 导线架
82 金线 83 封装胶
84 IC或半导体晶片 85 外引脚
90 二极体封装元件
具体实施方式
如图3所示，本发明的二极体封装元件10，于两端具有外端电极60，且外观不留外引脚，本文定义为晶片型二极体封装元件10。
配合图4至图6所示，本发明的晶片型二极体封装元件10基本构造，至少包括一颗二极体晶片20、两片导线架电极33、一个封胶体50及两个外端电极60。
其关键技术在于：所述二极体晶片20及两片导线架电极33包裹于该封胶体50的内部，且该两片导线架电极33具相同结构，选自相同导线架元件，所以，该两片相同结构的导线架电极33，得以相对呈180度旋转镜射(下文简称为180度镜射)的布置方式，一端分别连接于所述二极体晶片20的上端部及下端部，另一端则各自延伸到该封胶体50的其中一侧的侧端面表面，且与被覆在该封胶体5侧端部的外端电极60，分别构成电性连接，使得本发明的二极体封装元件10通过此结构而产生半导体二极体特性。
为简洁说明，本文根据上面所述，将该两片导线架电极33与二极体晶片20及封胶体50三者之间的结构关系，定义为该两片导线架电极33构成本发明的晶片型二极体封装元件10的内电极，且与外端电极60构成电性连接，使得所述二极体晶片20产生半导体二极体特性。
如图7所示，本发明的晶片型二极体封装元件10的另一种具体实施例，至少包括一封胶体50包裹两颗以上(含两颗)二极体晶片20，每颗二极体晶片20各自对应两片导线架电极33构成内电极，且与所对应的两个外端电极60构成电性连接。
本发明的二极体晶片20，可选自瞬态电压抑制二极体(TVS Diode)、肖特基二极体(Schottky Diodes)、开关二极体(Switch Diode)、齐纳二极体(Zener Diode)或整流二极体(Rectifiers Diode)种的一种，但不以此为限，其他半导体晶粒植晶制程也都适用。
所述封胶体50可为陶瓷材料或塑胶材料，优选为使用环氧树脂。
如图4至图6所示，所述二极体晶片20及两片导线架电极33之间，使用无铅导电膏40构成一导电胶层41，将所述二极体晶片20及每片导线架电极33联结一起。
所述无铅导电膏40的成分，包含无铅导电金属，可选自银(Ag)、锡(Sn)、铜(Cu)、金(Au)、镍(Ni)、钯(Pd)或铂(Pt)中的单一成分或其两种以上成分的混合，但不以此为限。
所述外端电极60是以涂布、沾覆、蒸镀薄膜或溅镀薄膜制制作，其材质可选自银(Ag)、金(Au)、铜(Cu)、镍(Ni)、钯(Pd)或铂(Pt)中的单一成分或其两种以上成分的混合，或是其金属合金，但不以此为限。
据此，本发明的晶片型二极体封装元件10，可依据不同用途，使用单颗二极体晶片20制成，或使用多颗二极体晶片20且布置成阵列(Array)制成SMD型二极体封装元件。
如图4所示，本发明的晶片型二极体封装元件10制法，需预制一种导线架冲制件30，该导线架冲制件30的结构，设有一片以上(含一片)的导线架31，且设有两个或以上的定位孔35。关键技术在于：两片相同结构的导线架冲制件30翻转180度后，利用定位孔35的对位，可以相互呈180度镜射布置，有利于设计自动封装设备进行大量生产。
本发明的晶片型二极体封装元件10的制法，适用于制成含单颗或多颗二极体晶片20的晶片型二极体封装元件10，以下举含单颗二极体晶片20作具体说明，其步骤包括：
1.放置导线架冲制件30；
如图4所示，使用两片呈180度镜射的导线架冲制件30，且利用所设计的定位孔35准确定位。
2.点胶；
如图4所示，对导线架冲制件30的导线架31用于固定联结二极体晶片20的特定区域，印上或点上无铅导电膏40；
3.植晶及焊接；
如图4所示，采用固晶机对二极体晶片20植晶，且使二极体晶片20的底部与其中一片导线架31之间充满无铅导电膏40，二极体晶片20的顶部与另一片呈180度镜射的导线架31之间也充满无铅导电膏40，经烘烤后，使铅导电膏40硬化成导电胶层41，使得两片呈180度镜射的导线架31分别结合于二极体芯片20的底部和顶部；
4.封胶及制作内电极；
如图5所示，将完成焊接导线架31的二极体晶片20放入封装模中，经灌入半融化树脂及硬化后，制得内部包裹二极体晶片20及两片呈180度镜射的导线架31的封胶体50，经去除残胶及修整后，使得两片呈180度镜射的导线架31的一端各自延伸到该封胶体50的其中一侧的侧端面表面，而成为该封胶体50的导线架电极33，或称为晶片型二极体封装元件10的内电极；
5.制作外端电极；
如图5所示，接着对该封胶体50的两侧端部，施以涂布、沾银或薄膜制程，使该封胶体50的两侧端部形成外端电极60，且与为该封胶体50的导线架电极33(或称内电极)构成电性连接。
6.制得无外引脚的晶片型二极体封装元件10；
如图3所示或图7所示，成品经测试后，具备半导体二极体特性，即制得一种无外引脚的晶片型二极体封装元件10。
本发明的晶片型二极体封装元件10的制法，不使用含铅锡膏的有铅制程，可满足国际上各项环保要求，且所制成的二极体封装元件不具有外引脚，不但可解决现有技术的外引脚的尺寸精度问题，而且可提高封装速度与封装稳定度。

Claims (2)

1.一种晶片型二极体封装组件的制法，使用多颗二极体晶片制成不具外引脚且具阵列型态的晶片型二极体封装组件，其特征在于，包括以下步骤：
1)使用两片相同结构的导线架冲制件，每片导线架冲制件设有二片以上导线架，且设有两个或以上的定位孔，供两片相同结构的导线架冲制件相对呈180度旋转镜射后利用定位孔对位；
2)对步骤1)的导线架冲制件的每一片导线架，在联结二极体晶片的特定区域印上或点上无铅导电膏；
3)采用固晶机对二极体晶片植晶，经烘烤使两片呈180度旋转镜射的导线架分别结合于所对应的二极体晶片的底部和顶部；
4)进行封胶及制得内部包裹两颗以上呈阵列型态布置的二极体晶片及每颗二极体晶片的底部和顶部还结合两片相对呈180度旋转镜射的导线架的封胶体，且使得每颗二极体晶片所结合的导线架成为所述封胶体的内电极；
5)施以涂布、沾银或薄膜制程，使得所述封胶体的相对两侧端部各自形成呈阵列型态布置的外端电极，且两个相对外端电极与该封胶体内部对应的内电极构成电性连接；从而制得无外引脚且具阵列型态的晶片型二极体封装组件。
2.根据权利要求1所述的晶片型二极体封装组件的制法，其中，步骤4)的封胶体内部包裹的每颗二极体晶片，选自瞬态电压抑制二极体、肖特基二极体、开关二极体、齐纳二极体或整流二极体中的一种。
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