CN1157057A - 制造适于表面贴装的半导体器件的方法 - Google Patents

制造适于表面贴装的半导体器件的方法 Download PDF

Info

Publication number
CN1157057A
CN1157057A CN96190488A CN96190488A CN1157057A CN 1157057 A CN1157057 A CN 1157057A CN 96190488 A CN96190488 A CN 96190488A CN 96190488 A CN96190488 A CN 96190488A CN 1157057 A CN1157057 A CN 1157057A
Authority
CN
China
Prior art keywords
semiconductor element
bus
row
die cavity
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN96190488A
Other languages
English (en)
Other versions
CN1155996C (zh
Inventor
K·H·桑德斯
G·J·杜因克肯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of CN1157057A publication Critical patent/CN1157057A/zh
Application granted granted Critical
Publication of CN1155996C publication Critical patent/CN1155996C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • H01L2224/37599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明是关于适于表面贴装的半导体器件的制造方法,由该方法制备的半导体元件(2)的第一面和第二面都有一个连接点(3,4),相对的主表面(5,6)备有与以上所说的连接点(3,4)进行电接触的导电条(8),此后将半导体元件(2)封装在保护性材料(16)中,并加工导电条(8),使之进入器件(1)的连接导体(22)中。根据本发明,该方法的特征在于半导体元件(2)可通过导电条(8)互连为半导体元件(2)互连排,这样某个半导体元件(2)的连接点(3)可通过导电条(8)与排(10)中它之前的半导体元件(2’)的连接点(3’)相连接,所说的某个半导体元件(2)的另一个连接点(4)可与排中它之后的半导体元件(2”)的连接点(4”)相连接,之后将半导体元件(2)的排(10)封装在保护性材料中,并将半导体元件分离为有两个面(7)的分立半导体器件,每个器件都有一段导电条(8),此后加工每个导电条,使之进入连接导体(22)中,其中在面(7)有导电层(22’,22”),它们与以上所说的导电条(8)段相接触。

Description

制造适于表面贴装的半导体器件的方法
本发明涉及一种制造适于表面贴装的半导体器件的方法,其中半导体元件的第一面和第二面都有一个连接点,相对的主表面备有与以上所说的连接点电接触的导电条,此后将半导体元件封装在保护性材料中,加工导电条,放之进入器件的连接导体中。
采用这种方法制造的器件适于表面贴装。这类器件,也称作“表面贴装器件”(SMDs),和传统元件相比具有优越性,例如,SMDs可制作在印刷电路板的表面,器件的连接导体不必穿过印刷电路板上的孔,而传统的元件却需要。
日本专利申请JP-A-59-143348的英语摘要公开了开篇中的一种方法,由该方法制造的半导体二极管元件在连接点有两个铜导电条,此时它们形成二极管的阴极和阳极。二极管和每个导电条的一段封装在树脂中,之后加工导电条,使之进入连接导体中,其中导电条沿器件的侧面弯曲。
介绍的已知方法的缺点为器件的制造方法较昂贵,并且随着器件的日益小型化,半导体器件制造工艺另外会产生机械化的问题。
因此,本发明的目的是消除以上缺点。
根据本发明,用于该目的的方法的特征在于半导体元件可通过导电条互连为互连半导体元件排,这样通过导电条,某个半导体元件的连接点可与排中它之前的半导体元件的连接点相连接,所说的某个半导体元件的另一个连接点可与排中它之后的半导体元件的连接点相连接,之后将半导体元件排封装在保护性材料中,并将半导体元件相互分离为有两个面的分立半导体器件,每个器件都有一段相应的导电条,此后加工每个导电条,使之进入连接导体中,其中在面上有导电层,它们与以上所说的导电条段相接触。
因此,在依据本发明的方法中,每次相邻的半导体元件的两个连接点互连时,半导体元件互连从而形成互连排。这里的连接点理解为连接半导体元件的点,例如,发射极、基极、集电极、源极、漏极或栅极连接。这样就建立了相关排,其中,例如,半导体元件在第一个主表面上的连接点与排中它之前的半导体元件的连接点相连接,而另一个连接点,也就是在第二个主表面上的连接点,与下一个半导体元件的连接点相连接。因此,可在一次操作中将互连半导体元件排封装在保护材料中。这在封装中可节省大量成本,而互连排也比已知方法中的分立半导体元件更易处理,这样在日益小型化的半导体器件的制造工艺中也不会产生机械化的问题。
半导体元件排可以封装,其中在半导体元件排上有保护层例如膏或涂料。优选地,依据本发明的方法的特征在于半导体元件排封装在保护性材料中,其中半导体元件排放置在模腔内,而以上所说模腔的是用树脂填充的。这种情况下半导体元件相关排使用的封装材料为,例如,环氧树脂。可在一个模腔内放置一个或多个半导体元件排,之后将元件排封装。封装后,例如,利用锯将元件排再分为分立的半导体器件。
此方法的特征在于半导体元件排放置在模腔内的支撑点上,而支撑点支撑导电条的位置就是将分离半导体元件的位置,而除了元件排上导电条的首尾端,导电条其余的部分都不与模腔壁相接触。在模腔内整个半导体元件排都以这种方式支撑着。然后由树脂基本上完全包围元件排。半导体元件将在导电条被支撑的位置处分离,器件的侧面也将在以后的制造工序中在这些位置处形成。除了元件排上导电条的首尾端和支撑点,导电条和模腔壁不再有其它接触点,也就是半导体元件排完全处在模腔内。导电条不从模腔内伸出,以便沿模腔边缘密封时,不必对导电条进行复杂的密封。由于按照这种方式,内含腔的模具部分很容易制造。半导体元件排上导电条的首尾端可放置在模腔外,例如,用于夹紧内含模腔的模具之间的元件排。然而,同样也可将导电条的首尾端完全放置在模腔内。这样就不必对导电条进行密封。
优选地,导电条可为突起部分提供孔和接触点,半导体元件排被定位在模腔内使得突起嵌入孔内。这样用简单的方式就可将元件排定位在模腔内。
半导体器件的形状可以自由选择。然而,优选地,该方法的特征在于使用的模腔基本上为矩形,半导体元件排的纵向定位在模腔的纵向。分开后制造出的器件基本上为矩形。这种矩形非常适于表面贴装。
下面将参照附图对发明进行详细的介绍,其中:
图1显示的是使用本方法制造并贴装在印刷电路板上的半导体器件,且
图2到图7显示的是依据本发明的方法制造半导体器件的不同阶段。
各附图完全示意性的,并没有按比例画图。
在图中对应的部分一般给出了相同的参考数字。
图1显示了适于表面贴装并用本方法制造的半导体器件1。器件1,也称作“表面贴装器件”(SMD),和传统元件相比具有优越性,例如,SMD可制作印刷电路板20的表面,器件1的连接导体22不必穿过印刷电路板20上的孔,而传统的元件却需要。器件1放置在印刷电路板20的导电印刷线24上,连接导体22通过如焊料25与导电印刷线24相连接。
图2到图7显示的是依据本发明的方法制造半导体器件的不同阶段。图2显示了如何在半导体元件2的第一和第二面上的连接点3和4上外加导电条8,第一和第二面即为相对的主表面5和6,导电条和连接点3,4进行电接触。在这个例子中,半导体元件为晶体二极管,它的pn结在连接点3,4之间并与主表面5,6平行,连接点3,4构成二极管的阴极和阳极连接点。二极管基本上为方形,尺寸为1×1mm,厚度为0.5mm。在这个实施例中,导电条8是由铜制做的,它的长×宽×高尺寸为5×2×0.5mm。采用已有的焊接技术将导电条8与连接点3,4相接。根据本发明,半导体元件2通过导电条8进行互连,从而形成半导体元件2的互连排10,其中某个半导体元件2的连接点3可通过导电条8与排中它前面的半导体元件2’的连接点3’相连,以上所说的某个半导体元件2的另一个连接点4可与排中它后面的半导体元件2”的连接点4”相连。
图3显示的是如何将半导体元件排封装在保护材料中的,根据本发明,半导体元件2排放置在模腔12内,而模腔12的是用树脂填充的。半导体元件2的互连排10使用的封装材料16为如环氧树脂之类。环氧树脂为用于封装半导体元件的已公知的材料。
优选地,半导体元件2的排10放置在模腔12内的支撑点15上,而支撑导电条8的位置就是将分开半导体元件2的位置,而除了元件排10上导电条8的首尾端,导电条8其余的部分都不与模腔壁18相接触。在模腔12内整个半导体元件2的排10都以这种方式支撑着。然后元件排10基本上完全由树脂包围。导电条8仅在被支撑处没有被包围。除了元件排10上导电条8的首尾端和支撑点15,导电条8和模腔壁12不再有其它接触点,也就是半导体元件2的排10完全处在模腔12内。导电条8不从模腔12内伸出,以便沿模腔12边缘密封时,不必对导电条8进行复杂的密封。由于按照这种方式,很容易制造内含腔12的模具14,14’部分。半导体元件2的排上导电条8的首尾端可放置在模腔12外,如果需要这样的话,例如为夹紧内含腔12的模具14,14’之间的元件排10。同样,可以将导电条的首尾端完全放置在模腔内,这时只有支撑点15支撑元件排10。
优选地,导电条8有孔,而支撑点15有突起(未显示),根据本方法,可将半导体元件2排10放入模腔12内以使突起嵌入孔中。这样用简单的方式就可将元件排10定位在模腔12内。
半导体器件1的形状可以自由选择。在这个例子中使用的模腔12实际为矩形,半导体元件2的排10纵向沿模腔的纵向放置(见图3)。之后制造出的器件1基本上为矩形(见图1)。这种矩形非常适合表面贴装。
图2显示的是外加保护性材料16后的半导体元件2排10。在模腔12内支持元件排10的支撑点15处,半导体元件2相互分离从而形成分立的半导体器件1,所说的器件有两个侧面7,每个侧面都有部分导电条8,例如,采用已知的锯切处理将元件排再分为单立的半导体器件1。然后被锯的表面形成侧面7。因为导电条8也被锯断,因此侧面7包含部分导电条8。导电条8经加工进入连接导体22中,其中在侧面7有导电层22’,22”,它们与以上所说的导部分电条8相接触。导电层包含导电性膏22’,它是用已知方式涂在侧面,例如,焊膏。焊膏外加了一个铜帽,在采用如焊接之类的已知技术例时,它可使半导体器件有良好的接触。
依据本发明的方法可在一次操作中将半导体元件2的互连排10封装在保护材料16中。这在封装中可节省大量成本,而排10也比已知方法中的分立半导体元件2更易处理,这样在日益小型化的半导体器件的制造工艺中也不会产生机械化的问题。
本发明并不局限在以上介绍的实施例。在该例子中,二极管的阴极和阳极连接点接到制造出的半导体器件的连接导体上。然而,其它连接点,例如,半导体元件的发射极、基极、集电极、源极、漏极或栅极的连接点,这类半导体例如晶体管、晶闸管和ICs,都可以使用依据本发明的方法接到连接导体上。
在方法中也可以接有两个以上连接点的半导体元件,例如晶体管或ICs。那么在每个主表面上有一个或几个导电条。侧面的连接导体的构成取决于形成相应侧面的导电条数,例如通过光刻和腐蚀,或如丝网印刷之类的其它本已知的技术形成的。
在本例子中的导电条8是由铜做的,但也可用一些其它导电性材料替代用做导电条8。在本实施例中,连接点3与它之前的半导体元件2’的连接点3’相连接(见图2)。很显然也可以将连接点3连到它之前半导体元件2’的连接点4’上。那么假设前面元件2’的与元件2反相。
在本实施例中,导电层22由焊膏和铜帽形成。同样,导电层22也可以仅包含导电膏或,例如,由电化学或汽相淀积技术生长的导电层。
制造半导体器件1的一些技术在以上介绍中都提到了。但这并不意味着依照本发明的方法仅能由这些技术完成。所以,例如,除了焊接也可以使用如导电粘合技术。

Claims (5)

1.一种适于表面贴装的半导体器件的制造方法,由此方法制备的半导体元件的第一和第二相对的主表面都有一个连接点,主表面上备有与以上所说的连接点电接触的导电条,此后半导体元件封装在保护性材料中,加工导电条使之进入器件的连接导体中,其特征在于:半导体元件可通过导电条互连为半导体元件相关排,这样通过导电条某个半导体元件的连接点可与排中它之前的半导体元件的连接点相连接,所说的某个半导体元件的另一个连接点可与排中它之后的半导体元件的连接点相连接,之后将半导体元件排封装在保护材料中,并将这些半导体元件相互分离为有两个侧面的分立半导体器件,每个器件都有一段相关的导电条,此后加工每个导电条,使之进入连接导体中,其中在侧面有导电层,它们与以上所说的导电条段相接触。
2.根据权利要求1的方法,其特征在于:半导体元件排封装在保护材料中,其中半导体元件排放置在模腔内,并用树脂填充所说模腔。
3.根据权利要求2的方法,其特征在于:半导体元件排放置在模腔内的支撑点上,支撑点支撑导电条,支撑位置就是将分离半导体元件的位置,而除了元件排上导电条的首尾端,导电条其余的部分都不与模腔壁相接触。
4.根据权利要求3的方法,其特征在于:导电条可为突起部分提供孔和接触点,半导体元件排被定位在模腔内以便突起嵌入孔内。
5.根据权利要求2,3和4中任一项的方法,其特征在于:模腔基本上为矩形,半导体元件排纵向定位在模腔的纵向。
CNB961904887A 1995-05-12 1996-05-07 制造适于表面贴装的半导体器件的方法 Expired - Fee Related CN1155996C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP95201234 1995-05-12
EP95201234.2 1995-05-12

Publications (2)

Publication Number Publication Date
CN1157057A true CN1157057A (zh) 1997-08-13
CN1155996C CN1155996C (zh) 2004-06-30

Family

ID=8220286

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB961904887A Expired - Fee Related CN1155996C (zh) 1995-05-12 1996-05-07 制造适于表面贴装的半导体器件的方法

Country Status (8)

Country Link
US (1) US5712197A (zh)
EP (1) EP0770266B1 (zh)
JP (1) JP4129842B2 (zh)
CN (1) CN1155996C (zh)
DE (1) DE69609921T2 (zh)
MY (1) MY132219A (zh)
TW (1) TW302595B (zh)
WO (1) WO1996036071A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824784A (zh) * 2010-05-05 2014-05-28 万国半导体有限公司 用连接片实现连接的半导体封装的方法
CN104319268A (zh) * 2013-11-05 2015-01-28 立昌先进科技股份有限公司 一种晶片型二极体封装元件及其制法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5990490A (en) * 1998-06-29 1999-11-23 Miracle Technology Co., Ltd. Optical electronic IC capable of photo detection
US6008535A (en) * 1998-09-17 1999-12-28 Advanced Ceramic X Corp. Method of making a semiconductor diode from laminated ceramic tape
US6159771A (en) * 1999-07-27 2000-12-12 Smtek Inc. Method of manufacturing diodes
US20070117268A1 (en) * 2005-11-23 2007-05-24 Baker Hughes, Inc. Ball grid attachment
TW200836315A (en) * 2007-02-16 2008-09-01 Richtek Techohnology Corp Electronic package structure and method thereof
EP2242094A1 (en) 2009-04-17 2010-10-20 Nxp B.V. Foil and method for foil-based bonding and resulting package
TWI651830B (zh) * 2015-02-17 2019-02-21 立昌先進科技股份有限公司 多功能小型化表面黏著型電子元件及其製法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3148778A1 (de) * 1981-05-21 1982-12-09 Resista Fabrik elektrischer Widerstände GmbH, 8300 Landshut Bauelemente in chip-bauweise und verfahren zu dessen herstellung
JPS59143348A (ja) * 1983-02-07 1984-08-16 Hitachi Ltd 電子部品
JPS60145525A (ja) * 1984-01-10 1985-08-01 Canon Inc 磁気記録媒体
US4660127A (en) * 1985-12-17 1987-04-21 North American Philips Corporation Fail-safe lead configuration for polar SMD components
KR960006710B1 (ko) * 1987-02-25 1996-05-22 가부시기가이샤 히다찌세이사꾸쇼 면실장형 반도체집적회로장치 및 그 제조방법과 그 실장방법
EP0509065A1 (en) * 1990-08-01 1992-10-21 Staktek Corporation Ultra high density integrated circuit packages, method and apparatus
US5281849A (en) * 1991-05-07 1994-01-25 Singh Deo Narendra N Semiconductor package with segmented lead frame
KR970002140B1 (ko) * 1993-12-27 1997-02-24 엘지반도체 주식회사 반도체 소자, 패키지 방법, 및 리드테이프
US5478402A (en) * 1994-02-17 1995-12-26 Ase Americas, Inc. Solar cell modules and method of making same
US5550086A (en) * 1995-12-27 1996-08-27 Tai; George Ceramic chip form semiconductor diode fabrication method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824784A (zh) * 2010-05-05 2014-05-28 万国半导体有限公司 用连接片实现连接的半导体封装的方法
CN103824784B (zh) * 2010-05-05 2016-10-12 万国半导体有限公司 用连接片实现连接的半导体封装的方法
CN104319268A (zh) * 2013-11-05 2015-01-28 立昌先进科技股份有限公司 一种晶片型二极体封装元件及其制法
CN104319268B (zh) * 2013-11-05 2017-12-01 立昌先进科技股份有限公司 一种晶片型二极体封装元件及其制法

Also Published As

Publication number Publication date
JPH10503329A (ja) 1998-03-24
CN1155996C (zh) 2004-06-30
TW302595B (zh) 1997-04-11
DE69609921D1 (de) 2000-09-28
DE69609921T2 (de) 2001-03-15
JP4129842B2 (ja) 2008-08-06
EP0770266A2 (en) 1997-05-02
WO1996036071A2 (en) 1996-11-14
MY132219A (en) 2007-09-28
US5712197A (en) 1998-01-27
EP0770266B1 (en) 2000-08-23
WO1996036071A3 (en) 1997-01-30

Similar Documents

Publication Publication Date Title
KR101130633B1 (ko) 면실장형 전자부품과 그 제조방법
US6580161B2 (en) Semiconductor device and method of making the same
US6660558B1 (en) Semiconductor package with molded flash
CN1153997A (zh) 改进的减小尺寸的集成芯片封装
CN1252753C (zh) 引线剥离方法、微电子元件连接方法和元件承载体制造系统
CN1222993C (zh) 小型半导体封装装置
CN101053079A (zh) 堆叠式封装的改进
CN1571151A (zh) 双规引线框
CN1458691A (zh) 形成多引线框半导体器件的结构和方法
CN101060087A (zh) 电极及其制造方法,以及具有该电极的半导体器件
CN1155996C (zh) 制造适于表面贴装的半导体器件的方法
CN1129184C (zh) 用于半导体器件的引线框架
CN1161010C (zh) 利用导电的互连接在基片的上下侧之间制造接线的方法和在基片上具有该互连接的接线
US3629668A (en) Semiconductor device package having improved compatibility properties
KR100214544B1 (ko) 볼 그리드 어레이 반도체 패키지
JP4023698B2 (ja) 下面電極付き側面使用電子部品の製造方法
CN1222252A (zh) 制造半导体封装的方法
US20090236705A1 (en) Apparatus and method for series connection of two die or chips in single electronics package
JP2000196153A (ja) チップ電子部品およびその製造方法
US4011398A (en) Electrical connection to a circuit potted within a housing and method of same
JPH0878732A (ja) チップ型発光ダイオード及びその製造方法
JPH1051034A (ja) 面実装型電子部品、その製造方法、これを回路基板上に実装する方法、およびこれを実装した回路基板
CN1324108A (zh) 用于封装或测试应用中的多线格栅
CN1641876A (zh) 集成电路模块中的安装结构
CN1094849A (zh) 一种塑封半导体器件的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: ROYAL PHILIPS ELECTRONICS CO., LTD.

Effective date: 20090710

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20090710

Address after: Holland Ian Deho Finn

Patentee after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Patentee before: Koninklike Philips Electronics N. V.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040630

Termination date: 20110507