TW302595B - - Google Patents

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TW302595B
TW302595B TW085105741A TW85105741A TW302595B TW 302595 B TW302595 B TW 302595B TW 085105741 A TW085105741 A TW 085105741A TW 85105741 A TW85105741 A TW 85105741A TW 302595 B TW302595 B TW 302595B
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semiconductor
conductive sheet
mold cavity
conductive
row
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Philips Electronics Nv
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/495—Lead-frames or other flat leads
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

3C25dS A7 B7 五、發明説明（1 ) 發明背景 本發明係關於製造一適合用於表面黏著的半導體裝置的 方法’在一個第一和第二相對主要表面上都具有接點的半 導體元件上，加上與該接點-形成電性接觸的導電片，然後 將半導禮元件封裝在保護材料中，再將導電片處理成爲裝 置的連接導體。 ’ .這種方法製造的裝置適合用於表面黏著。這種裝置也稱 爲「表面黏著裝置」（SMD)優於傳統元件， ，議可以黏著在一個印刷電路板的表面上，== 元件’將裝置的連接導體穿過印刷電路板上的孔洞。 编號JP-A-59-143348日本專利申請案的英文摘要中說明 了首段所提及的方法，其中的二極體半導體元件在接點上 有兩個銅片，在這個例子中即作爲二極體和陰極和陽極。 二極體和各銅片的一部份封裝在樹脂内，然後將銅片弩折 包圍裝置的侧面，·成爲連接導體。 所敛述的已知方法有個缺點，製造方法比較昂貴，在持 續微小化的趨勢下，會對半導體製程的機械化造成額外的 問題。 經濟部中央標準局員工消费合作社印製 本發明的目的特別是爲要克服上述的缺點β 根據本發明，爲以上的目的所提出的方法的特徵在於： 半導體元件藉由導電片連接起來，形成一列連貫的半導體 儿件，其中某一半導體元件的一個接點藉由導電片連接至 列中前面一個半導體元件的一個接點，而該半導體元件的 另一個接點則連接至列中下一個半導體元件的—個接點， -4 - 本紙張尺度適用中國國家橾準（CNS) A<1規格（210Χ297公釐） 經濟部中央標準局員工消費合作社印製 五、發明説明（2 接著將整列的半導體元件分開， ϋ ]成爲獨立的半導體裝置，各 自具有兩個侧面，其上都帶有部 ^ ^ T啕邵伤的導電片，最後將各導 電片處理成爲連接導體，使侧 導電片。 疋則面上的導電層接觸該部份的 因此’在本發明的方法中，在_1 每一次都將相鄰半導體元件 的兩個接點連接起來，所以使丰劣Μ i Λ, 仗千導鱧几件連接成一列連貫 々元件0在此，接點可以視爲丰 - 优馬乎等體疋件上可供連接的點 ’例如射極、基極、集極、诉杯、，π & * n t 痕極、汲極或閘極的連接。這 樣一來，，就產生了 -整列的元件，舉例來説，可使半導體 疋件在第-王要表面的-個接點.連接至列中前一個半導趙 元件的-個接點’而使第二主要表面上的另一個接點連接 至下一個半導體元件的接點上。 這樣一來，可以在一個操作步驟中將—列連貫的半導體 元件封裝在保護材料内。這會節省相當多的封裝成本，而 且對現有的方法，處理一列連貫的半導體元件要比處理各 自的半導體元件更爲容易，所以對半導體裝置製造機械化 、和持續微小化來説，都不會造成問題。 封裝整列的半導體元件時，可將油墨或塗料—類的保護 材料塗佈在整列的半導體元件上。最好的作法，也是本發 明之方法的特徵，是在封裝整列的丰導體元件時，使整列 的半導體元件安置在一個鑄模腔内，而在該鑄模腔内填以 樹脂。舉例來説，可以用環氧樹脂來封裝這整列的半導體 元件。也可以將一整列或數列這種半導體元件放在—個鋒 模腔内，然後再封裝。封裝之後，再分割成獨立的半導禮 -5- 表紙張尺度適用中國國家標準（CNS ) Α4规格（210X297公釐） —^ϋ m 1^1 -------(裝—— (請先閱讀背面之ii-意事項再填寫本頁) 訂 」 4· 五、發明説明（ 3 A7 B7 經濟部中央標準局員工消費合作社印製 元件，分割時可以用的方法舉例來説，可以加以錄開。 本發明比較理想的特徵在於，整列的半導體元件是放在 鑄模腔中的支持點上，將導電片頂住在分割半導體元件的 位置，而且導電片其他的部-位並沒有靠在鑄模腔壁上，除 了整列當中最初和最後的導電片以外。照這樣，整列的半 導體元件可以全然支律在鑄模腔内。然後會用樹脂將整列 元件完全封住。以後分割半導體元件時，會在頂住導電片 的位置形成裝置的侧面。除了元件列中最初和最後的導電 片，和支持點以外，導電片與鑄模腔沒有其他的接觸點， 也就是説整列的半導體元件完全位在鑄模腔内。導電片不 會伸出鋒模腔外，所以在密封轉模腔的邊緣時，就毋需沿 著導電片的複雜密封。因爲這樣的設計，具有空腔的鑄模 組件就比較容易製作了。舉例來説，整列半導體元件最初 和最後的導電片可以放在鑄模腔外，以便抓緊帶有鑄模腔 之鑄模组件之間的元件列。但是另一方面，最初和最後導 電片最好能全部放在鑄模腔内。這樣就毋需沿著導電片加 以密封。 比較理想的作法是，在導電片上製作凸出物可以穿過的 孔洞和接點，當整列半導體要放在錡模腔内時，可使凸出 物伸入孔洞内。這樣就可以很容易將元件列放入鑄模腔内 Ο 半導體裝置的外型可以隨意選擇。但是，本發明最理想 的特徵在於，鑄模腔實質上是矩形，而整列的半導體元件 放置時係以其水平方向沿轉模腔的水平方向放置。在分割 -6 - 各紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚） (請先閱讀背面之注意事I再填寫本頁) 裝. 訂
A 經濟部中央標準局員工消費合作社印製 A7 —_____B7 五、發明説明（4 ) 又後，就會製造出大致爲矩形盒狀的裝置。這種矩形的 外形非常適合用於表面黏著。 附圖的簡單説明 底下將參照附圖詳細説明本發明，各附囷分別是： 圖1説明本發明之方法所製造，黏著在一面印刷電路板上 的一個半導體裝置，並且 -圖2至圖7説明了本發明之方法所製造的半導體裝置的各 個階段。 附圖只是單純的輪廓，並不按照實際的比例。在各附圖 中’相對應的部份大都编以相同的參考代號。 發明的詳細説明 囷1中説明了本發明之方法所製造適於表面黏著的半導 體裝置1。這樣裝置1也稱爲「表面黏著裝置」（SMD)，優 於傳統元件，因爲舉例來説，s M D可以黏著在一個印刷電 路板20的表面上，毋需像傳統元件，將裝置1的連接導體 22穿過印刷電路板2〇上的孔洞。裝置i放在印刷電路板2〇 的連線24上’而且連接導體22可以用，舉例來説，銲錫 25連接至連線24 » 囷2至囷7説明了本發明之方法的各個階段。囷2的半導 體疋件2中，在第一和第二彼此相對的主要表面5、6上的 接點3、4上，有著導電片8，點3、4有著電性的接觸。在 這個例子中，半導體元件是一個二極體晶體，在兩個接點 3、4之間有一個ΡΝ接面，平行於主要表面5、6延展，而 接點3、4形成了二極禮的陰極和陽極接點。二極體大致上 本紙張尺度適用中國國家標準（CNS ) Α4規格（210χ297公瘦） (請先閲讀背面之：义意事項再填寫本頁) 裝. 訂 經濟部中央標準局貝工消費合作社印裝 A7 ________— B7_ 五、發明説明（5 ) " 一 ' ·~·~— 是正方形，大小爲1 X ：[公釐，厚約0 5公釐。在這個例子 中導電片8是用銅作成的，其長父寬〆高爲5χ2χ〇5公釐 。導電片8是藉已知的銲錫技巧連接至接點3、4上。根據 本發明，半導體元件2是藉由導電片8互相連接，形成—列 10連贯的半導體元件2，其中某一半導體元件2的一個接 點3是由導電片8連接至列中前_個半導體元件2，的接點3 , '’而孩半導體元件2的另—個接點4則連接至列中下一個半 導體元件2 "的接點4 "。 圖3説明了將整列10的半導體元件2封裝在保護材料中， 而根據本發明，整列的半導體元件2是放在鑄模腔12内， 並使鑄模腔1 2填滿了樹脂。舉例來説，可用環氧樹脂作爲 這列10連貫之半導體元件2的封裝16。環氧樹脂本身已知 是封裝半導體元件的材料。 比較理想的作法是，將整列1〇的半導體元件2放在鑄模 腔1 2的支持點i 5上，可使導電片8頂在隨後分割半導體元 件2的位置上，而除了全列丨〇的起初和最後導電片8以外， 導電片8與鑄模腔的内壁18之間並沒有其他的接觸。照這 樣，就可以將整列10的半導體元件2支律在鑄模腔12中。 然後用樹脂實際上完全地封裝住全列丨〇。只有在頂住導電 片8的位置上，才沒有封裝住導電片8。導電片8並沒有靠 在鑄模腔12的内壁上，除了全列1〇的最初和最後導電片8 ，以及支持點1 5，也就是説，全列i 〇的半導體元件2完全 裝在鑄模腔1 2内。導電片8並沒有伸珠鑄模腔i 2，所以在 歡封轉模腔12的邊緣時，就毋需沿著導電片8的複雜密封 _______ ~ 8 i紙張尺度適用中國國家標準（CNS ) A4規格（210x297公瘦） I, ^ ^裝------訂------^4 (請先閲讀背面之：义意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 五、發明説明（6 ) 。因爲這樣的設計，具有空腔12和鑄模组件14、14，就比 較谷易製作。如果需要，整列半導趙元件2和最初和最後 導電片8可以放在鋒模腔丨2之外，舉例來説可以用來緊緊 抓住具有鑄模腔丨2之鑄模組件丨4、1 4，之間的元件列】〇。 另—方面，最初和最後導電片8也很可能全部放在鉾模腔 1 2内’而只用支持點i 5來支撐元件列1 〇。 -最好在導電片8上製作孔洞，而使支持點1 5具有凸出物（ 未畫出），這樣根據本發明要將全列10的半導體元件2放在 鑄模腔1 2中時，可使凸出物伸入孔洞内。這樣就可以很容 易地將元件列10放入鑄模腔12内。 半導體裝置1的外型可以隨意選擇。在這個例子中所用的 鑄模腔12實際上是矩形，而整列10的半導體元件2放置時 ，係以其水平方向沿鑄模腔（請看囷3)的水平方向放置。這 樣製造的裝置1實質上是矩形盒狀（見圏1)。這種矩形外型 非常適合於表面黏著。 圖2的全列1 〇半導體元件已經加上保護材料1 6。舉例來 説’可以用已知的錄法將整列分割成獨立的半導雜裝置1 ，而且半導體元件2彼此分開形成獨立的半導趙裝置丨時， 是從鑄模腔1 2内支撢全列1 〇的支持點丨5分開，使所得到 的裝置具有兩個侧面7，各自具有部份的導電片8。這樣， 鋸開的表面就形成側面7。即然導電片8也同時被鋸開，侧 面7就包含了導電片8的一部份。導電片8加以處理後成爲 連接導體22，其中在侧面7上會有導點層22,、22"接觸到 該導電片8的部份》導點層包含了導電油墨22·，是以已知 -9- 本紙張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） -------- ί 批衣-- (請先閲讀背面之：>χ意事項再填寫本頁} 訂 五、發明説明（ A7 B7 經濟部中央標準局員工消費合作社印製 的方式，誓如銲錫油墨，施加在側面上。在銲錫油墨上再 加上銅蓋22"，就可以用銲錫之類的已知技術很輕易地完 成半導體裝置的接觸。 本發明的方法，可以在一個操作步驟中，將全列1〇連貫 的半導體元件2都封裝在保護材料中。這可以省下大量的 封裝成本’而且以現有的方法，整列丨〇的連貫的元件比獨 立的半導體tl件2更容易處理，所以對半導體裝置製造機 械化、和持續微小化來説，都不會造成問題。 本發明並不限於以上敘述的實施例。在這個例子中，所 製造的半導體裝置是一個二極體，而且使陰極和陽極連接 連接至連接導體上。但是，以本發明的方法，也可使電晶 體、閘流體和1C之類的半導體元件上，射極、基極、集極 、源極、汲極或閘極等接點連接至連接導體上。 本發明的方法也可以用來連接具有二個以上的接點的半 導體元件，例如電晶體或1(：。在各主要表面上可以加上一 個或數個導電片8。側壁上的連接導底的結構會視導電片 的數目4定，在形成連接導體的結構時，舉例來説，可以 用微影技術和蝕刻，或者其他本身已知的技術，如網印。 本例子中導電片是用銅作成，但另—方面也可用其他導 電材料作爲導電片8。在實施例中，接點3是連接至前一個 半導體7C件2’（見圖2)的接點3,》很明顯地，接點3也可以 接至前一個半導體元件2,的接點4,。這時，就需將前一個 元件2 ’相對於元件2倒轉過來。 在實抱例中，導電層是由一層銲踢油墨和一個銅蓋所形 -10- 木纸張尺度適财11¾家轉（CNS) A4規格（21Gx297公瘦 (請先聞讀背面之ίΐ.意事項再填寫本頁) 裝. -St A7 _______B7______ 五'發明説明（8 ) 成。另一方面，導電層22也可能只包含一層銲錫油墨，而 且可以利用，舉例來説，電化學或氣相沉積技術來製作。 以上的説明提及了製造半導體裝置1的某些技術《但這 絕不表示本發明的方法只能-用這些技術來實施。因此，舉 例來説，銲錫以外，如導電膠的技術一樣可以適用。 (請先閱讀背面之主意事項再填寫本頁) 裝. *ys 4 經濟部中央標準局貝工消費合作社印製 -11 - 本紙張尺度適用中國國家;^準（CNS ) A4規格（210X297公釐〉

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  1. A8 B8 C8 D8 申請專利範園 個二表面黏著之半導趙裝置的方法，在- .王要表面上都具有接點的半導體元件 趙元接點形成電性接觸的導電片，然後將半導 » #保護材科中，再將導電片處理成作裝 ==!趙，其特徵在於：半導趙元件藉由導電片彼 :連接成爲—料貫的半導航件，其中某-半導體元 件的-個接點連接至列中前一個半導禮元件的一個接點 丄而孩某半導it元件的另-個接㈣連接至列中下一個 導雜元件的-個接點，㈣將整列的半導體元件封裝 在^種保護材料中，並使半導航件彼此分開成爲獨立 的半導體裝置，各自具有兩個侧面，其上都帶有部份的 _導電片’最後將各導電片處理成爲連接導體，使側 面上具有導電層，接觸該部份的導電片。 2. 根據_請專利範圍第1項之方法，其特徵在於：將整列 半導體疋件封裝在保護材料中時，整列的半導體元件是 放在鑄模腔内，而該鑄模腔填充了樹脂。 3. 根據申請專利範圍第2項之方法，其特徵在於：整列的 半導體元件是放在鑄模腔中的支持點上，將導電片頂在 半導體將分割的位置上，而導電片和其他部位並不會靠 在鎊模腔的内壁上，除了可能是整列中最初和最後的導 電片以外。 4. 根據申請專利範圍第3項之方法，其特徵在於導電片上 具有孔洞，而接觸點爲凸出物，在放置整列的半導體元 件時，係使凸出物伸入孔洞内。 -12- 本紙張尺度適用中國國家標準（CNS〉Α4規格（210 X 297公釐） 請 先 閱 讀 背 之 注· 項· | 再人 填 I裝 I I 訂 A8 B8 C8 D8 、申請專利範圍 5.根據申請專利範圍第2、3、4項任一項之方法，其特徵 在於所用的鑄模腔實質上是矩形，而放置半導體元件時 是以其水平的方向沿鋒模腔的水平方向放置。 (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 」 經濟部中央標隼局員工消费合作社印裝 -13 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）
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JP (1) JP4129842B2 (zh)
CN (1) CN1155996C (zh)
DE (1) DE69609921T2 (zh)
MY (1) MY132219A (zh)
TW (1) TW302595B (zh)
WO (1) WO1996036071A2 (zh)

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TW200836315A (en) * 2007-02-16 2008-09-01 Richtek Techohnology Corp Electronic package structure and method thereof
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CN103824784B (zh) * 2010-05-05 2016-10-12 万国半导体有限公司 用连接片实现连接的半导体封装的方法
TWI559576B (zh) * 2013-11-05 2016-11-21 Sfi Electronics Technology Inc A chip type diode package element and its manufacturing method
TWI651830B (zh) * 2015-02-17 2019-02-21 立昌先進科技股份有限公司 多功能小型化表面黏著型電子元件及其製法

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US5712197A (en) 1998-01-27
DE69609921D1 (de) 2000-09-28
WO1996036071A2 (en) 1996-11-14
EP0770266A2 (en) 1997-05-02
EP0770266B1 (en) 2000-08-23
CN1155996C (zh) 2004-06-30
JP4129842B2 (ja) 2008-08-06
CN1157057A (zh) 1997-08-13
WO1996036071A3 (en) 1997-01-30
DE69609921T2 (de) 2001-03-15
MY132219A (en) 2007-09-28
JPH10503329A (ja) 1998-03-24

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