CN1040462A - Cmos晶体管和单电容动态随机存取存储单元及其制造方法 - Google Patents
Cmos晶体管和单电容动态随机存取存储单元及其制造方法 Download PDFInfo
- Publication number
- CN1040462A CN1040462A CN89104647A CN89104647A CN1040462A CN 1040462 A CN1040462 A CN 1040462A CN 89104647 A CN89104647 A CN 89104647A CN 89104647 A CN89104647 A CN 89104647A CN 1040462 A CN1040462 A CN 1040462A
- Authority
- CN
- China
- Prior art keywords
- transistor device
- electrode
- source
- word line
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000003990 capacitor Substances 0.000 title abstract description 12
- 230000000295 complement effect Effects 0.000 claims abstract description 26
- 238000003860 storage Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 claims description 2
- 230000008025 crystallization Effects 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims 3
- 239000012535 impurity Substances 0.000 claims 2
- 238000011049 filling Methods 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 238000012797 qualification Methods 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000006059 cover glass Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
一种互补型MOS单电容动态存取存储单元，该存贮单元无阈值损失，在无升压字线的情况下工作，它包括一存储电容和与该电容相连的、起两个互补晶体管器件作用的n型和p型传输器件，它们的栅极由RAM字线上的互补信号控制。
Description
本发明涉及使用互补型金属氧化物半导体（CMOS）晶体管和一个存储电容器的半导体存储器，更具体地说，本发明涉及用于大规模集成电路技术的动态操作的随机存取存储器（RAM）的结构与制造方法。
1986年12月30日公布的Kume等人的美国专利U.S.4，633，438题为“叠层半导体存储器”，它描述了一种进行动态操作的三管随机存取存储器，其中一个晶体管叠放在另一个晶体管上。写入用的晶体管置于读出用的晶体管上，其一端与晶体管的栅电极一起用来判断数据。其另一端与读出用晶体管的一端相连。
使用叠层互补型场效应管（FETS）可以获得能进行超大规模集成的存储单元，其中，两个FETs由重叠字线驱动。不过，这些字线是就读出和写入操作分别被驱动的，而不是象本发明那样由互补信号同时驱动的。
1981年1月2日公布的Saxe的美国专利U.S.4271488题为“使用模拟存储阵列的高速探测系统”，它描述了一种使用一个模拟存贮阵列的高速探测系统，在该阵列中，连接到一根模拟总线的取样-保持元件按行和列排列，形成了一个MXN阵列。该系统可按快进-慢出模式工作，而且可以把这个模拟存储阵列做在一块单片集成电路的半导体芯片上。该模拟存储器包括含有取样/保持电路的元件。典型的取样/保持电路示于图2，包括说明互补型FET开关装置的图2c。不过，互补驱动信号是借助于倒相器54和与门52在单元内得到的，且该专利没有说明或教导使用提供前面所述的本发明的互补驱动信号的互补字线。
1972年10月24日公布的Chartecs等人的美国专利U.S.3，701，120题为“慢写入和快无损读出的模拟电容存储器”，它描述了一种能以相当慢的速度写入并独立地以相当快的速度无损读出的模拟存储器。当需存储部件时，就规定一种单独的写入和读出地址逻辑。每个存储部件包括一取样和保持微电路阵列，各微电路有一外存储电容、一个隔离放大器和独立的输入和输出模拟开关以响应垂直和水平写入读出寻址。
1969年7月22日公布的Buvns等人的第3457435号题为“互补型场效应晶体管传输门”的美国专利，描述了一种电路，该电路的导电类型相反的场效应晶体管对的源-漏通路并联连接，极性相反的信号被加在这两个晶体管的栅极上，加偏压使它们同时导通或截止。构成互补型晶体管的栅极由图4所示的两个互补信号驱动，以便消除由单个场效应晶体管的阈值电压引起的传输电压的下降。该专利没有披露这种电路在一个动态随机存取存储器（DRAM）单元中的用法。
Fujitsu有限公司的欧洲专利175-378A示出了一种三管元件的DRAM结构，它有读和写的选择线，这两根线结合成一根线连接到读和写选择晶体管的栅极。写选择晶体管放在读选择晶体管之上，其间用一绝缘层隔开并共用一个漏区。存储晶体管形成在硅衬底上，其形成深度与读选择晶体管相同。两个晶体管的沟道区域互相连接，各自被用来作为另两个晶体管的扩散（源或漏）区。
写和读选择线可以结合成一根单独的控制线或一根写/读选择线。这里，读和写选择晶体管的栅极都连接到写/读选择线上，靠具有不同的阈值电压来区分它们。
其它的参考文件包括U.S专利4，434，433、4，308，595、4，203，159、4，044，342、3，919，569和IBM技术公报Vol.23，No.10第4620页及Vol.18，No.3，第649页上的内容。
本发明的目的是提供一种互补型MOS单电容动态随机存取存储单元，它用无升压字线工作，没有阈值损失的问题。
本发明的另一个目的是提供一种CMOS单存储电容动态随机存取存储单元，它包括连接到存储电容器的n型和p型传送器件。
本发明再一个目的是提供一种带有两个互补型晶体管器件的真正的CMOS DRAM单元，两个互补型晶体管器件的栅极由互补字线控制。
本发明的前述目的及其它目的、特征和优点从下面结合附图的更具体的说明可以看得很清楚。
图1是按本发明原理的CMOS存储单元的电路简图。
图2为按本发明原理的CMOS存储单元结构的截面示意图。
图3和图4为制造图2所示的CMOS单元结构的某个生产步骤时的截面示意图。
图5是按本发明原理的CMOS存储单元另一实施例的截面示意图。
在使用动态随机存取存储器（DRAM）单元的集成电路工艺中，随着DRAM密度的增加，按比例减少由DRAM单元（如单管、单电容DRAM器件等）所占据的面积是重要的。按比例缩少DRAM元件中传送器件的尺寸的一般的困难是：要把“截止”器件上的漏电流减到最小，就希望有高的阈值电压，但反过来，要把存储的电荷增到最大并获得较高的电荷传送速率，又希望阈值电压小。随着器件尺寸的减少，利用升压字线来避免这一问题的传统方法就更困难了。例如，尺寸减少了的器件的击穿电压降低，这就限制了可能的升压字线电压电平。因此，对于DRAMS来说，重要的是设计一种新的允许使用无升压字线但又不存在所述阈值损失问题的单元。
本发明提供了一种克服了所述问题的互补型MOS单电容DRAM单元（CMOS-1C单元）。这种新单元的一个实施例的线路示意图示于图1。与常规的单管DRAM单元的区别在于，连接到存储电容器的传送器件不是只用一种类型的，而是在每个存贮单元中同时具有n型传送器件和p型传送器件，例如，图1中的器件10、12和14、16。这些互补器件的栅极18、22和20、24分别由互补字线26和28控制。在准备状态，字线26处于低电平使n型器件10、14截止，而互补字线28处于高电平使p型器件12、16截止。存贮单元38由传送器件10和12以及存储电容30构成，电荷存储在电容30中，在准备状态，单元38与位线（bitline）34相隔离。当该单元被选通时，字线26变为高电位，而互补字线28变为低电位，使器件10和12两者均导通。互补器件10和12构成一CMOS旁路门（pass gate），没有阈值损失。结果，不需要使字线电压电平升高来存储全电压（全电源电压VDD或零电压）。因此，能够通过位线34以全VDD的值（即没有阈值损失）从电容30读出总的传感电荷或将其存入电容30。
所述的存贮单元有几个优点：（1）对电荷传送即使不升高字线电压电平也没有阈值电压损失，因为不管是VDD还是零均可分别通过PMOS或NMOS全部传送;（2）因为在电荷传送期间的大部分时间两个器件都工作，所以信号传输较快;（3）因为该单元没有阈值损失并有高的电荷传送速率，所以在设计时可使传送器件的阈值电压的绝对值较大，以便抑制漏电。
本发明提供的制造工艺克服了在目前由单一器件占据的集成电路的那个面积上完成PMOS和NMOS两个器件的技术难题。本发明还提供了CMOS-1C单元的一种新颖结构，它和单器件单元占有大致同样的面积。
图2示出这种新的存贮单元结构的横截面示意图。图2中的CMOS-1C单元包括一个PMOS器件，该器件具有栅极46和分别在n阱44中的p+漏区40和源区42。该存贮单元还包括一个做在p+衬底50上的沟槽式电容（trench capacitor）48。沟槽式电容器48通过称为连接片（strap）的中间连接层52与传送器件p+源区42相连接。连接片的材料可以用硅化钛、氮化钛/硅化钛或硅化钴等。PMOS传送器件之上是另一个n型（NMOS）传送器件，它包括在SOI（硅层在绝缘层之上）膜上制作的源区和漏区54、56。因为连接片52对p型和N型材料均是导电的，所以NMOS和PMOS器件的源和漏区42、40及54、56互相连接。NMOS器件的栅极18和PMOS器件的栅极20（也记作46）分别与字线26和28相连，它们连接到阵列端部它们各自的字线驱动器上。图2中的NMOS器件和PMOS器件分别对应于图1中的器件10和12，其工作方式如前所述。
下面叙述制造图2所示单元结构的工艺过程。尽管该工艺过程是就一个单元描述的，但应认为该工艺过程也适用于致密阵列中多个单元的制造。该工艺过程包括下列步骤：
步骤一.在p+半导体衬底50上淀积一p型外延层58，用活性离子刻蚀法（RIE）在p型外延层58和p+型衬底晶片50上刻出5至6微米的沟槽。（图3）
步骤二.在沟槽的壁上形成复合的氧化物/氮化物/氧化物存储器绝缘体80。（图3）
步骤三.用p+型多晶硅60填满沟槽并将其弄平整。
步骤四.用1.6Mev能量进行两次磷注入（一次表面注入和一次深注入）形成一反型的n型阱44。
步骤五.生长局部氧化物绝缘区82。
步骤六.通过单一的硼注入调整PMOS和圆周电路NMOS器件的阈值电压。
步骤七.生长栅极氧化物，在PMOS栅极上淀积n+多晶硅栅极材料46和氧化膜62并制出图形。
步骤八.在栅电极的边缘形成氧化物隔离层。
步骤九.分别对PMOS和NMOS器件注入磷和硼，以获得有梯度变化的源/漏结。
步骤十.为了形成硅化物52而将源/漏区42、40的表面显露出来，同时栅极46仍由厚的绝缘体62使其与所述硅化物隔开。（图3）。
步骤十一.在硅化物和绝缘区上形成一轻掺杂的p型硅膜64，其形成方法可以有下面四种：（11a）、按多晶结构淀积所述膜64，再用电子束退火进行再结晶;（11b）.按多晶结构淀积膜64，通过氢钝化处理使晶粒间界（grain boundavy tvaps）不活泼;（11c）.淀积一非晶硅膜64，因为硅化的p+源/漏区中的存在籽晶，使非晶硅能在热处理后转变为单晶;（11d）.淀积成多晶结构的膜64，调整p型掺杂水平以给出一个高阈值电压，这能用来把器件的漏电减到最小。
步骤十二.限定NMOS的有源区面积，并生长一薄层栅极氧化物。
步骤十三.通过硼注入来调整n沟道阈值电压。
步骤十四.淀积n+型多晶栅极材料18，并刻出图形，在栅电极边缘形成氧化物隔离层。
步骤十五.注入砷掺杂剂以获得n沟道传送器件的n+源/漏结54，56，并生长氧化物以包覆该器件。
步骤十六.淀积表面覆盖玻璃膜并回熔处理。
步骤十七.刻蚀接触孔84，淀积金属台面86，并刻出图形。
这样就得到了图2所示的元件结构。
本发明CMOS-1C元件的结构的另一个实施例示于图5。在这一理想化的结构中，CMOS旁路门是由PMOS器件72和NMOS器件74构成的，器件72和74均为垂直晶体管，除了与位线73的接触以及一个连接硅化物或金属连接电75外，它们与周围的导电材料完全隔离。整个元件，包括与其它元件的栅极互连以形成互补字线的多晶栅极77和78，可以做在沟槽68中，沟槽68是在覆盖着一厚层绝缘体79的导电衬底70上刻蚀形成的。存储电容由多晶硅电极90、薄的氧化物电介质71和板70构成。多晶硅电极90通过导电连接片75与器件扩散器相连。
Claims (11)
1、一种动态半导体存储器阵列的存储器单元结构，包括字线对，第一字线用于传输表示第一和第二信号电平的第一字线信号，第二字线用于传输表示与所述第一字线信号的第一和第二信号电平互补的两个信号电平的第二字线信号，所述存储器阵列还包括位线，所述存储单元结构连接在所述存储器阵列的一根位线和一字线对之间，
其特征在于：还包括一个包含第一电极、第二电极和栅电极的NMOS晶体管器件、一个包含第一电极、第二电极和栅电极的PMOS晶体管器件以及一存储电容，
其中，所述NMOS晶体管器件的第一电极与所述PMOS晶体管器件的第一电极相连，同时与所述存储器阵列的位线相连接，所述NMOS晶体管器件的第二电极与所述PMOS晶体管器件的第二电极相连，同时与所述存储电容相连接，所述NMOS晶体管器件的栅电极与所述字线对的第一字线相连，所述PMOS晶体管器件的栅极与所述字线对的第二字线相连接，所述NMOS和PMOS晶体管器件响应所述第一字线上的第一信号电平及其在所述第二字线上的所述互补信号电平同时截止，所述NMOS和PMOS晶体管器件响应所述第一字线上的第二信号电平及其在所述第二字线上的所述互补信号电平同时导通，
其中，所述位线与所述存储电容电连接，电荷响应所述NMOS和PMOS晶体管器件由所述字线上的信号而至的导通和截止而存入所述存储电容，或从所述存储电容读出。
2、按权利要求1的存储单元，其特征在于：所述NMOS晶体管器件的第一电极为源电极，所述PMOS晶体管器件的第一电极为漏电极，所述NMOS晶体管器件的第二电极为漏电极，所述PMOS晶体管器件的第二电极为源电极。
3、按权利要求1的存储单元，其特征在于：所述NMOS晶体管器件的第一电极和第二电极分别为漏电极和源电极，所述PMOS晶体管器件的第一和第二电极分别为源电极和漏电极。
4、按权利要求1的存储单元，其特征在于包括一半导体衬底;淀积在所述衬底上的硅外延层;注入到所述外延层中的h型阱区域;刻在所述衬底和外延层上并与它们绝缘的充满多晶硅的沟槽，该沟槽用来形成所述存储电容;设置在所述外延层上，包括源、漏掺杂区和栅电极的PMOS晶体管，所述源、漏区注入在所述n型阱区域中，所述栅电极由氧化层覆盖并设置在h型阱区之上，靠近所述源和漏区;垂直设置在所述PMOS晶体管器件之上的所述NMOS器件，包括设置在所述PMOS晶体管器件的源和漏区上方并与之电连接的源、漏掺杂区，以及设置在PMOS晶体管器件的所述栅电极之上与其电绝缘并覆盖一层氧化层的栅电极。
5、按权利要求4的存储单元，其特征在于：包括一层设置在所述多晶硅填满的沟槽上的导电材料，该材料在所述PMOS晶体管器件的源区之上，在所述NMOS晶体管器件的源区之下，将所述沟槽存储电容与所述两个源区电连接。
6、按权利要求4的存储单元，其特征在于：所述衬底为p+型硅，所述硅外延层为p型，所述沟槽中充填的多晶硅为p+型，所述n型阱由磷注入形成，所述PMOS和NMOS晶体管器件的源、漏区通过磷注入和硼注入形成以提供梯度变化的源/漏结。
7、一种制造组成半导体存储阵列的存储单元的方法，包括下列步骤：
（一）在半导体衬底上设置外延层，并在所述外延层和衬底内活性离子刻蚀出的沟槽，
（二）在所述沟槽的内壁上形成复合的氧化物/氮化物/氧化物存储绝缘层，
（三）用多晶硅填满沟槽并将其弄平整，
（四）通过表面杂质注入和深杂质注入在所述外延层中形成一反型的n型，
（五）生长栅氧化物并淀积用于PMOS器件的多晶硅栅极材料，在PMOS栅极上淀积一层氧化膜绝缘层，用金属板印刷法对所述氧化膜层制作图形，其特征在于下列步骤：
（六）对所述n型阱进行注入掺杂分别对PMOS和NMOS晶体管器件提供缓变的源/漏结，
（七）为了形成硅化物而将源/漏区的表面显露出来，所述栅极由步骤五中形成的所述氧化膜绝缘层将其与所述硅化物隔开，
（八）在所述硅化物、栅氧化物和绝缘区上形成一轻掺杂的硅膜，其中，用多晶硅结构淀积所述轻掺杂的硅膜，并用电子束退火进行再结晶，
（九）限定NMOS晶体管器件的有源区，生长一薄层NMOS栅极氧化物，
（十）通过硼注入调整沟道阈值电压，
（十一.淀积多晶硅NMOS晶体管器件栅极材料并刻出图形，
（十二）在所述NMOS栅电极边缘形成氧化物隔离区，
（十三）注入掺杂剂以获得传送器件的源/漏结，生长氧化物以覆盖器件。
8、按权利要求7的存储单元的制造方法，其特征在于：所述衬底由p型硅构成，所述硅外延层为p型，步骤（三）中填入所述沟槽的多晶硅为p+型，步骤（二）中形成的所述n型阱由磷注入形成，所述PMOS和NMOS晶体管器件的源和漏区由磷注入和硼注入形成，以提供缓变的源/漏结。
9、按权利要求7的存储单元的制造方法，其特征在于：所述轻掺杂的硅膜以多晶硅结构淀积而成，通过氢钝化处理使晶粒间界阱不活泼。
10、按权利要求7的存储单元的制造方法，其特征在于：所述轻掺杂的硅膜是淀积的非晶薄膜，经热处理和靠所述硅化的p+源/漏区的籽晶将其转变为单晶。
11、按权利要求7的存储单元的制造方法，其特征在于：所述轻掺杂的硅膜按多晶结构淀积而成，调整p型掺杂水平以提供一高的阈值电压。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/230,410 US4910709A (en) | 1988-08-10 | 1988-08-10 | Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell |
| US07/230,410 | 1988-08-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1040462A true CN1040462A (zh) | 1990-03-14 |
| CN1027411C CN1027411C (zh) | 1995-01-11 |
Family
ID=22865117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN89104647A Expired - Fee Related CN1027411C (zh) | 1988-08-10 | 1989-07-08 | Cmos晶体管和单电容动态随机存取存储单元及其制造方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4910709A (zh) |
| EP (1) | EP0354348A3 (zh) |
| JP (1) | JPH0644392B2 (zh) |
| KR (1) | KR920011046B1 (zh) |
| CN (1) | CN1027411C (zh) |
| CA (1) | CA1314991C (zh) |
| MY (1) | MY104092A (zh) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1084054C (zh) * | 1995-10-14 | 2002-05-01 | 日本电气株式会社 | 动态随机存取存储器件中的场效应晶体管及其存储单元结构 |
| CN101174631B (zh) * | 2006-11-03 | 2010-06-30 | 北京芯技佳易微电子科技有限公司 | 一种互补动态存储器的结构 |
| CN102709286A (zh) * | 2011-03-28 | 2012-10-03 | 南亚科技股份有限公司 | 隔离结构和包含隔离结构的元件结构 |
| CN103794650A (zh) * | 2014-02-21 | 2014-05-14 | 成都方舟微电子有限公司 | 集成esd保护的耗尽型功率mos器件及其制备方法 |
Families Citing this family (80)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5475642A (en) * | 1992-06-23 | 1995-12-12 | Taylor; David L. | Dynamic random access memory with bit line preamp/driver |
| US5898619A (en) * | 1993-03-01 | 1999-04-27 | Chang; Ko-Min | Memory cell having a plural transistor transmission gate and method of formation |
| US5543348A (en) * | 1995-03-29 | 1996-08-06 | Kabushiki Kaisha Toshiba | Controlled recrystallization of buried strap in a semiconductor memory device |
| US5905279A (en) * | 1996-04-09 | 1999-05-18 | Kabushiki Kaisha Toshiba | Low resistant trench fill for a semiconductor device |
| US5982659A (en) * | 1996-12-23 | 1999-11-09 | Lsi Logic Corporation | Memory cell capable of storing more than two logic states by using different via resistances |
| US5808932A (en) * | 1996-12-23 | 1998-09-15 | Lsi Logic Corporation | Memory system which enables storage and retrieval of more than two states in a memory cell |
| US5771187A (en) * | 1996-12-23 | 1998-06-23 | Lsi Logic Corporation | Multiple level storage DRAM cell |
| US5847990A (en) * | 1996-12-23 | 1998-12-08 | Lsi Logic Corporation | Ram cell capable of storing 3 logic states |
| US5761110A (en) * | 1996-12-23 | 1998-06-02 | Lsi Logic Corporation | Memory cell capable of storing more than two logic states by using programmable resistances |
| US5784328A (en) * | 1996-12-23 | 1998-07-21 | Lsi Logic Corporation | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array |
| US5956350A (en) * | 1997-10-27 | 1999-09-21 | Lsi Logic Corporation | Built in self repair for DRAMs using on-chip temperature sensing and heating |
| US5909404A (en) * | 1998-03-27 | 1999-06-01 | Lsi Logic Corporation | Refresh sampling built-in self test and repair circuit |
| US6376873B1 (en) | 1999-04-07 | 2002-04-23 | International Business Machines Corporation | Vertical DRAM cell with robust gate-to-storage node isolation |
| TWI230392B (en) | 2001-06-18 | 2005-04-01 | Innovative Silicon Sa | Semiconductor device |
| US20040228168A1 (en) | 2003-05-13 | 2004-11-18 | Richard Ferrant | Semiconductor memory device and method of operating same |
| US7335934B2 (en) | 2003-07-22 | 2008-02-26 | Innovative Silicon S.A. | Integrated circuit device, and method of fabricating same |
| US7606066B2 (en) | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
| US7683430B2 (en) | 2005-12-19 | 2010-03-23 | Innovative Silicon Isi Sa | Electrically floating body memory cell and array, and method of operating or controlling same |
| US7492632B2 (en) | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
| WO2007128738A1 (en) | 2006-05-02 | 2007-11-15 | Innovative Silicon Sa | Semiconductor memory cell and array using punch-through to program and read same |
| US8069377B2 (en) | 2006-06-26 | 2011-11-29 | Micron Technology, Inc. | Integrated circuit having memory array including ECC and column redundancy and method of operating the same |
| US7542340B2 (en) | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
| KR101277402B1 (ko) | 2007-01-26 | 2013-06-20 | 마이크론 테크놀로지, 인코포레이티드 | 게이트형 바디 영역으로부터 격리되는 소스/드레인 영역을 포함하는 플로팅-바디 ｄｒａｍ 트랜지스터 |
| WO2009031052A2 (en) | 2007-03-29 | 2009-03-12 | Innovative Silicon S.A. | Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor |
| US8064274B2 (en) | 2007-05-30 | 2011-11-22 | Micron Technology, Inc. | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same |
| US8085594B2 (en) | 2007-06-01 | 2011-12-27 | Micron Technology, Inc. | Reading technique for memory cell with electrically floating body transistor |
| US8194487B2 (en) | 2007-09-17 | 2012-06-05 | Micron Technology, Inc. | Refreshing data of memory cells with electrically floating body transistors |
| US8536628B2 (en) | 2007-11-29 | 2013-09-17 | Micron Technology, Inc. | Integrated circuit having memory cell array including barriers, and method of manufacturing same |
| US8349662B2 (en) | 2007-12-11 | 2013-01-08 | Micron Technology, Inc. | Integrated circuit having memory cell array, and method of manufacturing same |
| US8773933B2 (en) | 2012-03-16 | 2014-07-08 | Micron Technology, Inc. | Techniques for accessing memory cells |
| US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
| US8189376B2 (en) | 2008-02-08 | 2012-05-29 | Micron Technology, Inc. | Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same |
| US7957206B2 (en) | 2008-04-04 | 2011-06-07 | Micron Technology, Inc. | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same |
| US7947543B2 (en) | 2008-09-25 | 2011-05-24 | Micron Technology, Inc. | Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation |
| US7933140B2 (en) | 2008-10-02 | 2011-04-26 | Micron Technology, Inc. | Techniques for reducing a voltage swing |
| US7924630B2 (en) | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
| US8223574B2 (en) | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
| US8213226B2 (en) | 2008-12-05 | 2012-07-03 | Micron Technology, Inc. | Vertical transistor memory cell and array |
| US8319294B2 (en) | 2009-02-18 | 2012-11-27 | Micron Technology, Inc. | Techniques for providing a source line plane |
| WO2010102106A2 (en) | 2009-03-04 | 2010-09-10 | Innovative Silicon Isi Sa | Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device |
| WO2010114890A1 (en) | 2009-03-31 | 2010-10-07 | Innovative Silicon Isi Sa | Techniques for providing a semiconductor memory device |
| US8139418B2 (en) | 2009-04-27 | 2012-03-20 | Micron Technology, Inc. | Techniques for controlling a direct injection semiconductor memory device |
| US8508994B2 (en) | 2009-04-30 | 2013-08-13 | Micron Technology, Inc. | Semiconductor device with floating gate and electrically floating body |
| US8498157B2 (en) | 2009-05-22 | 2013-07-30 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
| US8537610B2 (en) | 2009-07-10 | 2013-09-17 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US9076543B2 (en) | 2009-07-27 | 2015-07-07 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
| US8199595B2 (en) | 2009-09-04 | 2012-06-12 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
| US8174881B2 (en) | 2009-11-24 | 2012-05-08 | Micron Technology, Inc. | Techniques for reducing disturbance in a semiconductor device |
| US8310893B2 (en) | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
| US8416636B2 (en) | 2010-02-12 | 2013-04-09 | Micron Technology, Inc. | Techniques for controlling a semiconductor memory device |
| US8411513B2 (en) | 2010-03-04 | 2013-04-02 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device having hierarchical bit lines |
| US8576631B2 (en) | 2010-03-04 | 2013-11-05 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
| US8369177B2 (en) | 2010-03-05 | 2013-02-05 | Micron Technology, Inc. | Techniques for reading from and/or writing to a semiconductor memory device |
| CN102812552B (zh) | 2010-03-15 | 2015-11-25 | 美光科技公司 | 半导体存储器装置及用于对半导体存储器装置进行偏置的方法 |
| US8411524B2 (en) | 2010-05-06 | 2013-04-02 | Micron Technology, Inc. | Techniques for refreshing a semiconductor memory device |
| JP5671418B2 (ja) * | 2010-08-06 | 2015-02-18 | 株式会社半導体エネルギー研究所 | 半導体装置の駆動方法 |
| US8531878B2 (en) | 2011-05-17 | 2013-09-10 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
| US9559216B2 (en) | 2011-06-06 | 2017-01-31 | Micron Technology, Inc. | Semiconductor memory device and method for biasing same |
| US8557657B1 (en) | 2012-05-18 | 2013-10-15 | International Business Machines Corporation | Retrograde substrate for deep trench capacitors |
| US9105470B2 (en) * | 2013-05-07 | 2015-08-11 | Infineon Technologies Austria Ag | Semiconductor device |
| US10367514B2 (en) | 2015-01-24 | 2019-07-30 | Circuit Seed, Llc | Passive phased injection locked circuit |
| WO2017019064A1 (en) * | 2015-07-29 | 2017-02-02 | Schober Robert C | Complementary current field-effect transistor devices and amplifiers |
| CN108141180A (zh) | 2015-07-30 | 2018-06-08 | 电路种子有限责任公司 | 基于互补电流场效应晶体管装置的低噪声跨阻抗放大器 |
| US10514716B2 (en) | 2015-07-30 | 2019-12-24 | Circuit Seed, Llc | Reference generator and current source transistor based on complementary current field-effect transistor devices |
| CN108141181A (zh) | 2015-07-30 | 2018-06-08 | 电路种子有限责任公司 | 多级式且前馈补偿的互补电流场效应晶体管放大器 |
| CN108140613B (zh) | 2015-12-14 | 2020-07-28 | 电路种子有限责任公司 | 过饱和电流场效应晶体管和跨阻抗mos装置 |
| US10541268B2 (en) | 2017-12-28 | 2020-01-21 | Spin Memory, Inc. | Three-dimensional magnetic memory devices |
| US10693056B2 (en) | 2017-12-28 | 2020-06-23 | Spin Memory, Inc. | Three-dimensional (3D) magnetic memory device comprising a magnetic tunnel junction (MTJ) having a metallic buffer layer |
| US10403343B2 (en) | 2017-12-29 | 2019-09-03 | Spin Memory, Inc. | Systems and methods utilizing serial configurations of magnetic memory devices |
| US10347308B1 (en) | 2017-12-29 | 2019-07-09 | Spin Memory, Inc. | Systems and methods utilizing parallel configurations of magnetic memory devices |
| US10424357B2 (en) | 2017-12-29 | 2019-09-24 | Spin Memory, Inc. | Magnetic tunnel junction (MTJ) memory device having a composite free magnetic layer |
| US10803916B2 (en) | 2017-12-29 | 2020-10-13 | Spin Memory, Inc. | Methods and systems for writing to magnetic memory devices utilizing alternating current |
| US10770510B2 (en) | 2018-01-08 | 2020-09-08 | Spin Memory, Inc. | Dual threshold voltage devices having a first transistor and a second transistor |
| US10319424B1 (en) | 2018-01-08 | 2019-06-11 | Spin Memory, Inc. | Adjustable current selectors |
| US10192789B1 (en) | 2018-01-08 | 2019-01-29 | Spin Transfer Technologies | Methods of fabricating dual threshold voltage devices |
| US10192787B1 (en) | 2018-01-08 | 2019-01-29 | Spin Transfer Technologies | Methods of fabricating contacts for cylindrical devices |
| US10192788B1 (en) | 2018-01-08 | 2019-01-29 | Spin Transfer Technologies | Methods of fabricating dual threshold voltage devices with stacked gates |
| US10497415B2 (en) | 2018-01-08 | 2019-12-03 | Spin Memory, Inc. | Dual gate memory devices |
| US10692556B2 (en) | 2018-09-28 | 2020-06-23 | Spin Memory, Inc. | Defect injection structure and mechanism for magnetic memory |
| US10878870B2 (en) | 2018-09-28 | 2020-12-29 | Spin Memory, Inc. | Defect propagation structure and mechanism for magnetic memory |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3457435A (en) * | 1965-12-21 | 1969-07-22 | Rca Corp | Complementary field-effect transistor transmission gate |
| US3701120A (en) * | 1969-09-18 | 1972-10-24 | Boeing Co | Analog capacitor memory with slow write-in and fast nondestructive read-out |
| US3699544A (en) * | 1971-05-26 | 1972-10-17 | Gen Electric | Three transistor memory cell |
| US3706891A (en) * | 1971-06-17 | 1972-12-19 | Ibm | A. c. stable storage cell |
| US3919569A (en) * | 1972-12-29 | 1975-11-11 | Ibm | Dynamic two device memory cell which provides D.C. sense signals |
| JPS51123531A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Diode memory |
| NL191683C (nl) * | 1977-02-21 | 1996-02-05 | Zaidan Hojin Handotai Kenkyu | Halfgeleidergeheugenschakeling. |
| US4203159A (en) * | 1978-10-05 | 1980-05-13 | Wanlass Frank M | Pseudostatic electronic memory |
| US4271488A (en) * | 1979-04-13 | 1981-06-02 | Tektronix, Inc. | High-speed acquisition system employing an analog memory matrix |
| US4308595A (en) * | 1979-12-19 | 1981-12-29 | International Business Machines Corporation | Array driver |
| JPS59180889A (ja) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | ダイナミツクメモリ |
| JPS60130160A (ja) * | 1983-12-19 | 1985-07-11 | Hitachi Ltd | 半導体記憶装置 |
| JPS60245266A (ja) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | 半導体装置およびその製造方法 |
| JPS6177359A (ja) * | 1984-09-21 | 1986-04-19 | Fujitsu Ltd | 半導体記憶装置 |
| JPS61281548A (ja) * | 1985-06-06 | 1986-12-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS62155556A (ja) * | 1985-12-27 | 1987-07-10 | Nec Corp | 半導体装置の製造方法 |
-
1988
- 1988-08-10 US US07/230,410 patent/US4910709A/en not_active Expired - Fee Related
-
1989
- 1989-05-25 CA CA000600744A patent/CA1314991C/en not_active Expired - Fee Related
- 1989-07-06 EP EP19890112325 patent/EP0354348A3/en not_active Ceased
- 1989-07-08 CN CN89104647A patent/CN1027411C/zh not_active Expired - Fee Related
- 1989-07-10 KR KR1019890009780A patent/KR920011046B1/ko not_active IP Right Cessation
- 1989-07-10 MY MYPI89000937A patent/MY104092A/en unknown
- 1989-07-19 JP JP1184889A patent/JPH0644392B2/ja not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1084054C (zh) * | 1995-10-14 | 2002-05-01 | 日本电气株式会社 | 动态随机存取存储器件中的场效应晶体管及其存储单元结构 |
| CN101174631B (zh) * | 2006-11-03 | 2010-06-30 | 北京芯技佳易微电子科技有限公司 | 一种互补动态存储器的结构 |
| CN102709286A (zh) * | 2011-03-28 | 2012-10-03 | 南亚科技股份有限公司 | 隔离结构和包含隔离结构的元件结构 |
| CN102709286B (zh) * | 2011-03-28 | 2016-01-13 | 南亚科技股份有限公司 | 隔离结构和包含隔离结构的元件结构 |
| CN103794650A (zh) * | 2014-02-21 | 2014-05-14 | 成都方舟微电子有限公司 | 集成esd保护的耗尽型功率mos器件及其制备方法 |
| CN103794650B (zh) * | 2014-02-21 | 2017-02-08 | 成都方舟微电子有限公司 | 集成esd保护的耗尽型功率mos器件及其制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| MY104092A (en) | 1993-11-30 |
| KR920011046B1 (ko) | 1992-12-26 |
| CA1314991C (en) | 1993-03-23 |
| JPH0644392B2 (ja) | 1994-06-08 |
| CN1027411C (zh) | 1995-01-11 |
| EP0354348A3 (en) | 1991-06-05 |
| EP0354348A2 (en) | 1990-02-14 |
| JPH0268792A (ja) | 1990-03-08 |
| US4910709A (en) | 1990-03-20 |
| KR900003891A (ko) | 1990-03-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1027411C (zh) | Cmos晶体管和单电容动态随机存取存储单元及其制造方法 | |
| US4864374A (en) | Two-transistor dram cell with high alpha particle immunity | |
| US4927779A (en) | Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor | |
| US5066607A (en) | Method of making a trench DRAM cell with dynamic gain | |
| US5463234A (en) | High-speed semiconductor gain memory cell with minimal area occupancy | |
| US4298962A (en) | Memory | |
| US4070653A (en) | Random access memory cell with ion implanted resistor element | |
| EP0147151A2 (en) | Semiconductor memory with stacked structure | |
| US6657250B1 (en) | Vertical flash memory cell with buried source rail | |
| US4999811A (en) | Trench DRAM cell with dynamic gain | |
| US4369564A (en) | VMOS Memory cell and method for making same | |
| US5321285A (en) | Carrier injection dynamic random access memory having stacked depletion region in Mesa | |
| US6048767A (en) | Method of forming a semiconductor memory device | |
| EP1181694B1 (en) | Plateline sensing | |
| CN102084427A (zh) | 具有独立的读取和写入存取晶体管的栅极横向晶闸管随机存取存储器(gltram)单元及具有该gltram的存储器器件和集成电路 | |
| US5973954A (en) | Reduced leakage DRAM storage unit | |
| US5128731A (en) | Static random access memory cell using a P/N-MOS transistors | |
| US7894255B1 (en) | Thyristor based memory cell | |
| JPH05299605A (ja) | 半導体記憶装置 | |
| US4276616A (en) | Merged bipolar/field-effect bistable memory cell | |
| KR100319623B1 (ko) | 디램 셀 어레이 및 그 제조방법 | |
| EP0782186B1 (en) | Method to form a buried, implanted plate for DRAM trench storage capacitors | |
| US4152779A (en) | MOS ram cell having improved refresh time | |
| EP0032279B1 (en) | One transistor-one capacitor memory cell | |
| CA1231445A (en) | High speed merged charge memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C15 | Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993) | ||
| OR01 | Other related matters | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CI01 | Publication of corrected invention patent application |
Correction item: Termination of patent right Correct: delete False: Wrong announcement Number: 36 Page: 561 Volume: 20 |
|
| ERR | Gazette correction |
Free format text: CORRECT: CESSATION OF PATENT RIGHT; FROM: WRONG PUBLICATION TO: DELETION |
|
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |