CN1027411C - Cmos晶体管和单电容动态随机存取存储单元及其制造方法 - Google Patents
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Abstract
一种互补型MOS单电容动态取样存储单元，该存贮单元无阈值损失，在无升压字线的情况下工作，它包括一存储电容和与该电容相连的、起两个互补晶体管器件作用的n型和p型传输器件，它们的栅极由RAM字线上的互补信号控制。
Description
本发明涉及使用互补型金属氧化物半导体（CMOS）晶体管和一个存储电容器的半导体存储器，更具体地说，本发明涉及用于大规模集成电路技术的动态操作的随机存取存储器（RAM）的结构与制造方法。
1986年12月30日公布的Kume等人的美国专利U.S.4，633，438题为“叠层半导体存储器”，它描述了一种进行动态操作的三管随机存取存储器，其中一个晶体管叠放在另一个晶体管上。写入用的晶体管置于读出用的晶体管上。其一端与晶体管的栅电极一起用来判断数据。其另一端与读出用晶体管的一端相连。
使用叠层互补型场效应管（FETS）可以获得能进行超大规模集成的存储单元，其中，两个FETS由重叠字线驱动。不过，这些字线是就读出和写入操作分别被驱动的，而不是象本发明那样由互补信号同时驱动的。
1981年1月2日公布的Saxe的美国专利U.S.4271488题为“使用模拟存储阵列的高速探测系统”，它描述了一种使用一个模拟存储阵列的高速探测系统，在该阵列中，连接到一根模拟总线的取样-保持元件按行和列排列，形成了一个MXN阵列。该系统可按快进-慢出模式工作，而且可以把这个模拟存储阵列做在一块单片集成电路的半导体芯片上。该模拟存储器包括含有取样/保持电路的元件。典型的取样/保持电路示于图2，包括说明互补型FET开关装置的图2c。不过，互补驱动信号是借助于倒相器54和与门52在单元内得到的，且该专利没有说明或教导使用提供前面所述的本发明的互补驱动信号的互补字线。
1972年10月24日公布的Chartecs等人的美国专利U.S.3，701，120题为“慢写入和快无损读出的模拟电容存储器”，它描述了一种能以相当慢的速度写入并独立地以相当快的速度无损读出的模拟存储器。当需存储部件时，就规定一种单独的写入和读出地址逻辑。每个存储部件包括一取样和保持微电路阵列，各微电路有一外存储电容、一个隔离放大器和独立的输入和输出模拟开关以响应垂直和水平写入读出寻址。
1969年7月22日公布的Buvns等人的第3457435号题为“互补型场效应晶体管传输门”的美国专利，描述了一种电路，该电路的导电类型相反的场效应晶体管对的源-漏通路并联连接，极性相反的信号被加在这两个晶体管的栅极上，加偏压使它们同时导通或截止。构成互补型晶体管的栅极由图4所示的两个互补信号驱动，以便消除由单个场效应晶体管的阈值电压引起的传输电压的下降。该专利没有披露这种电路在一个动态随机存取存储器（DRAM）单元中的用法。
Fujitsu有限公司的欧洲专利175-378A示出了一种三管元件的DRAM结构，它有读和写的选择线，这两根线结合成一根线连接到读和写选择晶体管的栅极。写选择晶体管放在读选择晶体管之上，其间用一绝缘层隔开并共用一个漏区。存储晶体管形成在硅衬底上，其形成深度与读选择晶体管
相同。两个晶体管的沟槽区域互相连接，各自被用来作为另两个晶体管的扩散（源或漏）区。
写和读选择线可以结合成一根单独的控制线或一根写/读选择线。这里，读和写选择晶体管的栅极都连接到写/读选择线上，靠具有不同的阈值电压来区分它们。
其它的参考文件包括U.S专利4，434，433、4，308，595、4，203，159、4，044，342、3，919，569和IBM技术公报Vol.23，No.10第4620页及Vol.18，No.3，第649页上的内容。
本发明的目的是提供一种互补型MOS单电容动态随机存取存储单元，它用无升压字线工作，没有阈值损失的问题。
本发明的另一个目的是提供一种CMOS单存储电容动态随机存取存储单元，它包括连接到存储电容器的n型和p型传送器件。
本发明再一个目的是提供一种带有两个互补型晶体管器件的真正的CMOS DRAM单元，两个互补型晶体管器件的栅极由互补字线控制。
本发明的前述目的及其它目的、特征和优点从下面结合附图的更具体的说明可以看得很清楚。
图1是按本发明原理的CMOS存储单元的电路简图。
图2为按本发明原理的CMOS存储单元结构的截面示意图。
图3和图4为制造图2所示的CMOS单元结构的某个生产步骤时的截面示意图。
图5是按本发明原理的CMOS存储单元另一实施例的截面示意图。
在使用动态随机存取存储器（DRAM）单元的集成电路工艺中，随着DRAM密度的增加，按比例减少由DRAM单元（如单管、单电容DRAM器件等）所占据的面积是重要的。按比例缩少DRAM元件中传送器件的尺寸的一般的困难是：要把“截止”器件上的漏电流减到最小，就希望有高的阈值电压，但反过来，要把存储的电荷增到最大并获得较高的电荷传送速度，又希望阈值电压小。随着器件尺寸的减少，利用升压字线来避免这一问题的传统方法就更困难了。例如，尺寸减少了的器件的击穿电压降低，这就限制了可能的升压字线电压电平。因此，对于DRAMS来说，重要的是设计一种新的允许使用无升压字线但又不存在所述阈值损失问题的单元。
本发明提供了一种克服了所述问题的互补型MOS单电容DRAM单元（CMOS-1C单元）。这种新单元的一个实施例的线路示意图示于图1。与常规的单管DRAM单元的区别在于，连接到存储电容器的传送器件不是只用一种类型的，而是在每个存贮单元中同时具有n型传送器件和p型传送器件，例如，图1中的器件10、12和14、16。这些互补器件的栅极18、22和20、24分别由互补字线26和28控制。在准备状态，字线26处于低电平使n型器件10、14截止，而互补字线28处于高电平使p型器件12、16截止。存贮单元38由传送器件10和12以及存储电容30构成，电荷存储在电容30中，在准备状态，单元38与位线（bitline）34相隔离。当该单元被选通时，字线26变为高电位，而互补字线28变为低电位，使器件10和12两者均导通。互补器件10和12构成一CMOS旁路门（pass gate），没有阈值损失。结果，不需要使字线电压电平升高来存储全电压（全电源电压VDD或零电压）。因此，能够通过位线34以全VDD的值（即没有阈值损失）从电容30读出总的传感电荷或将其存入电容30。
所述的存贮单元有几个优点：（1）对电荷传送即使不升高字线电压电平也没有阈值电压损失，因为不管是VDD还是零均可分别通过PMOS或NMOS全部传送;（2）因为在电荷传送期间的大部分时间两个器件都工作，所以信号传输较快;（3）因为该单元没有阈值损失并有高的电荷传送速率，所以在设计时可使传送器件的阈值电压的绝对值较大，以便抑制漏电。
本发明提供的制造工艺克服了在目前由单一器件占据的集成电路的那个面积上完成PMOS和NMOS两个器件的技术难题。本发明还提供了CMOS-1C单元的一种新颖结构，它和单器件单元占有大致同样的面积。
图2示出这种新的存贮单元结构的横截面示意图。图2中的CMOS-1C单元包括一个PMOS器件，该器件具有栅极46和分别在n阱44中的p+漏区40和源区42。该存贮单元还包括一个做在p+衬底50上的沟槽式电容（trench capacitor）48。沟槽式电容器48通过称为连接片（strap）的中间连接层52与传送器件p+源区42相连接。连接片的材
料可以用硅化钛、氮化钛/硅化钛或硅化钴等。PMOS传送器件之上是另一个n型（NMOS）传送器件，它包括在SOI（硅层在绝缘层之上）膜上制作的源区和漏区54、56。因为连接片52对p型和N型材料均是导电的，所以NMOS和PMOS器件的源和漏区42、40及54、56互相连接。NMOS器件的栅极18和PMOS器件的栅极20（也记作46）分别与字线26和28相连，它们连接到阵列端部它们各自的字线驱动器上。图2中的NMOS器件和PMOS器件分别对应于图1中的器件10和12，其工作方式如前所述。
下面叙述制造图2所示单元结构的工艺过程。尽管该工艺过程是就一个单元描述的，但应认为该工艺过程也适用于致密阵列中多个单元的制造。该工艺过程包括下列步骤：
步骤一.在p+半导体衬底50上淀积一p型外延层58，用活性离子刻蚀法（RIE）在p型外延层58和p+型衬底晶片50上刻出5至6微米的沟槽。（图3）
步骤二.在沟槽的壁上形成复合的氧化物/氮化物/氧化物存储器绝缘体80。（图3）
步骤三.用p+型多晶硅60填满沟槽并将其弄平整。
步骤四.用1.6Mev能量进行两次磷注入（一次表面注入和一次深注入）形成一反型的n型阱44。
步骤五.生长局部氧化物绝缘区82。
步骤六.通过单一的硼注入调整PMOS和圆周电路NMOS器件的阈值电压。
步骤七.生长栅极氧化物，在PMOS栅极上淀积n+多晶硅栅极材料46和氧化膜62并制出图形。
步骤八.在栅电极的边缘形成氧化物隔离层。
步骤九.分别对PMOS和NMOS器件注入磷和硼，以获得有梯度变化的源/漏结。
步骤十.为了形成硅化物52而将源/漏区42、40的表面露出来，同时栅极46仍由厚的绝缘体62使其与所述硅化物隔开。（图3）。
步骤十一.在硅化物和绝缘区上形成一轻掺杂的p型硅膜64，其形成方法可以有下面四种：（11a）、按多晶结构淀积所述膜64，再用电子束退火进行再结晶;（11b），按多晶结构淀积膜64，通过氢钝化处理使晶粒间界（grain boundavy tvaps）不活泼;（11c）.淀积一非晶硅膜64，因为硅化的p+源/漏区中的存在籽晶，使非晶硅能在热处理后转变为单晶;（11d）.淀积成多晶结构的膜64，调整p型掺杂水平以给出一个高阈值电压，这能用来把器件的漏电减到最小。
步骤十二.限定NMOS的有源区面积，并生长一薄层栅极氧化物。
步骤十三.通过硼注入来调整n沟道阈值电压。
步骤十四.淀积n+型多晶栅极材料18，并刻出图形，在栅电极边缘形成氧化物隔离层。
步骤十五.注入砷掺杂剂以获得n沟道传送器件的n+源/漏结54，56，并生长氧化物以包覆该器件。
步骤十六.淀积表面覆盖玻璃膜并回熔处理。
步骤十七.刻蚀接触孔84，淀积金属台面86，并刻出图形。
这样就得到了图2所示的元件结构。
本发明CMOS-1C元件的结构的另一个实施例示于图5。在这一理想化的结构中，CMOS旁路门是由PMOS器件72和NMOS器件74构成的，器件72和74均为垂直晶体管，除了与位线73的接触以及一个连接硅化物或金属连接电75外，它们与周围的导电材料完全隔离。整个元件，包括与其它元件的栅极互连以形成互补字线的多晶栅极77和78，可以做在沟槽68中，沟槽68是在覆盖着一厚层绝缘体79的导电衬底70上刻蚀形成的。存储电容由多晶硅电极90、薄的氧化物电介质71和板70构成。多晶硅电极90通过导电连接片75与器件扩散器相连。
Claims (11)
1、一种用于动态半导体存储器陈列的CMDS单电容存储器单元结构，包括字线对，第一字线用于传输表示第一和第二信号电平的第一字线信号，第二字线用于传输表示与所述第一字线信号的第一和第二信号电平互补的两个信号电平的第二字线信号，所述存储器陈列还包括位线，所述存储单元结构连接在所述存储器陈列的一根位线和一字线对之间。
其特征在于：还包括一个包含第一电极、第二电极和栅电极的NMOS晶体管器件、一个包含第一电极、第二电极和栅电极的PMOS晶体管器件以及一存储电容，
其中，所述NMOS晶体管器件的第一电极与所述PMOS晶体管器件的第一电极相连，同时与所述存储器陈列的位线相连接，所述NMOS晶体管器件的第二电极与所述PMOS晶体管器件的第二电极相连，同时与所述存储电容相连接，所述NMOS晶体管器件的栅电极与所述字线对的第一字线相连，所述PMOS晶体管器件的栅极与所述字线对的第二字线相连接，所述NMOS和PMOS晶体管器件响应所述第一字线上的第一信号电平及其在所述第二字线上的所述互补信号电平同时截止，所述NMOS和PMOS晶体管器件响应所述第一字线上的第二信号电平及其在所述第二字线上的所述互补信号电平同时导通，
其中，所述位线与所述存储电容电连接，电荷响应所述NMOS和PMOS晶体管器件由所述字线上的信号而至的导通和截止而存入所述存储电容，或从所述存储电容读出。
2、如权利要求1的存储单元，其特征在于：所述NMOS晶体管器件的第一电极为源电极，所述PMOS晶体管器件的第一电极为漏电极，所述NMOS晶体管器件的第二电极为漏电极，所述PMOS晶体管器件的第二电极为源电极。
3、按权利要求1的存储单元，其特征在于：所述NMOS晶体管器件的第一电极和第二电极分别为漏电极和源电极，所述PMOS晶体管器件的第一和第二电极分别为源电极和漏电极。
4、按权利要求1的存储单元，其特征在于包括一半导体衬底;淀积在所述衬底上的硅外延层;注入到所述外延层中的h型阱区域;刻在所述衬底和外延层上并与它们绝缘的充满多晶硅的沟槽，该沟槽用来形成所述存储电容;设置在所述外延层上，包括源、漏掺杂区和栅电极的PMOS晶体管，所述源、漏区注入在所述n型阱区域中，所述栅电极由氧化层覆盖并设置在h型阱区之上，靠近所述源和漏区;垂直设置在所述PMOS晶体管器件之上的所述NMOS器件，包括设置在所述PMOS晶体管器件的源和漏区上方并与之电连接的源、漏掺杂区，以及设置在PMOS晶体管器件的所述栅电极之上与其电绝缘并覆盖一层氧化层的栅电极。
5、按权利要求4的存储单元，其特征在于：包括一层设置在所述多晶硅填满的沟槽上的导电材料，该材料在所述PMOS晶体管器件的源区之上，在所述NMOS晶体管器件的源区之下，将所述沟槽存储电容与所述两个源区电连接。
6、按权利要求4的存储单元，其特征在于：所述衬底为p+型硅，所述硅外延层为p型，所述沟槽中充填的多晶硅为p+型，所述n型阱由磷注入形成，所述PMOS和NMOS晶体管器件的源、漏区通过磷注入和硼注入形成以提供梯度变化的源/漏结。
7、一种制造CMDS单电容存储单元的方法，包括下列步骤：
（一）在半导体衬底上设置外延层，并在所述外延层和衬底内活性离子刻蚀出的沟槽。
（二）在所述沟槽的内壁上形成复合的氧化物/氮化物/氧化物存储绝缘层。
（三）用多晶硅填满沟槽并将其弄平整，
（四）通过表面杂质注入和深杂质注入在所述外延层中形成一反型的n型，
（五）生长栅氧化物并淀积用于PMOS器件的多晶硅栅极材料，在PMOS栅极上淀积一层氧化膜绝缘层，用金属板印刷法对所述氧化膜层制作图形，其特征在于下列步骤：
（六）对所述n型阱进行注入掺杂分别对PMOS和NMOS晶体管器件提供缓变的源/漏结，
（七）为了形成硅化物而将源/漏区的表面显露出来，所述栅极由步骤五中形成的所述氧化膜绝缘层将其与所述硅化物隔开，
（八）在所述硅化物、栅氧化物和绝缘区上形成一轻掺杂的硅膜，其中，用多晶硅结构淀积所述轻掺杂的硅膜，并用电子束退火进行再结晶，
（九）限定NMOS晶体管器件的有源区，生长一薄层NMOS栅极氧化物，
（十）通过硼注入调整沟道阈值电压，
（十一）淀积多晶硅NMOS晶体管器件栅极材料并刻出图形，
（十二）在所述NMOS栅电极边缘形成氧化物隔离区，
（十三）注入掺杂剂以获得传送器件的源/漏结，生长氧化物以覆盖器件。
8、按权利要求7的存储单元的制造方法，其特征在于：所述衬底由p型硅构成，所述硅外延层为p型，步骤（三）中填入所述沟槽的多晶硅为p+型，步骤（二）中形成的所述n型阱由磷注入形成，所述PMOS和NMOS晶体管器件的源和漏区由磷注入和硼注入形成，以提供缓变的源/漏结。
9、按权利要求7的存储单元的制造方法，其特征在于：所述轻掺杂的硅膜以多晶硅结构淀积而成，通过氢钝化处理使晶粒间界阱不活泼。
10、按权利要求7的存储单元的制造方法，其特征在于：所述轻掺杂的硅膜是淀积的非晶薄膜，经热处理和靠所述硅化的p+源/漏区的籽晶将其转变为单晶。
11、按权利要求7的存储单元的制造方法，其特征在于：所述轻掺杂的硅膜按多晶结构淀积而成，调整p型掺杂水平以提供一高的阈值电压。
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| JPS59180889A (ja) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | ダイナミツクメモリ |
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| JPS60245266A (ja) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | 半導体装置およびその製造方法 |
| JPS6177359A (ja) * | 1984-09-21 | 1986-04-19 | Fujitsu Ltd | 半導体記憶装置 |
| JPS61281548A (ja) * | 1985-06-06 | 1986-12-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS62155556A (ja) * | 1985-12-27 | 1987-07-10 | Nec Corp | 半導体装置の製造方法 |
-
1988
- 1988-08-10 US US07/230,410 patent/US4910709A/en not_active Expired - Fee Related
-
1989
- 1989-05-25 CA CA000600744A patent/CA1314991C/en not_active Expired - Fee Related
- 1989-07-06 EP EP19890112325 patent/EP0354348A3/en not_active Ceased
- 1989-07-08 CN CN89104647A patent/CN1027411C/zh not_active Expired - Fee Related
- 1989-07-10 KR KR1019890009780A patent/KR920011046B1/ko not_active IP Right Cessation
- 1989-07-10 MY MYPI89000937A patent/MY104092A/en unknown
- 1989-07-19 JP JP1184889A patent/JPH0644392B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| MY104092A (en) | 1993-11-30 |
| KR920011046B1 (ko) | 1992-12-26 |
| CN1040462A (zh) | 1990-03-14 |
| CA1314991C (en) | 1993-03-23 |
| JPH0644392B2 (ja) | 1994-06-08 |
| EP0354348A3 (en) | 1991-06-05 |
| EP0354348A2 (en) | 1990-02-14 |
| JPH0268792A (ja) | 1990-03-08 |
| US4910709A (en) | 1990-03-20 |
| KR900003891A (ko) | 1990-03-27 |
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