CN103794650B - 集成esd保护的耗尽型功率mos器件及其制备方法 - Google Patents

集成esd保护的耗尽型功率mos器件及其制备方法 Download PDF

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CN103794650B
CN103794650B CN201410060184.0A CN201410060184A CN103794650B CN 103794650 B CN103794650 B CN 103794650B CN 201410060184 A CN201410060184 A CN 201410060184A CN 103794650 B CN103794650 B CN 103794650B
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蒲奎
周仲建
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ARK MICROELECTRONICS Co Ltd
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Abstract

本发明公开了一种集成ESD保护的耗尽型功率MOS器件及其制备方法，所述方法包括：场氧化层生长，环区光刻和环区屏蔽氧化层生长；环区推结和环区氧化层再生长；有源区光刻；阱区屏蔽氧化层生长；ESD多晶硅淀积，ESD离子注入；ESD多晶硅光刻和刻蚀；阱区较高温推结和阱区屏蔽氧化层去除；VTH屏蔽氧化层生长；栅氧生长，栅极多晶硅淀积；栅极多晶硅光刻和刻蚀；源区光刻和离子注入，源区推结；ILD氧化层淀积，接触孔光刻和刻蚀；金属淀积，金属光刻和刻蚀，背面减薄和背面金属化。本发明的优点是：制造的耗尽型MOSFET器件能够有效地减小ESD多晶硅二极管的泄漏电流，提高了该器件抗ESD冲击的能力。

Description

集成ESD保护的耗尽型功率MOS器件及其制备方法
技术领域
本发明属于半导体电力电子器件制造技术领域，特别地，涉及一种集成ESD保护的耗尽型功率MOS器件的制备方法。
背景技术
MOSFET器件分为增强型MOSFET和耗尽型MOSFET，对于耗尽型MOSFET，因为在漏极和源极的氧化层内掺入了大量离子，使得在栅压VGS=0时，在氧化层的掺杂离子的作用下，衬底表层中会感应出与衬底掺杂类型相反多数载流子形成反型层，即源-漏之间存在沟道，只要在源-漏之间加上正向电压，就能产生漏极电流，当加上栅压VGS时，会使多数载流子流出沟道，反型层变窄沟道电阻变大，当栅压VGS增大到一定时，反型层消失，沟道被耗尽，耗尽型MOSFET会关断。
然而，现有的制造MOSFET器件的过程中常常发生ESD(Electro-StaticDischarge)事件，如果半导体器件位于ESD放电的通路上，很有可能损坏。功率MOSFET器件抗ESD冲击能力主要取决于两个因素：第一，栅氧击穿电压，功率MOS器件中的栅氧很薄，一般介于10nm~200nm之间，其击穿电压约为10V~100V，如果施加到器件栅极-源极的ESD有效电压超过栅氧的击穿电压，则氧化层损坏，器件失效；第二，栅极-源极电容，此电容越大，器件吸收ESD放电的能力越强，施加到栅极-源极的ESD有效电压越低，例如，当此电容较大时，3kV的ESD放电可能只会带来40V~50V的ESD有效电压应力。
另外，公开号为CN102931093的中国专利公开了一种N沟道耗尽型功率MOSFET器件及制造方法，其包括：进行离子注入和退火工艺，在所述栅极之间的有源区中形成P型阱区，并且在进行离子注入和退火工艺的步骤之间，进行氧化工艺，以及进行电子辐照工艺，以在相邻的两个P型阱区中相邻近的两源区之间形成耗尽层，通过电子辐照工艺，被电子辐照产生的电子在器件的硅表面形成电子导通沟道，形成耗尽层，该耗尽型MOSFET器件具有较短的反响恢复时间，可以节约工艺步骤和提高生产效率。传统方法的缺点是：如果直接制造ESD保护二极管，则会导致极差的器件特性，例如：极大的反向泄漏电流，较大的正向压降，以及极大的低掺杂区寄生电阻，并且，在ESD保护二极管设计中，极大的反向泄漏电流最终体现为功率MOS器件极大的栅极-源极的泄漏电流，这直接增加了器件的栅极驱动功耗，同时，极大的寄生电阻在ESD事件中会产生较大的欧姆压降，使栅极-源极间所承受的ESD有效电压随ESD浪涌电流迅速上升，极大地降低了器件抗ESD冲击的能力。
发明内容
针对上述不足，本发明所要解决的技术问题在于提供一种集成ESD保护的耗尽型功率MOS器件的制备方法，其能够有效地减小ESD多晶硅二极管的泄漏电流，提高了器件抗ESD冲击的能力。
本发明的技术方案是这样实现的，一种集成ESD保护的耗尽型功率MOS器件的制备方法，其特征在于，包括：步骤一、场氧化层生长，环区光刻和环区场氧刻蚀，光刻胶去除，环区屏蔽氧化层生长，和环区离子注入；步骤二、环区推结和环区氧化层再生长；步骤三、有源区光刻，场氧刻蚀和光刻胶去除；步骤四、阱区屏蔽氧化层生长，阱区光刻，阱区离子注入，光刻胶去除；步骤五、ESD多晶硅淀积，ESD离子注入；步骤六、ESD多晶硅光刻和刻蚀，光刻胶去除；步骤七、阱区较高温推结，和阱区屏蔽氧化层去除；步骤八、VTH屏蔽氧化层生长，VTH离子注入；步骤九、栅氧生长，栅极多晶硅淀积；步骤十、栅极多晶硅光刻和刻蚀，光刻胶去除；步骤十一、源区光刻和离子注入，源区推结；步骤十二、ILD氧化层淀积，ILD致密，接触孔光刻和刻蚀，回流，接触孔注入；步骤十三、金属淀积，金属光刻和刻蚀，背面减薄和背面金属化。
通过上述技术方案可以看出，本发明的有益效果是：
第一，增加了ESD多晶硅层及其相关工艺，用于ESD保护二极管的制造，该ESD多晶硅层形成于阱区较高温推结之前，故在后续的阱区较高温推结过程中，多晶硅的晶粒尺寸会显著增大，晶粒界面会显著减少，这为制造特性较好的多晶硅二极管等提供了条件。特别地，在ESD多晶硅刻蚀时，除ESD保护结构所在区域外，其他区域的ESD多晶硅都需要完全去除，尽量避免影响后续栅极多晶硅的淀积和刻蚀。
第二，和传统工艺兼容，本发明工艺的VTH离子注入仍在阱区较高温推结之后，而栅极多晶硅淀积仍在VTH离子注入之后，故栅极多晶硅仍然没有经历较高温退火，无法完成再结晶和再生长过程。但是，由于栅极多晶硅不再用于制造多晶硅二极管，其结晶程度和晶粒大小就不再重要，同时，由于不再用于制造多晶硅二极管，栅极多晶硅可进行原位重掺杂，以尽量减小栅极等效寄生串联电阻，加快器件开关速度。
附图说明
为了更清楚地描述本发明所涉及的相关技术方案，下面将其涉及的附图予以简单说明，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明的集成ESD保护的耗尽型功率MOS器件的制备方法的第一实施例的流程框图；
图2a－图2d为图1所示实施例的工艺流程图，图2a－图2d整体构成图1所示实施例的完整工艺流程，为了便于描述在本申请中统称图2；
图3为本发明的集成ESD保护的耗尽型功率MOS器件的制备方法的第二实施例的流程框图；
图4a－图4d为图3所示实施例的工艺流程图，图4a－图4d整体构成图1所示实施例的完整工艺流程，为了便于描述在本申请中统称图4。
图中各个附图标记示意：
1—环区屏蔽氧化层 2—再生长氧化层 3—光刻胶
4—栅极多晶硅 5—ILD氧化层 6—正面金属
7—背面金属 8—ESD多晶硅 9—VTH屏蔽氧化层
10—栅极多晶硅 11—栅极氧化层 12—阱区屏蔽氧化层
13—栅极 14—漏极 15—源极。
具体实施方式
为了便于本领域的技术人员对本发明的进一步理解，清楚地认识本发明的技术方案，完整、充分地公开本发明的相关技术内容，下面结合附图对本发明的具体实施方式进行详细的描述，当然，所描述的具体实施方式仅仅列举了本发明一部分实施例，而不是全部的实施例，用于帮助理解本发明及其核心思想。
实施例1，参见图1和图2，本发明的集成ESD保护的耗尽型功率MOS器件的制备方法包括：步骤一、场氧化层生长，环区光刻和环区场氧刻蚀，光刻胶去除，环区屏蔽氧化层生长，和环区离子注入；步骤二、环区推结和环区氧化层再生长；步骤三、有源区光刻，场氧刻蚀和光刻胶去除；步骤四、阱区屏蔽氧化层生长，阱区光刻，阱区离子注入，光刻胶去除；步骤五、ESD多晶硅淀积，ESD离子注入；步骤六、ESD多晶硅光刻和刻蚀，光刻胶去除；步骤七、阱区较高温推结，和阱区屏蔽氧化层去除；步骤八、VTH屏蔽氧化层生长，VTH离子注入；步骤九、栅氧生长，栅极多晶硅淀积；步骤十、栅极多晶硅光刻和刻蚀，光刻胶去除；步骤十一、源区光刻和离子注入，源区推结；步骤十二、ILD氧化层淀积，ILD致密，接触孔光刻和刻蚀，回流，接触孔注入；步骤十三、金属淀积，金属光刻和刻蚀，背面减薄和背面金属化。
优选地，所述的步骤一进一步包括：场氧化层生长的条件为：厚度600~2000nm，1000~1100℃，环区屏蔽氧化层生长的具体条件为：厚度20~50nm，850~900℃，环区离子注入采用硼离子注入，剂量1E14~2E15cm-2, 能量40~100keV。
优选地，所述的步骤二进一步包括：环区氧化层厚度400~1000nm，1000~1150℃。
优选地，所述的步骤四进一步包括：阱区屏蔽氧化层生长的具体条件为：厚度为20~50nm，850~900℃；阱区离子注入为：硼离子注入，剂量1E13~1E14cm-2，能量40~100keV。
优选地，所述的步骤五进一步包括：ESD离子注入采用硼离子注入，剂量2E13~1E14cm-2，能量60keV。
优选地，所述的步骤六进一步包括：ESD多晶硅光刻和刻蚀采用等离子干法刻蚀。
优选地，所述的步骤七进一步包括：阱区较高温推结的条件为：1150~1175℃，时间为60~120分钟。
优选地，所述的步骤八进一步包括：VTH屏蔽氧化层生长的具体条件为：厚度为20~50nm，850~900℃；VTH离子注入采用砷离子注入，剂量1E12~1E13cm-2，能量40~100keV。
优选地，所述的步骤九进一步包括：栅氧生长的具体条件为：厚度为70~110nm，900℃；栅极多晶硅淀积的具体条件为：LPCVD, 原位掺杂，掺杂砷或磷，掺杂剂量大于1E20cm-2。
在具体的实施例中，VTH离子注入仍在阱区较高温推结之后，而栅极多晶硅淀积仍在VTH离子注入之后，故栅极多晶硅仍然没有经历较高温退火，无法完成再结晶和再生长过程。但是，由于栅极多晶硅不再用于制造多晶硅二极管（BJT，SCR），其结晶程度和晶粒大小就不再重要。同时，由于不再用于制造多晶硅二极管（BJT，SCR），栅极多晶硅可进行原位重掺杂，以尽量减小栅极等效寄生串联电阻，加快器件开关速度。
优选地，所述的步骤十进一步包括：栅极多晶硅刻蚀采用等离子干法刻蚀。
优选地，所述的步骤十一进一步包括：源区离子注入采用：砷和/或磷离子注入，剂量1E15~1E16cm-2, 能量40~100keV，源区推结的具体条件为：850~900℃，时间为30分钟。
优选地，所述的步骤十二进一步包括：ILD(Inter-Level Dielectric)氧化层淀积的具体条件为：LPCVD或PECVD，厚度为600~1000nm；ILD致密的具体条件为： 850~900℃，时间为15~30分钟；回流的具体条件为： 850~900℃，时间为15~30分钟；接触孔注入为：硼离子注入，剂量2E14~2E15cm-2，能量40~100keV。
优选地，所述的步骤十三进一步包括：溅射金属Al, 厚度为4.0um，然后进行金属的光刻和刻蚀，背面金属化：金属Ti，厚度为1kA；金属Ni，厚度为3kA，或金属Ag，厚度为10kA。
实施例2，参见图3和图4，本实施例中，ESD多晶硅还可淀积于环区推结和再氧化之后，阱区屏蔽氧化层形成之前。其制备方法包括：步骤一、场氧化层生长，环区光刻和环区场氧刻蚀，光刻胶去除，环区屏蔽氧化层生长，和环区离子注入；步骤二、环区推结和环区氧化层再生长；步骤三、ESD多晶硅淀积，ESD离子注入；步骤四、ESD多晶硅光刻和刻蚀；步骤五、有源区光刻，场氧刻蚀和光刻胶去除；步骤六、阱区屏蔽氧化层生长，阱区光刻，阱区离子注入，光刻胶去除；步骤七、阱区较高温推结和阱区屏蔽氧化层去除；步骤八、VTH屏蔽氧化层生长，VTH离子注入；步骤九、栅氧生长，栅极多晶硅淀积；步骤十、栅极多晶硅光刻和刻蚀，光刻胶去除；步骤十一、源区光刻和离子注入，源区推结；步骤十二、ILD氧化层淀积，ILD致密，接触孔光刻和刻蚀，回流，接触孔注入；步骤十三、金属淀积，金属光刻和刻蚀，背面减薄和背面金属化。
优选地，所述的步骤一进一步包括：场氧化层生长的条件为：厚度600~2000nm，1000~1100℃，环区屏蔽氧化层生长的具体条件为：厚度20~50nm，850~900℃，环区离子注入采用硼离子注入，剂量1E14~2E15cm-2, 能量40~100keV。
优选地，所述的步骤二进一步包括：环区氧化层厚度400~1000nm，1000~1150℃。
优选地，所述的步骤三进一步包括：ESD离子注入采用硼离子注入，剂量2E13~1E14cm-2，能量60keV。
优选地，所述的步骤四进一步包括：ESD多晶硅光刻和刻蚀采用等离子干法刻蚀。
优选地，所述的步骤六进一步包括：阱区屏蔽氧化层生长的具体条件为：厚度为20~50nm，850~900℃；阱区离子注入为：硼离子注入，剂量1E13~1E14cm-2，能量40~100keV。
优选地，所述的步骤七进一步包括：阱区较高温推结的条件为：1150~1175℃，时间为60~120分钟。
优选地，所述的步骤八进一步包括：VTH屏蔽氧化层生长的具体条件为：厚度为20~50nm，850~900℃；VTH离子注入采用砷离子注入，剂量1E12~1E13cm-2，能量40~100keV。
优选地，所述的步骤九进一步包括：栅氧生长的具体条件为：厚度为70~110nm，900℃；栅极多晶硅淀积的具体条件为：LPCVD, 原位掺杂，掺杂砷或磷，掺杂剂量大于1E20cm-2。
优选地，所述的步骤十进一步包括：栅极多晶硅刻蚀采用等离子干法刻蚀。
优选地，所述的步骤十一进一步包括：源区离子注入采用：砷和/或磷离子注入，剂量1E15~1E16cm-2, 能量40~100keV，源区推结的具体条件为：850~900℃，时间为30分钟。
优选地，所述的步骤十二进一步包括：ILD(Inter-Level Dielectric)氧化层淀积的具体条件为：LPCVD或PECVD，厚度为600~1000nm；ILD致密的具体条件为： 850~900℃，时间为15~30分钟；回流的具体条件为： 850~900℃，时间为15~30分钟；接触孔注入为：硼离子注入，剂量2E14~2E15cm-2，能量40~100keV。
优选地，所述的步骤十三进一步包括：溅射金属Al, 厚度为4.0um，然后进行金属的光刻和刻蚀，背面金属化：金属Ti，厚度为1kA；金属Ni，厚度为3kA，或金属Ag，厚度为10kA。
将本发明工艺与传统方法进行对比进行测试，其结果如表一所示：
工艺 反向泄漏电流 寄生电阻 抗ESD能力（HBM模型）
传统方法 1.0 1.0 1.0
本发明 0.001~0.01 0.001~0.01 10~20
表一
由此可见，在耗尽型功率MOS器件制造中，采用本发明工艺实现ESD保护结构，具有反向泄漏电流小，寄生电阻小，抗ESD冲击能力强的特点，极大地改进了器件的坚固性和可靠性。本领域技术人员还可将本发明工艺用于制造SCR（Silicon Controlled Rectifier）器件来实现ESD保护结构。
基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，和/或在不背离本发明精神及其实质的情况下，即使对各个步骤的执行顺序进行了改变，以及根据本发明做出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明保护的范围。

Claims (10)

1.一种集成ESD保护的耗尽型功率MOS器件的制备方法，其特征在于，包括：
步骤一、场氧化层生长，环区光刻和环区场氧刻蚀，光刻胶去除，环区屏蔽氧化层生长，和环区离子注入；
步骤二、环区推结和环区氧化层再生长；
步骤三、有源区光刻，场氧刻蚀和光刻胶去除；
步骤四、阱区屏蔽氧化层生长，阱区光刻，阱区离子注入，光刻胶去除；
步骤五、ESD多晶硅淀积，ESD离子注入；
步骤六、ESD多晶硅光刻和刻蚀，光刻胶去除；
步骤七、阱区较高温推结，和阱区屏蔽氧化层去除，所述较高温为1150~1175℃；
步骤八、VTH屏蔽氧化层生长，VTH离子注入；
步骤九、栅氧生长，栅极多晶硅淀积；
步骤十、栅极多晶硅光刻和刻蚀，光刻胶去除；
步骤十一、源区光刻和离子注入，源区推结；
步骤十二、ILD氧化层淀积，ILD致密，接触孔光刻和刻蚀，回流，接触孔注入；
步骤十三、金属淀积，金属光刻和刻蚀，背面减薄和背面金属化。
2.如权利要求1所述的方法，其特征在于，所述的步骤四进一步包括：
阱区屏蔽氧化层生长的具体条件为：厚度为20~50nm，850~900℃；
阱区离子注入为：硼离子注入，剂量1E13~1E14cm-2，能量40~100keV。
3.如权利要求2所述的方法，其特征在于，所述的步骤五进一步包括：ESD离子注入采用硼离子注入，剂量2E13~1E14cm-2，能量60keV。
4.如权利要求3所述的方法，其特征在于，所述的步骤六进一步包括：ESD多晶硅光刻和刻蚀采用等离子干法刻蚀。
5.如权利要求4所述的方法，其特征在于，所述的步骤七进一步包括：阱区较高温推结的时间为60~120分钟。
6.如权利要求5所述的方法，其特征在于，所述的步骤八进一步包括：
VTH屏蔽氧化层生长的具体条件为：厚度为20~50nm，850~900℃；
VTH离子注入采用砷离子注入，剂量1E12~1E13cm-2，能量40~100keV。
7.如权利要求6所述的方法，其特征在于，所述的步骤九进一步包括：
栅氧生长的具体条件为：厚度为70~110nm，900℃；
栅极多晶硅淀积的具体条件为：LPCVD,原位掺杂,掺杂砷或磷,掺杂剂量大于1E20cm-2。
8.如权利要求7所述的方法，其特征在于，所述的步骤十二进一步包括：
ILD氧化层淀积的具体条件为：LPCVD或PECVD，厚度为600~1000nm；
ILD致密的具体条件为： 850~900℃，时间为15~30分钟；
回流的具体条件为： 850~900℃，时间为15~30分钟；
接触孔注入为：硼离子注入，剂量2E14~2E15cm-2，能量40~100keV。
9.一种集成ESD保护的耗尽型功率MOS器件的制备方法，其特征在于，包括：
步骤一、场氧化层生长，环区光刻和环区场氧刻蚀，光刻胶去除，环区屏蔽氧化层生长，和环区离子注入；
步骤二、环区推结和环区氧化层再生长；
步骤三、ESD多晶硅淀积，ESD离子注入；
步骤四、ESD多晶硅光刻和刻蚀；
步骤五、有源区光刻，场氧刻蚀和光刻胶去除；
步骤六、阱区屏蔽氧化层生长，阱区光刻，阱区离子注入，光刻胶去除；
步骤七、阱区较高温推结和阱区屏蔽氧化层去除，所述较高温为1150~1175℃；
步骤八、VTH屏蔽氧化层生长，VTH离子注入；
步骤九、栅氧生长，栅极多晶硅淀积；
步骤十、栅极多晶硅光刻和刻蚀，光刻胶去除；
步骤十一、源区光刻和离子注入，源区推结；
步骤十二、ILD氧化层淀积，ILD致密，接触孔光刻和刻蚀，回流，接触孔注入；
步骤十三、金属淀积，金属光刻和刻蚀，背面减薄和背面金属化。
10.一种采用如权利要求1至9中任何一项所述的方法制造的耗尽型功率MOSFET器件。
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US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
US6022769A (en) * 1997-12-23 2000-02-08 Texas Instruments -- Acer Incorporated Method of making self-aligned silicided MOS transistor with ESD protection improvement
CN102891143A (zh) * 2012-10-12 2013-01-23 成都芯源系统有限公司 具有静电放电保护模块的半导体器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1040462A (zh) * 1988-08-10 1990-03-14 国际商用机器公司 Cmos晶体管和单电容动态随机存取存储单元及其制造方法
US6022769A (en) * 1997-12-23 2000-02-08 Texas Instruments -- Acer Incorporated Method of making self-aligned silicided MOS transistor with ESD protection improvement
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
CN102891143A (zh) * 2012-10-12 2013-01-23 成都芯源系统有限公司 具有静电放电保护模块的半导体器件及其制造方法

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