CN110797263A - 功率mosfet器件及其制造方法 - Google Patents
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Abstract
本发明涉及一种功率MOSFET器件及其制造方法,步骤为:在N+Sub上生长外延层N‑epi;生长场氧化层,在有源区刻蚀场氧化层,在终端区注入P+并退火;在有源区生长屏蔽氧化层,注入杂质磷形成JFET区;在外延层生长牺牲氧化层并腐蚀,热氧化生长栅氧化层;在栅氧化层之上淀积多晶硅并刻蚀;在栅氧化层和多晶硅上注入Boron离子形成自对准的P阱;对PW进行热氧化推结;N+注入,形成自对准的源极N+区;N+退火处理;淀积LPSIN并进行源极P+高能注入;层间介质ILD淀积;接触孔刻蚀,Ti/TiN淀积;正面金属淀积并刻蚀;衬底减薄,背面注入,背面金属淀积,合金化,形成完整器件结构。本发明将closed结构改为open结构,采用LPSIN掩蔽的源极P+注入,提高了器件的通流能力。
Description
技术领域
本发明属于半导体功率器件技术领域,具体涉及一种功率MOSFET器件及其制造方法。
背景技术
功率MOSFET (Metal Oxide Semiconductor Field Effect Transistor),金属氧化物半导体场效应晶体管,是目前市场最为常见的功率半导体器件之一,功率MOSFET通常采用纵向的垂直结构,其源极和漏极在晶圆片两个相对的平面,从而可以流过大的电流和具有高的电压。功率MOSFET具有很低的栅极驱动功率,较快的开关速度和优异的热稳定性,以及良好的并联工作能力。除以上优点外,功率MOSFET的主要缺点为为其导通电阻较高,因为对于高压器件,其具有一电阻率高的N-漂移区所致,如减薄这层漂移区的厚度或者减少其电阻率,则产品的耐压会急剧下降。
此外,功率MOSFET结构中还存在有一纵向的NPN结构,器件在实际工作中要避免该NPN管开启,该NPN开启会导致器件不再受栅极控制,引起电流集中,甚至导致器件产生不可逆的损坏。
发明内容
本发明的目的是提供一种功率MOSFET器件及其制造方法,可以在不影响器件击穿电压的前提下,降低功率MOSFET的导通电阻,提高器件通流能力。
本发明所采用的技术方案为:
功率MOSFET器件的制造方法,其特征在于:
所述方法包括以下步骤:
步骤1:选取N+ Sub作为制作VDMOS外延层的衬底片;
步骤2:在所选取的N+ Sub上面生长外延层N-epi;
步骤3:在所生长的N-epi外延层上部生长一层场氧化层,并在器件有源区刻蚀场氧化层,在终端区注入P+并退火;
步骤4:在器件有源区生长一层屏蔽氧化层,之后注入杂质磷形成JFET区;
步骤5:在外延层上表面生长牺牲氧化层并腐蚀,之后热氧化生长栅氧化层;
步骤6:在栅氧化层之上淀积多晶硅并刻蚀形成多晶栅极;
步骤7:在栅氧化层和多晶硅的上表面注入Boron离子形成自对准的P阱;
步骤8:对PW进行热氧化推结;
步骤9:N+注入,形成自对准的源极N+区;
步骤10:N+退火处理;
步骤11:淀积LPSIN并进行源极P+高能注入;
步骤12:层间介质ILD淀积;
步骤13:接触孔刻蚀,Ti/TiN淀积;
步骤14:正面金属淀积并刻蚀;
步骤15:衬底减薄,背面注入,背面金属淀积,合金化,形成完整器件结构。
如所述的制造方法制得的功率MOSFET器件。
本发明具有以下优点:
本发明增大了电流密度,将closed结构改为open结构,采用LPSIN掩蔽的源极P+注入,并采用特殊源极N+区设计,在保证平面功率VDMOS器件BVDSS和EAS能力不变的情况下提高器件的通流能力,降低器件的导通电阻,克服了现有平面功率VDMOS为closed栅极结构、沟道结构被一部分栅极占用、产品比导通电阻Rsp偏大的问题。
附图说明
图1为步骤1示意图。
图2为步骤2示意图。
图3为步骤3示意图。
图4为步骤4示意图。
图5为步骤5示意图。
图6为步骤6示意图。
图7为步骤7示意图。
图8为步骤8示意图。
图9为步骤9示意图。
图10为步骤10示意图。
图11为步骤11示意图。
图12为步骤12示意图。
图13为步骤13示意图。
图14为步骤14示意图。
图15为步骤15示意图。
图16为现有平面功率VDMOS栅极结构顶视图。
图17为本发明栅极结构顶视图。
图18为本发明工艺流程图。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
现有的平面close栅极结构功率MOSFET,将击穿点引入cell区,有效提高了产品的击穿特性和雪崩耐量。但因为其close栅极结构的限制,部分栅宽W被占据,沟道密度较低,在小电流器件中表现为特征导通电阻较高。本发明涉及一种改进的新型功率MOSFET的制作方法,可以在不影响器件击穿电压的前提下,降低功率MOSFET的导通电阻,提高器件通流能力。该方法能提高VDMOS器件通流能力,属于VDMOS的设计及制造技术,具体包括以下步骤:
步骤1:首先选取N型合适电阻率的硅片N+ Sub作为制作VDMOS外延层的衬底片;
步骤2:在所选取的N+ Sub上面生长特定电阻率的外延层N-epi;
步骤3:在所生长的N-epi外延层上部生长一层场氧化层,并在器件有源区刻蚀场氧化层,在终端区注入P+并退火;
步骤4:在器件有源区生长一层屏蔽氧化层,之后注入杂质磷形成JFET区;
步骤5:在外延层上表面生长牺牲氧化层并腐蚀,之后热氧化生长栅氧化层;
步骤6:在栅氧化层之上淀积多晶硅并刻蚀形成多晶栅极;
步骤7:在栅氧化层和多晶硅的上表面注入Boron离子形成自对准的P阱;
步骤8:对PW进行热氧化推结;
步骤9:N+注入,形成自对准的源极N+区;
步骤10:N+退火处理;
步骤11:淀积LPSIN并进行源极P+高能注入;
步骤12:层间介质ILD淀积;
步骤13:接触孔刻蚀,Ti/TiN淀积;
步骤14:正面金属淀积并刻蚀;
步骤15:衬底减薄,背面注入,背面金属淀积,合金化,形成完整器件结构。
该制造方法采用LPSIN掩蔽的源极P+注入,制得器件EAS能力更高的源极N+结构,将closed结构改为open结构,并采用特殊源极N+区设计,在不影响击穿电压BVDSS和EAS的前提下,提高了功率MOSFET的通流能力。
本发明的内容不限于实施例所列举,本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换,均为本发明的权利要求所涵盖。
Claims (2)
1.功率MOSFET器件的制造方法,其特征在于:
所述方法包括以下步骤:
步骤1:选取N+ Sub作为制作VDMOS外延层的衬底片;
步骤2:在所选取的N+ Sub上面生长外延层N-epi;
步骤3:在所生长的N-epi外延层上部生长一层场氧化层,并在器件有源区刻蚀场氧化层,在终端区注入P+并退火;
步骤4:在器件有源区生长一层屏蔽氧化层,之后注入杂质磷形成JFET区;
步骤5:在外延层上表面生长牺牲氧化层并腐蚀,之后热氧化生长栅氧化层;
步骤6:在栅氧化层之上淀积多晶硅并刻蚀形成多晶栅极;
步骤7:在栅氧化层和多晶硅的上表面注入Boron离子形成自对准的P阱;
步骤8:对PW进行热氧化推结;
步骤9:N+注入,形成自对准的源极N+区;
步骤10:N+退火处理;
步骤11:淀积LPSIN并进行源极P+高能注入;
步骤12:层间介质ILD淀积;
步骤13:接触孔刻蚀,Ti/TiN淀积;
步骤14:正面金属淀积并刻蚀;
步骤15:衬底减薄,背面注入,背面金属淀积,合金化,形成完整器件结构。
2.如权利要求1所述的制造方法制得的功率MOSFET器件。
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CN113224135A (zh) * | 2021-05-21 | 2021-08-06 | 上海道之科技有限公司 | 一种高雪崩耐量的屏蔽栅mosfet器件及其制作方法 |
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CN113224135A (zh) * | 2021-05-21 | 2021-08-06 | 上海道之科技有限公司 | 一种高雪崩耐量的屏蔽栅mosfet器件及其制作方法 |
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