WO2015109929A1 - 一种超势垒整流器件及其制造方法 - Google Patents

一种超势垒整流器件及其制造方法 Download PDF

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WO2015109929A1
WO2015109929A1 PCT/CN2014/095918 CN2014095918W WO2015109929A1 WO 2015109929 A1 WO2015109929 A1 WO 2015109929A1 CN 2014095918 W CN2014095918 W CN 2014095918W WO 2015109929 A1 WO2015109929 A1 WO 2015109929A1
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well region
layer
conductivity type
epitaxial layer
rectifying device
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PCT/CN2014/095918
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English (en)
French (fr)
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秦旭光
唐红祥
张新
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无锡华润华晶微电子有限公司
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Publication of WO2015109929A1 publication Critical patent/WO2015109929A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular to the field of power semiconductor device technologies, and in particular, to a super barrier rectifying device and a method of fabricating the same.
  • a “super barrier” is created for a multi-sub-channel through a MOS (Metal Oxide Semiconductor) channel, and the barrier is lowered by the bulk effect of the MOS transistor.
  • the height reduces the forward voltage drop of the SBR diode, achieving a forward voltage drop close to the Schottky diode while ensuring a small leakage current.
  • FIG. 1 is a cross-sectional view showing the cell structure of a prior art super barrier rectifying device.
  • the prior art super-barrier rectifying device is based on a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device structure, and the gate and source are short-circuited.
  • the parasitic pn junction diode is formed in parallel with the MOS devices shorted by the gate source and alternately arranged. Since the gate oxide layer 105 of the MOS device is thin (usually at The surface concentration of the P-well 103 is low, and due to the bulk effect of the MOS transistor, its threshold voltage is low, usually smaller than the barrier voltage drop of the PN junction, so that the MOS device is multi-conductive when forward biased.
  • VDMOS Very Double-diffused Metal Oxide Semiconductor
  • the channel turns on before the parasitic PN junction, achieving a lower forward voltage drop than the PN junction diode.
  • the MOS device In the reverse bias, since the source is shorted to the gate, the MOS device is in an off state, and the parasitic PN junction is quickly depleted and subjected to a reverse bias voltage.
  • the existing ultra-barrier rectifier device needs to use a channel as short as possible, so the P-well depth is usually shallow.
  • a shallow P-well will result in a decrease in the avalanche breakdown resistance of the entire super-barrier rectifying device, and a short channel will also greatly increase the reverse leakage current.
  • embodiments of the present invention provide a super-barrier rectifying device and a method of fabricating the same that suppress reverse leakage current while reducing forward voltage drop.
  • an embodiment of the present invention provides a super barrier rectifying device, including:
  • An epitaxial layer of a first conductivity type on the substrate An epitaxial layer of a first conductivity type on the substrate;
  • the second well region is away from the gate oxide layer compared to the first well region.
  • the plurality of second well regions are sequentially spaced in a direction from the gate oxide layer toward the substrate.
  • an insulating dielectric layer between the polysilicon layer and the first metal layer is further included.
  • a source region of a first conductivity type embedded in the first well region is further included.
  • a second metal layer under the substrate is further included.
  • the shape of the cell structure of the super barrier rectifying device includes: a strip shape, a square shape or a hexagonal shape.
  • an embodiment of the present invention provides a method for fabricating a super barrier rectifying device, including:
  • the second well region is away from the gate oxide layer compared to the first well region.
  • the method further includes:
  • the first conductivity type impurity is implanted at least once, and a non-uniform distribution of the first conductivity type doping concentration is formed in the epitaxial layer.
  • the forming the first well region of the second conductivity type and the second well region of the second conductivity type and separated from the first well region in the epitaxial layer comprises:
  • a second conductivity type impurity is implanted at least twice, and a first well region of a second conductivity type and a second well region of a second conductivity type and separated from the first well region are formed in the epitaxial layer.
  • the plurality of second well regions are sequentially spaced in a direction from the gate oxide layer toward the substrate.
  • a first well region of a second conductivity type and a second well of a second conductivity type separated from the first well region are formed in the epitaxial layer Before the district, it also includes:
  • An insulating dielectric layer is formed on the polysilicon layer.
  • a first well region of a second conductivity type and a second well of a second conductivity type separated from the first well region are formed in the epitaxial layer Before the district, it also includes:
  • a source region of a first conductivity type is formed within the epitaxial layer.
  • the method for manufacturing the super barrier rectifying device further includes:
  • a second metal layer is formed under the substrate.
  • the shape of the cell structure of the super barrier rectifying device includes: a strip shape, a square shape or a hexagonal shape.
  • a shallow channel is used to realize a short channel, thereby ensuring an ultra-low forward voltage and a PN junction formed in the epitaxial layer by using a deep well region. It is quickly pinched off during reverse bias, and it is effective in suppressing leakage while maintaining anti-avalanche breakdown capability. drop.
  • FIG. 1 is a schematic cross-sectional view showing a cell structure of a prior art super barrier rectifying device
  • FIG. 2 is a schematic cross-sectional view showing a cell structure of a super barrier rectifying device according to a first embodiment of the present invention
  • FIG. 3 is a flow chart showing a method of manufacturing a super barrier rectifying device according to a second embodiment of the present invention.
  • 4A-4B are schematic diagrams showing doping concentration distributions of a first conductivity type and a second conductivity type in an epitaxial layer according to a second embodiment of the present invention
  • Fig. 5 is a flow chart showing a method of manufacturing a super barrier rectifying device according to a third embodiment of the present invention.
  • 201 a substrate; 202, an N- epitaxial layer; 203, a first P-well region; 204, an N+ source region; 205, a gate oxide layer; 206, a polysilicon layer; 207, a first metal layer; 208, a second P a well region; 209, a second metal layer.
  • Fig. 2 is a schematic cross-sectional view showing the cell structure of the super barrier rectifying device of the first embodiment of the present invention. As shown in FIG. 2, the super barrier rectifying device includes:
  • N- epitaxial layer 202 on the substrate 201 An N- epitaxial layer 202 on the substrate 201;
  • first P-well region 203 located in the N- epitaxial layer 202 and a second P-well region 208 separated from the first P-well region 203;
  • a polysilicon layer 206 on the gate oxide layer 205 wherein the gate oxide layer 205 and the polysilicon layer 206 together constitute a gate structure of the super barrier rectifying device;
  • a first metal layer 207 is disposed on the polysilicon layer 206 and the N- epitaxial layer 202, wherein the first metal layer 207 acts as an anode of the entire super barrier rectifying device.
  • an insulating dielectric layer may be included between the polysilicon layer 206 and the first metal layer 207.
  • the second P-well region 208 is away from the gate oxide layer 205 compared to the first P-well region 203, that is, the first P-well region 203 is located at the In a shallower position within the N- epitaxial layer 202, the second P-well region 208 is located below the first P-well region 203 and is located deeper within the N- epitaxial layer 202.
  • the super-barrier rectifying device further includes an N+ source region 204 embedded in the first P-well region 203.
  • a second metal layer 209 is further included under the substrate 201, wherein the second metal layer 209 and the substrate 201 together constitute a drain structure of the super barrier rectifying device, that is, as a whole super The cathode of the barrier rectifying device.
  • the working principle of the super-barrier rectifying device of the present embodiment is specifically described below.
  • the first metal layer 207 shorts the N+ source region 204 and the polysilicon layer 206 to form a gate-source short-circuit NMOS transistor.
  • the first P-well region 203 and the N- epitaxial layer 202 form a shallow parasitic PN junction diode, ie
  • the super-barrier rectifying device can be regarded as being formed by parallel and alternate arrangement of parasitic PN junction diodes and NMOS devices shorted to the gate source. And further comprising a deep parasitic PN junction diode formed by the N- epitaxial layer 202 and the second P-well region 208 separated from the first P-well region 203 in the super barrier rectifying device of the embodiment. .
  • the parasitic PN junction diode When the applied voltage is reverse biased, that is, when the gate voltage V G is equal to the source voltage V S and less than 0, the parasitic PN junction diode is in a reverse bias state, and the gate oxide layer of the NMOS transistor cannot be formed under the gate oxide layer. a conductive channel, the entire structure is in a reversed-off state, and the second P-well region 208 and the N- epitaxial layer 202 form a deeper parasitic PN junction diode that can be quickly pinched off during reverse bias, thereby Effectively suppress reverse leakage current while ensuring strong avalanche breakdown resistance.
  • the multi-sub-barrier voltage drop is mainly determined by the threshold voltage V T of the NMOS transistor, because the gate oxide layer of the MOS device is thin (usually The surface concentration of the first P-well region 203 is low, and due to the NMOS transistor body effect, the integration causes the threshold voltage V T to be low, typically less than the PN junction barrier voltage drop, thereby making the NMOS transistor
  • the multi-sub-conducting channel opens before the parasitic PN junction, achieving a lower forward voltage drop than the PN junction diode.
  • the shallower first P-well region 203 can be used only for short implementation.
  • the channel is such that an ultra-low forward voltage is achieved.
  • the second P-well region 208 may also be plural, and the plurality of second P-well regions 208 are from the gate oxide layer 205 toward the The substrates 201 are sequentially spaced apart in the direction.
  • each of the second P-well region 208 and the N- epitaxial layer 202 form a deeper or deeper parasitic PN junction diode. The deeper the position of the parasitic PN junction diode, the smaller the leakage current is. The performance of the ultra-barrier rectifying device is further improved.
  • the super-barrier rectifying device of the present embodiment is not limited to the case where the MOS structure of the device is equivalent to the N-channel MOS transistor.
  • the same embodiment is applicable.
  • an ultra-barrier rectifying device in which an N-channel is replaced with a P-channel is also applicable to the present embodiment.
  • the shape of the cell structure of the super barrier rectifying device is the same as that of the present embodiment, regardless of the shape of the strip, the square or the hexagon.
  • a separate well region structure is formed in the epitaxial layer, and a short channel of the MOS structure is realized by using a shallow well region, thereby ensuring forward conduction at an ultra-low voltage and utilizing a deeper
  • the PN junction formed in the epitaxial layer in the well region enables rapid pinch-off during reverse bias, thereby effectively suppressing leakage current while maintaining high avalanche breakdown resistance.
  • FIG. 3 is a flow chart showing a method of fabricating a super barrier rectifying device according to a second embodiment of the present invention, the method comprising:
  • Step 310 forming an epitaxial layer of a first conductivity type on the substrate.
  • an epitaxial layer is grown on the substrate.
  • a substrate having two opposing major faces is provided, and an epitaxial layer of a first conductivity type is formed on a first major face of the substrate.
  • a photoresist is formed and the first oxide layer is selectively masked and etched, and a ring implant window is formed on the epitaxial layer of the super barrier rectifying device.
  • a second oxide layer that is, a sacrificial oxide layer is formed on the first oxide layer, and a second conductivity type impurity is implanted on the epitaxial layer of the termination region of the super barrier rectifying device by using the ring implantation window, and passes through Pushing the well to form a pressure ring; optionally, utilizing the In the ring injection window, a second conductivity type impurity is implanted in a local region of the central unit cell region, and a deep junction is formed by pushing the well.
  • a photoresist is formed and the first oxide layer and the second oxide layer are selectively masked and etched, and the first oxide layer and the second oxide layer at the position where the original cell region is located are removed on the first main surface of the substrate .
  • the first conductivity type impurity is implanted at least once, and a non-uniform distribution of the first conductivity type doping concentration is formed in the epitaxial layer.
  • the doping concentration can be distributed according to a predetermined requirement by controlling the ion implantation energy, the implantation dose, and the priming time. The purpose of this process is to provide a basis for forming a first well region of the second conductivity type and a second well region of the second conductivity type and separated from the first well region in the epitaxial layer in step 340.
  • Step 320 forming a gate oxide layer on the epitaxial layer.
  • the gate oxide layer is formed on the N- epitaxial layer by gate oxidation.
  • Step 330 forming a polysilicon layer on the gate oxide layer.
  • a process of depositing polysilicon, photolithography polysilicon, and etching is performed on the gate oxide layer to form a polysilicon layer.
  • the gate oxide layer and the polysilicon layer together form the gate structure of the super barrier rectifying device.
  • an insulating dielectric layer may be formed on the polysilicon layer.
  • a photoresist is formed on the polysilicon layer and the insulating dielectric layer and the polysilicon layer are selectively masked and etched.
  • a source region of the first conductivity type is formed within the epitaxial layer. Specifically, after selectively masking and etching the insulating dielectric layer and the polysilicon layer, the remaining insulating dielectric layer and remaining The polysilicon layer serves as a masking layer, and the gate oxide layer and the epitaxial layer are etched to form a silicon trench on the epitaxial layer.
  • the method before forming the source region of the first conductivity type in the epitaxial layer, the method further includes: implanting a first conductivity type impurity on the epitaxial layer.
  • Step 340 forming a first well region of a second conductivity type and a second well region of a second conductivity type and separated from the first well region in the epitaxial layer. Specifically, after the silicon trench is formed, the second conductivity type impurity is implanted, and the separated first well region and second well region are formed by annealing.
  • the second well region is away from the gate oxide layer compared to the first well region.
  • the step 340 specifically includes:
  • a second conductivity type impurity is implanted at least once, and a first well region of a second conductivity type and a second well region of a second conductivity type and separated from the first well region are formed in the epitaxial layer.
  • This step is performed on the basis of injecting the first conductivity type impurity at least once, and forming a non-uniform distribution of the first conductivity type doping concentration in the epitaxial layer.
  • the second conductivity type impurity is implanted at least once, that is, the N- epitaxial layer is doped with P type ions.
  • the doping concentration may be distributed according to a predetermined requirement by controlling the ion implantation energy, the implantation dose, and the push-time when performing P-type doping.
  • the N-type doping concentration distribution of the N- epitaxial layer is to implant the first conductivity type impurity at least once, and form a non-uniform distribution of the first conductivity type doping concentration in the epitaxial layer.
  • the P-type doping concentration distribution of the N- epitaxial layer is set in step 340. After the superposition of the above two steps, the P-type doping concentration in the N- epitaxial layer is set.
  • a portion larger than the N-type doping concentration can form each P-well region, and the N-type doping concentration in the N- epitaxial layer is greater than that of the P-type doping
  • the portion of the impurity concentration is still an N-type region, and the respective P-well regions can be isolated, thus forming a shallower first P-well region and a deeper second P-well region, and The first P-well region and the second P-well region are separated by the N- epitaxial layer to form a separate P-well structure.
  • the first P-well region 203 is located at a shallower position in the N- epitaxial layer 202, and the second P-well region 208 is located below the first P-well region 203. The deeper position within the N- epitaxial layer 202.
  • 4A-4B are schematic diagrams showing the doping concentration distributions of the first conductivity type and the second conductivity type in the epitaxial layer of the present embodiment.
  • the x-axis represents the depth of the N- epitaxial layer
  • the y-axis represents the doping concentration
  • the solid line represents the doping concentration distribution of the first conductivity type, that is, the N-type impurity
  • the broken line represents the second conductivity type, that is, Doping concentration distribution of P-type impurities.
  • FIG. 4A is a schematic diagram showing the doping concentration distribution after the first conductivity type ion implantation and the first second conductivity type ion implantation in the N- epitaxial layer of the embodiment.
  • the concentration of the N-type ions may have a Gaussian distribution (shown by a solid line) in the epitaxial layer.
  • the second conductivity type ions are implanted once, and the second conductivity type ion concentration injected this time may have a Gaussian distribution (Fig. 4A, indicated by a broken line). As shown in FIG.
  • each P-well region can be formed in a portion where the P-type doping concentration is greater than the N-type doping concentration, and the portion of the N- epitaxial layer having an N-type doping concentration greater than the P-type doping concentration is still an N-type region. It is thus possible to isolate the individual P-well regions.
  • 4B is a doping concentration after performing a plurality of first conductivity type ion implantation (shown by a solid line) and a plurality of second conductivity type ion implantation (shown by a broken line) in the N- epitaxial layer of the embodiment.
  • Distribution diagram. The basic principle is the same as that of FIG. 4A, that is, different distributions of P-type doping concentration and N-type doping concentration are formed in the N- epitaxial layer by multiple doping, and then the P-type doping concentration is greater than the N-type doping.
  • the portion of the impurity concentration can form each P-well region, and the portion of the N- epitaxial layer having an N-type doping concentration greater than the P-type doping concentration
  • the individual P-well regions can be isolated by still being N-type regions.
  • the difference from 4A is that a plurality of separate well regions can be formed in the N- epitaxial layer by multiple doping ion implantation, and the separated well regions are from the gate oxide layer toward the The substrates are sequentially spaced apart in the direction.
  • Step 350 forming a first metal layer on the polysilicon layer and the epitaxial layer.
  • a first metal layer is formed on the polysilicon layer and the N- epitaxial layer, and the first metal layer serves as an anode of the super barrier rectifying device of the present embodiment.
  • the method further includes: forming a photoresist and selectively masking and etching the first metal layer to form a first metal line.
  • the method further includes: forming a passivation layer on the first metal connection line, and forming on the passivation layer A metal line window, wherein the passivation layer comprises a silicon dioxide layer deposited on the first metal line and a silicon nitride layer on the silicon dioxide layer.
  • the method further includes: forming a third metal layer on the passivation layer, that is, forming an anode metal layer.
  • a second metal layer is formed under the substrate, specifically, a second main surface of the substrate is thinned, and further, on a second main surface of the thinned substrate Forming a second metal layer, the manner of forming the second metal layer is not limited to evaporation and sputtering, and the second metal layer and the substrate together constitute a drain structure of the super barrier rectifying device, that is, forming a superpotential Rebar rectifier device cathode.
  • the plurality of second well regions are sequentially spaced in a direction from the gate oxide layer toward the substrate.
  • the shape of the cell structure of the super barrier rectifying device comprises: strip, square or hexagonal type.
  • the manufacturing method of the super barrier rectifying device of the present embodiment is not limited to the case where the MOS structure of the device is equivalent to the N-channel MOS transistor, and the other embodiments are the same for other types of super barrier rectifying devices.
  • an ultra-barrier rectifying device in which an N-channel is replaced with a P-channel is also applicable to the present embodiment.
  • the shape of the cell structure of the super barrier rectifying device is the same as that of the present embodiment, regardless of the shape of the strip, the square or the hexagon.
  • a separate well region structure can be formed in the epitaxial layer, and an ultra-low forward voltage can be realized by using a shallow well region, and at the same time,
  • the deep well region suppresses leakage current while maintaining high avalanche breakdown resistance.
  • FIG. 5 is a flow chart showing a method of fabricating a super barrier rectifying device according to a third embodiment of the present invention, the method comprising:
  • Step 510 forming an epitaxial layer of a first conductivity type on the substrate.
  • the first conductivity type impurity is implanted at least once, and a non-uniform distribution of the first conductivity type doping concentration is formed in the epitaxial layer.
  • Step 520 forming a gate oxide layer on the epitaxial layer.
  • Step 530 forming a polysilicon layer on the gate oxide layer.
  • Step 540 forming a first well region of a second conductivity type and a second well region of a second conductivity type and separated from the first well region in the epitaxial layer, wherein the second well region is compared
  • the first well region is away from the gate oxide layer.
  • the step 540 specifically includes:
  • a second conductivity type impurity is implanted at least twice, and a first well region of a second conductivity type and a second well region of a second conductivity type and separated from the first well region are formed in the epitaxial layer.
  • the second conductivity type impurity is implanted at least twice, that is, the N- epitaxial layer is doped with P type ions.
  • the doping position can be controlled by controlling the ion implantation energy and the implantation dose.
  • the first P-well region and the second P-well region are isolated by the N- epitaxial layer to form a separate P-well structure.
  • Step 550 forming a first metal layer on the polysilicon layer and the epitaxial layer.
  • a second metal layer is formed under the substrate, that is, a second metal layer is formed on the lower surface of the substrate by evaporation or sputtering, and the second metal layer and the substrate together constitute the super The drain structure of the barrier rectifying device.
  • the plurality of second well regions are sequentially spaced in a direction from the gate oxide layer toward the substrate.
  • a first well region of a second conductivity type and a second well of a second conductivity type separated from the first well region are formed in the epitaxial layer Before the district, it can also include:
  • An insulating dielectric layer is formed on the polysilicon layer.
  • a first well region of a second conductivity type and a second well of a second conductivity type separated from the first well region are formed in the epitaxial layer Before the district, it can also include:
  • a source region of a first conductivity type is formed within the epitaxial layer.
  • the shape of the cell structure of the super barrier rectifying device comprises: strip, square or hexagonal type.
  • the manufacturing method of the super barrier rectifying device of the present embodiment is not limited to the case where the MOS structure of the device is equivalent to the N-channel MOS transistor, and the other embodiments are the same for other types of super barrier rectifying devices.
  • an ultra-barrier rectifying device in which an N-channel is replaced with a P-channel is also applicable to the present embodiment.
  • the shape of the cell structure of the super barrier rectifying device is the same as that of the present embodiment, regardless of the shape of the strip, the square or the hexagon.
  • a separate well region structure can be formed in the epitaxial layer, and an ultra-low forward voltage can be realized by using a shallow well region while utilizing The deeper well region suppresses leakage current while maintaining high avalanche breakdown resistance.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供了一种超势垒整流器件及其制造方法，包括：衬底（201）；位于衬底（201）上的第一导电类型的外延层（202）；位于外延层（202）内的第二导电类型的第一阱区（203）以及第二导电类型的且与第一阱区（203）分离的第二阱区（208）；位于外延层（202）上的栅氧化层（205）；位于栅氧化层（205）上的多晶硅层（206）；位于多晶硅层（206）和外延层（202）上的第一金属层（207），其中第二阱区（208）相比于第一阱区（203）远离所述栅氧化层（205）。本发明通过在外延层中形成分离式的阱区结构，在降低正向导通压降的同时，能够有效抑制漏电流，并且保证合理的雪崩击穿能量。

Description

一种超势垒整流器件及其制造方法
相关申请的交叉引用
本专利申请要求于2014年1月24日提交的、申请号为201410035665.6、申请人为无锡华润华晶微电子有限公司、发明名称为“一种超势垒整流器件及其制造方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。
技术领域
本发明涉及半导体技术领域，具体涉及功率半导体器件技术领域，尤其涉及一种超势垒整流器件及其制造方法。
背景技术
在超势垒整流器件(SBR，Super Barrier Rectifier)中，通过MOS(Metal Oxide Semiconductor，金属氧化物半导体)沟道为多子创建一个“超势垒”，同时利用MOS晶体管的体效应降低势垒高度，减小SBR二极管的正向压降，获得接近肖特基二极管的正向压降，同时保证较小的漏电流。
图1示出了现有技术的超势垒整流器件的元胞结构的剖面示意图。如图1所述，现有技术的超势垒整流器件是在VDMOS(Vertical Double-diffused Metal Oxide Semiconductor，垂直双扩散金属氧化物半导体)器件结构的基础上进行栅极和源极短接，由寄生pn结二极管与栅源短接的MOS器件并联且交替排布所形成。由于该MOS器件的栅氧化层105厚度较薄(通常在
Figure PCTCN2014095918-appb-000001
)，P-阱103的表面浓度低，并且由于MOS晶体管的体效应，导致其阈值电压较低，通常小于PN结的势垒压降，从而使得在正向偏压时，MOS器件多子导电沟道先 于寄生PN结打开，获得了比PN结二极管低的正向压降。而在反向偏压时，由于源极与栅极短接，MOS器件处于截止状态，寄生PN结快速耗尽，承受反偏电压。
现有的超势垒整流器件为了实现超低正向导通压降，需要采用尽量短的沟道，因此其P阱深度通常都比较浅。但是，P阱较浅会导致整个超势垒整流器件抗雪崩击穿能力下降，同时短沟道也会大幅度提高反向漏电流。
发明内容
有鉴于此，本发明实施例提供一种超势垒整流器件及其制造方法，在降低正向压降的同时抑制反向漏电流。
一方面，本发明实施例提供了一种超势垒整流器件，包括：
衬底；
位于所述衬底上的第一导电类型的外延层；
位于所述外延层内的第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区；
位于所述外延层上的栅氧化层；
位于所述栅氧化上的多晶硅层；
位于所述多晶硅层和所述外延层上的第一金属层，其中
所述第二阱区相比于所述第一阱区远离所述栅氧化层。
进一步地，在所述第二阱区为多个的情况下，所述多个第二阱区在从所述栅氧化层朝着所述衬底的方向上依次隔开。
进一步地，还包括位于所述多晶硅层和所述第一金属层之间的绝缘介质层。
进一步地，还包括嵌入在所述第一阱区中的第一导电类型的源区。
进一步地，还包括位于所述衬底下方的第二金属层。
进一步地，所述超势垒整流器件的元胞结构的形状包括：条型、方型或六边型。
另一方面，本发明实施例还提供了一种超势垒整流器件的制造方法，包括：
提供衬底；
在所述衬底上形成第一导电类型的外延层；
在所述外延层上形成栅氧化层；
在所述栅氧化层上形成多晶硅层；
在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区；
在所述多晶硅层和所述外延层上形成第一金属层，其中
所述第二阱区相比于所述第一阱区远离所述栅氧化层。
进一步地，在所述衬底上形成第一导电类型的外延层之后，在所述外延层上形成栅氧化层之前，还包括：
至少一次注入第一导电类型杂质，在所述外延层内形成第一导电类型掺杂浓度的非均匀分布。
进一步地，所述在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区，包括：
至少一次注入第二导电类型杂质，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区；或者
至少两次注入第二导电类型杂质，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区。
进一步地，在所述第二阱区为多个的情况下，所述多个第二阱区在从所述栅氧化层朝着所述衬底的方向上依次隔开。
进一步地，在所述栅氧化层上形成多晶硅层之后，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区之前，还包括：
在所述多晶硅层上形成绝缘介质层。
进一步地，在所述栅氧化层上形成多晶硅层之后，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区之前，还包括：
在所述外延层内形成第一导电类型的源区。
进一步地，所述的超势垒整流器件的制造方法还包括：
在所述衬底下方形成第二金属层。
进一步地，所述超势垒整流器件的元胞结构的形状包括：条型、方型或六边型。
本发明实施例通过形成分离式阱区结构，使用较浅的阱区实现短沟道，确保实现超低的正向导通电压，同时利用较深的阱区在外延层内形成的PN结，使其在反向偏置时迅速夹断，在有效抑制漏电的同时，保持抗雪崩击穿能力不下 降。
附图说明
图1是现有技术的超势垒整流器件的元胞结构的剖面示意图；
图2是本发明第一实施例的超势垒整流器件的元胞结构的剖面示意图；
图3是本发明第二实施例的超势垒整流器件的制造方法的流程图；
[根据细则91更正 15.02.2015]　
图4A-4B是本发明第二实施例的外延层中的第一导电类型和第二导电类型掺杂浓度分布示意图；
图5是本发明第三实施例的超势垒整流器件的制造方法的流程图。
图中的附图标记所分别指代的技术特征为：
101、衬底；102、N-外延层；103、P-阱区；104、N+源区；105、栅氧化层；106、多晶硅层；107、第一金属层；108、第二金属层；
201、衬底；202、N-外延层；203、第一P-阱区；204、N+源区；205、栅氧化层；206、多晶硅层；207、第一金属层；208、第二P-阱区；209、第二金属层。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非限制本发明。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部内容。
图2是本发明第一实施例的超势垒整流器件的元胞结构的剖面示意图。如图2所示，所述超势垒整流器件包括：
衬底201；
位于衬底201上的N-外延层202；
位于所述N-外延层202内的第一P-阱区203以及与所述第一P-阱区203分离的第二P-阱区208；
位于所述N-外延层202上的栅氧化层205；
位于所述栅氧化层205上的多晶硅层206，其中，所述栅氧化层205和多晶硅层206共同组成所述超势垒整流器件的栅极结构；
位于所述多晶硅层206和N-外延层202上的第一金属层207，其中所述第一金属层207作为整个超势垒整流器件的阳极。可选地，在所述多晶硅层206和所述第一金属层207之间可以包括绝缘介质层。
需要特别说明的是，所述第二P-阱区208相比于所述第一P-阱区203远离所述栅氧化层205，也就是说，所述第一P-阱区203位于所述N-外延层202内较浅的位置，所述第二P-阱区208在所述第一P-阱区203的下方，位于所述N-外延层202内较深的位置。
可选地，所述超势垒整流器件还包括嵌入在所述第一P-阱区203的N+源区204。
优选地，在所述衬底201下方还包括第二金属层209，其中，所述第二金属层209和衬底201共同组成了所述超势垒整流器件的漏极结构，即作为整个超势垒整流器件的阴极。
下面具体说明本实施例的超势垒整流器件的工作原理，所述第一金属层207将所述N+源区204和所述多晶硅层206短接，形成了栅源短接NMOS晶体管，并且所述第一P-阱区203和所述N-外延层202形成较浅的寄生PN结二极管，即 所述超势垒整流器件可以看做是由寄生PN结二极管与栅源短接的NMOS器件并联且交替排布所形成。并且在本实施例的超势垒整流器件中还包括所述N-外延层202和与所述第一P-阱区203分离的第二P-阱区208形成的较深的寄生PN结二极管。
在外加电压反向偏置时，即栅极电压VG等于源极电压VS且小于0时，所述寄生PN结二极管处于反向偏置状态，所述NMOS晶体管的栅氧化层下不能形成导电沟道，整个结构处于反向截止状态，并且所述第二P-阱区208与所述N-外延层202形成较深的寄生PN结二极管可以在反向偏置时迅速夹断，从而有效抑制反向漏电流，同时保证较强的抗雪崩击穿能力。
在外加电压正向偏置时，源极电压VS大于所述NMOS晶体管开启电压时，所述栅源短接的NMOS晶体管的栅氧化层下面的第一P阱区域被强反型，形成了N型多子导电沟道，该多子势垒压降主要由NMOS晶体管的阈值电压VT决定，因该MOS器件的栅氧化层厚度较薄(通常在
Figure PCTCN2014095918-appb-000002
)，所述第一P-阱区203的表面浓度低，同时由于NMOS晶体管体效应，综合导致所述阈值电压VT较低，通常小于PN结势垒压降，从而使得所述NMOS晶体管的多子导电沟道先于寄生PN结打开，获得了比PN结二极管低的正向压降。由于所述较深P-阱区形成的寄生PN结二极管可以有效抑制反向漏电流，同时保持抗雪崩击穿能力，所以较浅的所述第一P-阱区203可以只用于实现短沟道，从而实现超低正向导通电压。
在本实施例的一个优选实施方式中，所述第二P-阱区208还可以为多个，并且所述多个第二P-阱区208在从所述栅氧化层205朝着所述衬底201的方向上依次隔开。这样，每个所述第二P-阱区208与所述N-外延层202形成较深或更深的寄生PN结二极管，寄生PN结二极管的位置越深反向漏电流就越小，从 而进一步改善了超势垒整流器件的性能。
需要特别说明的是，本实施例的超势垒整流器件不限于器件的MOS结构等效于N沟道的MOS晶体管的情形，对于其他类型的超势垒整流器件，本实施例同样适用，换句话说，将N沟道换成P沟道的超势垒整流器件同样适用于本实施例。并且无论超势垒整流器件的元胞结构的形状是条型、方型或者六边型，同样适用于本实施例。
本发明第一实施例通过在外延层中形成分离式的阱区结构，利用较浅的阱区实现MOS结构的短沟道，确保在超低的电压下可以正向导通，同时利用较深的阱区在外延层内形成的PN结，使其在反向偏置时能够迅速夹断，从而有效抑制漏电流，同时保持较高的抗雪崩击穿能力。
图3是根据本发明第二实施例的超势垒整流器件的制造方法的流程图，所示方法包括：
步骤310、在衬底上形成第一导电类型的外延层。
在本实施例中，在所述衬底上生长外延层。
具体地，提供具有两个相对主面的衬底，在所述衬底的第一主面上形成第一导电类型的外延层。
进一步地，制作光刻胶并选择性地掩蔽和刻蚀所述第一氧化层，并在超势垒整流器件的外延层上形成环注入窗口。进一步的，在所述第一氧化层上形成第二氧化层即牺牲氧化层，利用所述环注入窗口，在超势垒整流器件的终端区的外延层上注入第二导电类型杂质，并通过推阱形成耐压环；可选地，利用所 述环注入窗口，在中心单胞区局部区域注入第二导电类型杂质，通过推阱形成深结。
进一步地，制作光刻胶并选择性地掩蔽和刻蚀第一氧化层和第二氧化层，在衬底的第一主面上去除原胞区所在位置的第一氧化层和第二氧化层。
进一步地，至少一次注入第一导电类型杂质，在所述外延层内形成第一导电类型掺杂浓度的非均匀分布。具体地，可以通过控制离子注入能量、注入剂量和推结时间可以使得掺杂浓度按照预定要求进行分布。本过程的目的在于为步骤340在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区做基础。
步骤320、在所述外延层上形成栅氧化层。
具体地，在所述N-外延层上，经过栅氧化，形成所述栅氧化层。
步骤330、在所述栅氧化层上形成多晶硅层。
具体地，在所述栅氧化层上进行淀积多晶硅、光刻多晶硅及刻蚀的工艺流程，形成多晶硅层。这样，所述栅氧化层和多晶硅层共同形成了所述超势垒整流器件的栅极结构。
可选地，在所述栅氧化层上形成多晶硅层之后，可以在所述多晶硅层上形成绝缘介质层。
进一步地，在所述多晶硅层上制作光刻胶并选择性地掩蔽和刻蚀所述绝缘介质层和所述多晶硅层。
可选地，在所述外延层内形成第一导电类型的源区。具体地，选择性地掩蔽和刻蚀所述绝缘介质层和所述多晶硅层后，利用剩余的绝缘介质层和剩余的 多晶硅层作为掩蔽层，刻蚀所述栅氧化层及所述外延层，以在所述外延层上形成硅槽。
优选地，所述在所述外延层内形成第一导电类型的源区之前，还可以包括：在所述外延层上注入第一导电类型杂质。
步骤340、在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区。具体地，形成硅槽后，注入第二导电类型杂质，并通过退火形成分离的第一阱区和第二阱区。
其中，所述第二阱区相比于所述第一阱区远离所述栅氧化层。
在本实施例中，所述步骤340具体包括：
至少一次注入第二导电类型杂质，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区。
本步骤是在至少一次注入第一导电类型杂质，在所述外延层内形成第一导电类型掺杂浓度的非均匀分布的基础上进行的。在本实施例中，在所述N-外延层内，至少一次注入第二导电类型杂质，即对所述N-外延层进行P型离子掺杂。可选地，在进行P型掺杂的时候，通过控制离子注入能量、注入剂量和推结时间可以使得掺杂浓度按照预定要求进行分布。
这样，在本实施例中，所述N-外延层的N型掺杂浓度分布是在至少一次注入第一导电类型杂质，在所述外延层内形成第一导电类型掺杂浓度的非均匀分布的步骤中设置好的，所述N-外延层的P型掺杂浓度分布是在步骤340中设置好的，经过上述两个步骤的叠加，在所述N-外延层中P型掺杂浓度大于N型掺杂浓度的部分就可以形成各个P-阱区，而N-外延层中N型掺杂浓度大于P型掺 杂浓度的部分仍为N型区，就可以将所述各个P-阱区域隔离开来，这样就形成了较浅的第一P-阱区和较深的第二P-阱区，并且所述第一P-阱区和第二P-阱区被所述N-外延层隔离开来，形成了分离式的P-阱结构。其中，所述第一P-阱区203位于所述N-外延层202内较浅的位置，所述第二P-阱区208在所述第一P-阱区203的下方，位于所述N-外延层202内较深的位置。
图4A-4B是本实施例的外延层中的第一导电类型和第二导电类型掺杂浓度分布示意图。图4A-4B中x轴代表所述N-外延层的深度，y轴代表掺杂浓度，实线代表第一导电类型也就是N型杂质的掺杂浓度分布，虚线代表第二导电类型也就是P型杂质的掺杂浓度分布。
图4A是在本实施例的所述N-外延层中，只进行一次第一导电类型离子注入和一次第二导电类型离子注入后的掺杂浓度分布示意图。在图4A中，进行一次第一导电类型离子注入后，N型离子的浓度可以在所述外延层内呈高斯分布(实线所示)。然后在注入一次第二导电类型离子，这次注入的第二导电类型离子浓度可以呈高斯分布(图4A，虚线所示)。如图4A所示，经过两次不同类型的离子注入，在所述N-外延层中有些区域是P型掺杂浓度高，而另一些区域N型掺杂浓度高。于是，在P型掺杂浓度大于N型掺杂浓度的部分就可以形成各个P-阱区，而N-外延层中N型掺杂浓度大于P型掺杂浓度的部分仍为N型区，就可以将所述各个P-阱区域隔离开来。
图4B是在本实施例的所述N-外延层中，进行多次第一导电类型离子注入(实线所示)和多次第二导电类型离子注入(虚线所示)后的掺杂浓度分布示意图。其具基本原理与图4A相同，就是通过多次掺杂在所述N-外延层中形成P型掺杂浓度和N型掺杂浓度的不同分布，然后在P型掺杂浓度大于N型掺杂浓度的部分就可以形成各个P-阱区，而N-外延层中N型掺杂浓度大于P型掺杂浓度的部 分仍为N型区，就可以将所述各个P-阱区域隔离开来。与4A不同之处就在于，通过多次掺杂离子注入，可以在所述N-外延层内形成多个分离的阱区，并且所述分离的阱区从所述栅氧化层朝着所述衬底的方向上依次隔开。
步骤350、在所述多晶硅层和所述外延层上形成第一金属层。
具体地，在所述多晶硅层和所述N-外延层上淀积形成第一金属层，所述第一金属层作为本实施例的超势垒整流器件的阳极。
优选地，在形成所述第一金属层之后，还可以包括：制作光刻胶并选择性掩蔽和刻蚀所述第一金属层，以形成第一金属连线。
优选地，所述在所述多晶硅层和所述外延层上形成第一金属层之后，还可以包括：在所述第一金属连线上形成钝化层，并在所述钝化层上形成金属线窗口，其中，所述钝化层包括淀积于所述第一金属连线上的二氧化硅层及位于所述二氧化硅层上的氮化硅层。
优选地，在所述第一金属连线上形成钝化层之后，还可以包括：在所述钝化层上形成第三金属层，即形成阳极金属层。
优选地，在所述衬底下方形成第二金属层，具体的，对所述衬底的第二主面进行减薄处理，进一步地，在减薄处理后的衬底的第二主面上形成第二金属层，形成所述第二金属层的方式不限于蒸发和溅射，所述第二金属层和衬底共同组成了所述超势垒整流器件的漏极结构，即形成超势垒整流器件阴极。
优选地，在所述第二阱区为多个的情况下，所述多个第二阱区在从所述栅氧化层朝着所述衬底的方向上依次隔开。
优选地，所述超势垒整流器件的元胞结构的形状包括：条型、方型或六边 型。
需要特别说明的是，本实施例的超势垒整流器件的制造方法不限于器件的MOS结构等效于N沟道的MOS晶体管的情形，对于其他类型的超势垒整流器件，本实施例同样适用，换句话说，将N沟道换成P沟道的超势垒整流器件同样适用于本实施例。并且无论超势垒整流器件的元胞结构的形状是条型、方型或者六边型，同样适用于本实施例。
本发明第二实施例通过控制外延层的离子掺杂浓度的位置分布，可以在外延层中形成分离式的阱区结构，利用较浅的阱区实现超低的正向导通电压，同时利用较深的阱区抑制漏电流，同时保持较高抗雪崩击穿能力。
图5是根据本发明第三实施例的超势垒整流器件的制造方法的流程图，所示方法包括：
步骤510、在衬底上形成第一导电类型的外延层。
进一步地，至少一次注入第一导电类型杂质，在所述外延层内形成第一导电类型掺杂浓度的非均匀分布。
步骤520、在所述外延层上形成栅氧化层。
步骤530、在所述栅氧化层上形成多晶硅层。
步骤540、在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区，其中，所述第二阱区相比于所述第一阱区远离所述栅氧化层。
在本实施例中，所述步骤540具体包括：
至少两次注入第二导电类型杂质，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区。
具体地说，在所述N-外延层内，至少两次注入第二导电类型杂质，即对所述N-外延层进行P型离子掺杂。在进行P型掺杂的时候，可以通过控制离子注入能量、注入剂量来控制掺杂的位置。所述第一P-阱区和第二P-阱区被所述N-外延层隔离开来，形成了分离式的P-阱结构。
步骤550、在所述多晶硅层和所述外延层上形成第一金属层。
优选地，在所述衬底下方形成第二金属层，即在所述衬底的下表面通过蒸发或溅射形成第二金属层，所述第二金属层和衬底共同组成了所述超势垒整流器件的漏极结构。
优选地，在所述第二阱区为多个的情况下，所述多个第二阱区在从所述栅氧化层朝着所述衬底的方向上依次隔开。
优选地，在所述栅氧化层上形成多晶硅层之后，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区之前，还可以包括：
在所述多晶硅层上形成绝缘介质层。
优选地，在所述栅氧化层上形成多晶硅层之后，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区之前，还可以包括：
在所述外延层内形成第一导电类型的源区。
优选地，所述超势垒整流器件的元胞结构的形状包括：条型、方型或六边 型。
需要特别说明的是，本实施例的超势垒整流器件的制造方法不限于器件的MOS结构等效于N沟道的MOS晶体管的情形，对于其他类型的超势垒整流器件，本实施例同样适用，换句话说，将N沟道换成P沟道的超势垒整流器件同样适用于本实施例。并且无论超势垒整流器件的元胞结构的形状是条型、方型或者六边型，同样适用于本实施例。
本发明第三实施例通过控制外延层中第二导电类型离子注入的位置，可以在外延层中形成分离式的阱区结构，利用较浅的阱区实现超低的正向导通电压，同时利用较深的阱区抑制漏电流，同时保持较高抗雪崩击穿能力。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的保护范围由所附的权利要求范围决定。

Claims (14)

  1. 一种超势垒整流器件，其特征在于，包括：
    衬底；
    位于所述衬底上的第一导电类型的外延层；
    位于所述外延层内的第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区；
    位于所述外延层上的栅氧化层；
    位于所述栅氧化上的多晶硅层；
    位于所述多晶硅层和所述外延层上的第一金属层，其中
    所述第二阱区相比于所述第一阱区远离所述栅氧化层。
  2. 根据权利要求1所述的超势垒整流器件，其特征在于，在所述第二阱区为多个的情况下，所述多个第二阱区在从所述栅氧化层朝着所述衬底的方向上依次隔开。
  3. 根据权利要求1所述的超势垒整流器件，其特征在于，还包括位于所述多晶硅层和所述第一金属层之间的绝缘介质层。
  4. 根据权利要求1所述的超势垒整流器件，其特征在于，还包括嵌入在所述第一阱区中的第一导电类型的源区。
  5. 根据权利要求1或4所述的超势垒整流器件，其特征在于，还包括位于所述衬底下方的第二金属层。
  6. 根据权利要求1所述的超势垒整流器件，其特征在于，所述超势垒整流器件的元胞结构的形状包括：条型、方型或六边型。
  7. 一种超势垒整流器件的制造方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成第一导电类型的外延层；
    在所述外延层上形成栅氧化层；
    在所述栅氧化层上形成多晶硅层；
    在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区；
    在所述多晶硅层和所述外延层上形成第一金属层，其中
    所述第二阱区相比于所述第一阱区远离所述栅氧化层。
  8. 根据权利要求7所述的超势垒整流器件的制造方法，其特征在于，在所述衬底上形成第一导电类型的外延层之后，在所述外延层上形成栅氧化层之前，还包括：
    至少一次注入第一导电类型杂质，在所述外延层内形成第一导电类型掺杂浓度的非均匀分布。
  9. 根据权利要求7所述的超势垒整流器件的制造方法，其特征在于，所述在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区，包括：
    至少一次注入第二导电类型杂质，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区；或者
    至少两次注入第二导电类型杂质，在所述外延层内形成第二导电类型的第 一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区。
  10. 根据权利要求7-9任一项所述的超势垒整流器件的制造方法，其特征在于，在所述第二阱区为多个的情况下，所述多个第二阱区在从所述栅氧化层朝着所述衬底的方向上依次隔开。
  11. 根据权利要求7-9任一项所述的超势垒整流器件的制造方法，其特征在于，在所述栅氧化层上形成多晶硅层之后，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区之前，还包括：
    在所述多晶硅层上形成绝缘介质层。
  12. 根据权利要求7-9任一项所述的超势垒整流器件的制造方法，其特征在于，在所述栅氧化层上形成多晶硅层之后，在所述外延层内形成第二导电类型的第一阱区以及第二导电类型的且与所述第一阱区分离的第二阱区之前，还包括：
    在所述外延层内形成第一导电类型的源区。
  13. 根据权利要求7-9任一项所述的超势垒整流器件的制造方法，其特征在于，还包括：
    在所述衬底下方形成第二金属层。
  14. 根据权利要求7-9任一项所述的超势垒整流器件的制造方法，其特征在于，所述超势垒整流器件的元胞结构的形状包括：条型、方型或六边型。
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CN107204336A (zh) * 2016-03-16 2017-09-26 重庆中科渝芯电子有限公司 一种高效整流器及其制造方法
CN107204336B (zh) * 2016-03-16 2023-10-20 重庆中科渝芯电子有限公司 一种高效整流器及其制造方法
CN107546277A (zh) * 2016-06-24 2018-01-05 北大方正集团有限公司 超势垒二极管的制备方法和超势垒二极管
CN107946351A (zh) * 2017-09-20 2018-04-20 重庆中科渝芯电子有限公司 一种肖特基接触超级势垒整流器及其制作方法
CN107946351B (zh) * 2017-09-20 2023-09-12 重庆中科渝芯电子有限公司 一种肖特基接触超级势垒整流器及其制作方法
CN111463257A (zh) * 2019-01-22 2020-07-28 上海新微技术研发中心有限公司 Mos栅晶体管及其构建方法
CN111463257B (zh) * 2019-01-22 2023-09-08 上海睿驱微电子科技有限公司 Mos栅晶体管及其构建方法
CN113257917A (zh) * 2021-03-29 2021-08-13 重庆中科渝芯电子有限公司 一种集成整流器的平面mosfet及其制造方法
CN113257917B (zh) * 2021-03-29 2023-04-14 重庆中科渝芯电子有限公司 一种集成整流器的平面mosfet及其制造方法
CN117059673A (zh) * 2023-10-11 2023-11-14 珠海格力电子元器件有限公司 半导体结构、半导体结构的制作方法以及半导体器件
CN117059673B (zh) * 2023-10-11 2024-02-27 珠海格力电子元器件有限公司 半导体结构、半导体结构的制作方法以及半导体器件

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