CN104008968A - 多孔金属涂敷 - Google Patents
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Abstract
本发明涉及多孔金属涂敷。各种方法、装置和设备涉及被三维地涂敷的衬底上的多孔金属层。在一个实施例中,在衬底上沉积多孔金属层。能够用涂敷材料来三维地涂敷该多孔金属层。
Description
技术领域
本申请涉及多孔金属层的涂敷。
背景技术
在半导体器件的制造过程中,在类似于半导体晶片的衬底上沉积金属层。然后将这些金属层结构化以形成例如互连、结合焊盘、热沉等。常规沉积金属层(例如铜层)可例如对衬底造成应力,或者例如在衬底上施加力,例如由于热膨胀,这在某些情况下可能是不期望的。当在除半导体器件制造过程之外的其他过程中在其他种类的衬底上沉积金属层时,可能出现类似问题。
近年来,已经调查了多孔金属层的使用。多孔金属层可例如由基于等离子体的沉积方法或其他方法来沉积,并且其可例如根据金属层沉积期间的条件而展示出变化的孔隙度。在这方面,孔隙度指的是被空隙(“孔隙”)所占据的金属层百分比,高孔隙度层与具有较低孔隙度的层相比具有被此类空隙所占据的其体积的较高百分比。此类多孔金属层在某些情况下可具有良好的热和/或机械性质,例如在由于热膨胀而引发的应力或施加的力的方面。然而,对此类多孔金属层在例如基于硅的器件的制造过程中的集成构成了要解决的障碍。例如,多孔金属层在某些情况下可能具有与常规金属层相比不太良好的粘合性质,或者可能具有降低的硬度。
附图说明
图1示意性地示出了根据实施例的装置;
图2示出了图示出根据实施例的方法的流程图;
图3—6示出了根据某些实施例的器件的横截面电子显微图像;以及
图7示出了根据实施例的器件的示意性横截面图。
具体实施方式
下面,将参考附图来详细地描述实施例。应注意的是,这些实施例仅用于说明性目的,并且不应将其理解为以任何方式限制本申请的范围。例如,可将来自不同实施例的特征相互组合,除非另外具体地说明。此外,虽然将实施例描述为包括多个特征或元素,但不应将这理解为指示所有那些特征或元素都是实现实施例所必需的。例如,其他实施例可包括更少的特征或元素,或者可用其他特征或其他元素来替换所描述的实施例的特征或元素,例如用执行本质上与其替换的特征或元素相同的功能的其他特征或其他元素。
各种实施例涉及在衬底上,例如半导体晶片或其他衬底上沉积多孔金属层。在实施例中,然后用涂敷材料以三维方式来涂敷多孔金属层。该涂敷材料可包括不同于多孔金属层的材料,但是还可包括相同的材料,例如包括对应的无孔金属层。应将“涂敷材料”理解为可使用一个或多个涂敷材料,其可包括于一个或多个涂层中。
在这方面,三维涂敷意味着多孔金属层内的孔隙或空隙的表面的至少一部分被涂敷,例如孔隙表面的至少20%、孔隙表面的至少50%或孔隙表面的至少80%,而不仅仅是多孔金属层的外表面。稍后将更详细地解释用于此类涂敷的详细示例。
现在转到附图,在图1中示出了根据实施例的处理装置。图1的装置包括多个处理站或设备,其中连续地处理衬底,例如半导体晶片或其他衬底。应注意的是,所描绘的每个站在某些情况下可具有若干个子站以在站中的一个内连续地执行多个过程步骤。此外,应注意的是,图1的装置可以是更大的处理装置的一部分,即可存在附加的常规站,其在衬底进入图1的装置之前处理衬底和/或其在衬底离开图1的装置之后处理衬底。特别地,可使用图1的装置来处理已结构化的半导体晶片,例如其中已通过类似于掺杂(例如,经由离子注入)、外延层生长、层的结构化等的过程来形成器件的晶片。然而,图1的装置可同样被用来处理先前尚未被处理的半导体晶片或其他衬底或者除半导体晶片之外的已处理衬底。用于除半导体晶片之外的另一衬底类型的示例包括例如玻璃衬底和/或用于制造太阳能设备的衬底。并且,如本文所使用的术语“装置”将不被理解为意味着装置的部件之间的任何特定空间关系。例如,图1中所示的不同站可位于房间的不同部分中,或者甚至在不同的房间中,其中提供了用以将衬底从一个站传递至下一个的对应机构。同样地,站的不同子站不需要相互接近地定位。并且,在所示的站之间可采用附加站或设备。
在图1中,在多孔金属沉积站10中,在衬底上沉积多孔金属层,例如类似于硅晶片的半导体晶片或任何其他种类的衬底。衬底可以是未处理或先前已处理的。例如,可在衬底上形成半导体结构。并且,在某些实施例中,在沉积多孔金属层之前,可向衬底上沉积由例如与多孔金属相同的金属制成的种子层。并且,在某些情况下,可在沉积多孔金属层之前沉积蚀刻停止层。在其他实施例中,可向其中先前尚未沉积特定层的衬底上沉积多孔金属层。
在多孔金属沉积站10中沉积的多孔金属层可例如由铜或包括例如至少50%铜、至少80%铜或至少90%铜的铜合金制成。另外或替换地,多孔金属层可包括任何其他适当的金属,例如银。在某些实施例中,多孔金属沉积站10是基于等离子体的多孔沉积站。在这种情况下,可使用其中产生等离子体射流和/或活化载气和/或颗粒流的等离子体沉积,例如使用与类似于等离子体/火焰喷涂的过程相比较低的温度,并且其中活化颗粒的速度与类似于等离子体喷涂或冷气体喷涂相比是较低的。可使用例如载气来将要沉积的颗粒,特别地类似于铜颗粒的金属颗粒以粉末形式供应给等离子体射流。
为了产生等离子体射流,例如可使用两个电极之间的放电。为实现这点,例如可向通过电介质材料分离的电极供应电压。例如,该电介质材料可以是隔离管,其中在管道内提供一个电极并在管道外提供另一电极。
在操作中,在此类装置中,可导致辉光放电。通过供应流过可采取管形式的设备的处理气体,产生可与载气混合的等离子体射流。如上所述的载气可包括被用于涂敷衬底表面的颗粒,即要沉积在表面上的颗粒,在这种情况下为金属颗粒。在各种实施例中,可在产生等离子体射流的那部分设备外面的反应区中执行混合。在该反应区中,可将等离子体的能量传递至载气和/或包括在载气中的颗粒。例如,可通过载气与反应区中的等离子体射流的混合来活化包括在载气中的颗粒,使得例如可产生活化颗粒的流或射流。在某些实施例中,可提供多个反应区。
由于这是用于沉积多孔金属的常规技术,所以在这里将不更详细地对其进行描述。也可使用用于沉积多孔金属层的其他技术。
沉积金属层的厚度可例如在10 μm和1000 μm之间,例如在50 μm和600 μm之间。
此类多孔金属层与例如通过物理汽相沉积(PVD)或电化学沉积(ECD)而沉积的金属层相比在某些情况下可能具有涉及应力的良好性质。
在已在多孔金属沉积站10中沉积多孔金属之后,图1的实施例中的衬底被传递至结构化站11,在那里将多孔金属层结构化。在其他实施例中,可省略结构化站11,或者可在稍后将描述的涂敷站12的下游提供结构化站11。在结构化站11中,将多孔金属层结构化。在某些实施例中,例如,可在多孔金属层上提供掩模,并且可随后例如通过湿法化学蚀刻来蚀刻多孔金属层。在其他实施例中,可另外或替换地由结构化站11采用其他结构化技术,例如化学机械抛光(CMP)、镶嵌技术和/或剥离技术。
在已将多孔金属层结构化之后,将衬底传递至涂敷站12。
在涂敷站12中,采用多孔金属层的三维涂敷。在这种情况下,三维涂敷意指不仅多孔金属层的外表面被涂敷,而且多孔金属层的孔隙内的表面被至少部分地涂敷,例如表面的至少20%、表面的至少50%或更多。还可通过用涂敷材料填充孔隙来实现孔隙表面的此类涂敷。
可使用各种技术来执行三维涂敷。例如,能够从气相,例如通过原子层沉积(ALD)、化学汽相沉积(CVD)或物理汽相沉积(PVD),从液相,例如通过电化学沉积(ECD)或无电沉积,和/或从固相,例如通过烧结,来沉积对应的涂层。然而,这些技术仅仅用作示例,并且也可使用其他技术。并且,如先前已经提到的,可在三维涂敷之前,例如由结构化站11将多孔金属层结构化,或者该多孔金属层可以是非结构化的。还应注意的是,还可使用一个以上的涂层。
可将各种材料用于涂敷。例如,在某些实施例中可使用无电沉积(eless沉积)来沉积镍磷(NiP)或镍钼磷(NiMoP)。在某些实施例中,可将一个或多个另外的层沉积到NiP上,例如钯(Pd)层,其在某些实施例中后面可以是金(Au)层。此类层的厚度可约为几微米或以下,但是不限于此。例如,可使用约3 μm的NiP层,后面是约0.3 μm的Pd层。然而,这些数值仅仅是以示例的方式给出的,并且也可使用其他层厚度。在其他实施例中,例如,可使用银锡合金(AgSn)。在另外的其他实施例中,可使用与多孔金属相同的金属。例如,可通过电流沉积来在多孔铜层上沉积铜涂层。在另外的其他实施例中,可使用有机膜作为涂敷。
根据涂层的厚度和材料,可影响或调整多孔金属的电和/或机械性质,例如将其调谐成具有期望的性质。
在离开涂敷站12之后,可进一步处理衬底。例如,可沉积另外的层,可执行结合,可在其中省略了结构化站11的情况下将多孔金属层结构化,等等。
在图2中,示出了图示出根据实施例的方法的流程图。虽然图2的方法被图示为一系列动作或事件,但应注意的是不应将此类的动作或事件的所示顺序理解为限制性的,并且还可按照不同的顺序来执行动作或事件。并且,可省略所示的某些动作或事件,和/或可提供附加动作或事件。
在图2中的20处,在衬底上沉积多孔金属层。该衬底可以例如是类似于硅晶片、玻璃衬底或任何其他适当衬底的半导体衬底。多孔金属层可例如由铜、包括铜的合金或任何适当金属(例如银)制成。在某些实施例中,可在提供于衬底上的种子层和/或蚀刻停止层上沉积多孔金属层。在某些实施例中,可处理衬底。在其他实施例中,不在衬底上提供附加层。
可例如使用如上所述的基于等离子体的技术或任何其他适当技术来沉积多孔金属层。可将多孔金属层沉积至10 μm和1000 μm之间,例如在50 μm和600 μm之间的厚度,并且可具有在5%和90%之间,例如在20%和60%之间的孔隙度。然而,一般地,根据应用,可通过相应地调整处理条件来选择任何期望的孔隙度和厚度。
在21处,可选地例如通过湿法化学蚀刻、剥离技术、CMP技术和/或镶嵌技术将多孔金属层结构化。在其他实施例中,可省略或在该过程中稍后执行此结构化,例如在下面参考22所述的动作之后。
在22处,执行多孔金属层的三维(3D)涂敷。如上所述的三维涂敷意味着多孔金属层的孔隙内的表面的至少一部分(例如至少20%)被涂敷。可将各种技术用于此三维涂敷,例如ALD、CVD、PVD、ECD、无电沉积、烧结或用于从汽相、液相和/或固相沉积涂层的其他技术。可使用各种涂敷材料或其组合来以期望的方式影响多孔金属层的电和/或机械性质。用于涂敷材料的示例包括类似于铜的金属、类似于银锡合金的金属合金或类似于镍磷的其他材料。在某些实施例中,传导性材料被用来来能够实现多孔金属层的电接触。
在23处,执行衬底的进一步处理,例如另外的层的沉积、用于接触多孔金属层的结合、衬底的锯割或其他处理。在其他实施例中,不执行进一步处理。
下面,将参考图3—7来描述包括衬底和被涂敷的多孔金属层的器件的各种实施例。图3—6示出了对应结构的横截面电子显微图像。虽然示出并描述了特定材料和结构,但在其他实施例中,可使用其他材料,或者可形成其他结构。例如,虽然在所示的示例中,使用沉积在硅衬底上的多孔铜层作为示例,但在其他实施例中,可使用其他衬底材料或金属。
在图3中,在提供有种子层31的硅衬底30上沉积多孔金属层,在这种情况下为铜层32。在所示的示例中,种子层31也由铜制成,虽然也可使用其他材料,只要种子层31上的多孔铜层32的沉积是可能的。
在所示的实施例中,多孔金属层32是用镍磷(NiP)层33来三维涂敷的,其可例如通过无电(eless)沉积技术来沉积,后面是钯(Pd)层。在其他实施例中,可另外提供金层。在另外的其他实施例中,可使用镍钼磷(NiMoP)来代替NiP。
此类铜层提供用以结合的良好粘附性。例如,在图4中,示出了类似于图3的情况的涂有NiP层41的多孔铜层40,其中,结合引线42被结合到被涂敷的多孔金属层。
在图5中,示出了另外的实施例。并且,在本实施例中,在硅衬底50上沉积多孔铜层51。在图5的实施例中,由银锡合金来三维地涂敷多孔金属层51。在图5的实施例中,已经通过在多孔铜上烧结银锡焊料来执行涂敷。
在图6中示出了另外的实施例。在这里,在60处,已执行多孔铜层上的铜涂层的电流沉积,即电化学沉积。
在图7中以横截面示意性地示出了结构的另外的实施例。在这里,由圆圈来象征沉积在衬底70上的多孔金属层71,圆圈之间的间隙表示多孔金属层的孔隙。应仅将此表示视为示意性的,并且多孔金属层能够具有任何不规则形式,例如,如图3—6中所示。在图7的实施例中,用被导电层73(例如NiP/Pd/Au层或任何其他导电层)所覆盖的有机膜72来涂敷多孔金属层71。导电层73电接触多孔金属层71。
如从上述各种示例和实施例能够看到的,在各种实施例中存在用于三维地涂敷多孔金属层的各种可能性。不将给出的各种示例理解为限制性的,并且也可使用其他涂敷材料和/或其他涂敷技术。
Claims (25)
1. 一种方法,包括:
提供衬底,
在所述衬底上沉积多孔金属层,以及
用涂敷材料来三维地涂敷所述多孔金属层。
2. 权利要求1的方法,其中,所述三维涂敷包括涂敷所述多孔金属层的孔隙内的表面的至少20%。
3. 权利要求1的方法,其中,所述三维涂敷包括从气相、液相或固相中的至少一个沉积涂层。
4. 权利要求1的方法,其中,所述三维涂敷包括执行原子层沉积、化学汽相沉积、物理汽相沉积、电化学沉积、无电沉积或烧结中的至少一个。
5. 权利要求1的方法,其中,所述涂敷材料包括导电材料。
6. 权利要求1的方法,其中,所述涂敷材料包括镍磷、镍钼磷或金属中的至少一个。
7. 权利要求1的方法,其中,所述三维涂敷包括连续地沉积至少两个涂层。
8. 权利要求1的方法,其中,所述沉积多孔金属包括执行基于等离子体的沉积。
9. 权利要求1的方法,还包括在所述三维涂敷之前将所述多孔金属层结构化。
10. 一种装置,包括:
多孔金属沉积站,用以在衬底上沉积多孔金属层,以及
涂敷站,用以三维地涂敷所述多孔金属层。
11. 权利要求10的装置,还包括用以将所述多孔金属层结构化的结构化站。
12. 权利要求11的装置,其中,所述结构化站用以从所述多孔金属沉积站接收衬底以及将衬底提供给所述涂敷站。
13. 权利要求10的装置,其中,所述涂敷站被配置成执行原子层沉积、化学汽相沉积、物理汽相沉积、电化学沉积、无电淀积或烧结中的一个或多个。
14. 权利要求10的方法,其中,所述多孔金属沉积包括基于等离子体的多孔金属沉积站。
15. 一种器件,包括:
衬底,
多孔金属层,以及
涂层,三维地涂敷所述多孔金属层。
16. 权利要求15的器件,其中,所述涂层覆盖所述多孔金属层的孔隙内的表面的至少20%。
17. 权利要求16的器件,其中,所述涂层覆盖所述多孔金属层的所述孔隙内的所述表面的至少50%。
18. 权利要求15的器件,其中,所述多孔金属包括铜。
19. 权利要求15的器件,其中,所述涂层是导电的。
20. 权利要求15的器件,还包括涂敷所述涂层的另外的涂层。
21. 权利要求15的器件,其中,所述涂层包括镍磷、镍磷钼、有机材料、银锡合金或铜中的至少一个。
22. 权利要求15的器件,其中,所述衬底包括半导体晶片。
23. 权利要求22的器件,其中,所述半导体晶片包括硅。
24. 权利要求15的器件,还包括被固定于所述多孔金属层的结合引线。
25. 权利要求15的器件,其中,所述多孔金属层被结构化。
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US9362127B2 (en) * | 2013-07-23 | 2016-06-07 | Infineon Technologies Ag | Method for processing a workpiece by forming a pourous metal layer |
WO2016094660A1 (en) | 2014-12-12 | 2016-06-16 | New Valence Robotics Corporation | Additive manufacturing of metallic structures |
US9888584B2 (en) * | 2014-12-31 | 2018-02-06 | Invensas Corporation | Contact structures with porous networks for solder connections, and methods of fabricating same |
US9620466B1 (en) * | 2015-11-30 | 2017-04-11 | Infineon Technologies Ag | Method of manufacturing an electronic device having a contact pad with partially sealed pores |
US10685922B2 (en) | 2017-05-09 | 2020-06-16 | Unimicron Technology Corp. | Package structure with structure reinforcing element and manufacturing method thereof |
US10714448B2 (en) * | 2017-05-09 | 2020-07-14 | Unimicron Technology Corp. | Chip module with porous bonding layer and stacked structure with porous bonding layer |
US10178755B2 (en) * | 2017-05-09 | 2019-01-08 | Unimicron Technology Corp. | Circuit board stacked structure and method for forming the same |
US10950535B2 (en) | 2017-05-09 | 2021-03-16 | Unimicron Technology Corp. | Package structure and method of manufacturing the same |
JP6701261B2 (ja) * | 2018-05-08 | 2020-05-27 | 矢崎総業株式会社 | 筐体、電気接続箱及びワイヤハーネス |
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US11853033B1 (en) | 2019-07-26 | 2023-12-26 | Relativity Space, Inc. | Systems and methods for using wire printing process data to predict material properties and part quality |
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