CN103887175B - 带有自对准有源接触的基于高密度沟槽的功率mosfet及其制备方法 - Google Patents

带有自对准有源接触的基于高密度沟槽的功率mosfet及其制备方法 Download PDF

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CN103887175B
CN103887175B CN201310675752.3A CN201310675752A CN103887175B CN 103887175 B CN103887175 B CN 103887175B CN 201310675752 A CN201310675752 A CN 201310675752A CN 103887175 B CN103887175 B CN 103887175B
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insulating barrier
insulation spacer
layer
hard mask
groove
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CN103887175A (zh
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李亦衡
常虹
金钟五
雷燮光
哈姆扎·耶尔马兹
马督儿·博德
丹尼尔·卡拉夫特
陈军
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
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Abstract

本发明提出了一种带有自对准源极接触的高密度沟槽功率MOSFET。源极接触与第一绝缘垫片和第二绝缘垫片自对准，其中第一垫片可以抵抗选择性除去第二垫片制备材料的刻蚀工艺。另外，有源器件具有二阶栅极氧化物，其中栅极氧化物的底部厚度T2大于栅极氧化物顶部的厚度T1。

Description

带有自对准有源接触的基于高密度沟槽的功率MOSFET及其制 备方法
发明领域
本发明涉及金属氧化物半导体场效应晶体管（MOSFET），更确切地说是基于高密度沟槽的功率MOSFET。
技术背景
低压功率MOSFET通常用于负载开关器件。在负载开关器件中，要求降低器件的导通电阻（Rds）。确切地说，应该是器件的RdsA最小，其中RdsA就是器件的导通电阻与器件的有源区面积的乘积。另外，低压功率MOSFET常用于高频直流-直流器件。在这些应用中，通常要求器件的开关速度达到最大。优化开关速度最关键的三个因素为：1）Rds×Qg；2）Rds×Qoss；以及3）Qgd/Qgs之比。首先，Rds和栅极电荷（Qg）的乘积可测试器件传导和开关的共同损耗。Qg为栅漏电荷（Qgd）和栅源电荷（Qgs）之和。在第二个参数中，输出电荷Qoss用于测量当器件接通或断开时，需要充电和放电的电容。最后，使Qgd/Qgs的比值最小，当器件断开时，可以减少由很大的dV/dt导致器件接通的可能性。
如图4A所示，设计基于沟槽的MOSFET的目的之一是降低器件的RdsA。基于沟槽的MOSFET可以除去平面型MOSFET中原有的JFET结构。通过除去JFET，可以降低晶胞间距。然而，基本的基于沟槽的MOSFET在本体区中不具备任何电荷平衡，从而增大了RdsA。而且，栅极氧化物比较薄，在沟槽下方产生很高的电场，致使击穿电压较低。为了承载电压，漂流区中的掺杂浓度必须很低，从而对于带有较薄栅极氧化物的结构来说，增大了RdsA。另外，由于很难进一步减小栅极氧化物的厚度，所以随着晶胞间距持续减小，基于沟槽的MOSFET并非是一个理想的选择。
人们一直利用各种方法，试图解决上述问题。图4B表示Baliga在美国专利号5,998,833中提出的第一种示例——屏蔽栅MOSFET。利用一个连接到源极电势的基于沟槽的屏蔽电极，代替较大的栅极电极，降低了MOSFET的栅漏电容（Cgd），在高频操作时，通过减少栅极放电和充电的电量，提高了开关速度。然而，由于源极电势通过屏蔽电极电容耦合到漏极，因此Baliga提出的MOSFET器件具有很高的输出电容。而且，为了承载闭锁电压，需要很厚的氧化物。最后，为了在同一个沟槽中，制备两个电气性分隔的多晶硅电极，需要进行复杂的工艺。当器件的间距缩至很深的亚微米级别时，制备的复杂性将进一步增大。
最后，Temple在美国专利申请号4,941,026中提出的图4C所示的MOSFET设计图，具有有利于优化器件开关特性的某些特点。Temple提出的器件利用二阶栅极氧化物，在栅极顶部附近具有薄氧化层，在栅极底部具有厚氧化层，以便制成低通道电阻和低漂流电阻的器件。栅极顶部的薄氧化物可以在栅极和本体区之间提供良好的耦合，在薄氧化物附近的沟槽中，产生很强的反转以及低导通电阻。栅极底部较厚的栅极氧化物产生电荷平衡效果，使得漂流区的掺杂浓度增高。漂流区中较高的掺杂浓度降低了它的电阻。
然而，由于图4C所示器件对本体接触区的失准误差高度敏感，并不能轻松地减小它的尺寸。例如，如果器件的间距尺寸降至深亚微米级别（例如0.5-0.6μm），那么接触掩膜的失准就相当于栅极的失准，可能会对器件的性能造成很大的影响。为了形成到本体区良好的欧姆接触，在使用接触掩膜之后，注入欧姆接触区，其中欧姆接触区用导电类型与本体区相同的掺杂物重掺杂。如果接触掩膜中的开口对准得太靠近栅极，也就是说不是准确地位于硅台面结构的中心，那么使用掺杂层注入，形成同本体产生欧姆接触的接触区之后，注入的重掺杂物会终止在通道中。如果重掺杂欧姆接触区处于通道中，那么器件的阈值电压和导通电阻将受到影响。而且，如果接触掩膜对准得离栅极过远，那么双极结型晶体管（BJT）的接通将成为一个问题。因为如果接触区离沟槽较远的话，本体区的长度及其电阻都会增大。随着本体区电阻的增大，施加在本体区的电压也会增大。本体区上较大的压降将更容易地接通寄生BJT，对器件造成损坏。
因此，为了制备深亚微米级间距的功率MOSFET器件，优化后作为负载开关和高频直流-直流器件，必须使用将接触自对准到栅极的器件和方法，以避免上述不良效果。
正是在这一前提下，提出了本发明的实施例。
发明内容
本发明提供了一种MOSFET器件的制备方法，其中，包括：
a)在第一导电类型的半导体衬底顶面上方，制备一个硬掩膜，其中半导体衬底包括一个轻掺杂的漂流区，形成在衬底顶部，其中硬掩膜包括第一、第二和第三绝缘层，其中第二绝缘层夹在第一和第三绝缘层之间，其中第三绝缘层位于第二绝缘层和半导体衬底顶面之间，其中第二绝缘层可以抵抗刻蚀第一和第三绝缘层材料的刻蚀工艺，其中第一和第三绝缘层可以抵抗刻蚀第二绝缘层材料的第二次刻蚀工艺；
b)通过硬掩膜中的开口，刻蚀半导体衬底，以便在半导体衬底中形成多个沟槽，其中沟槽包括沟槽顶部和沟槽底部；
c)用第一厚度T1的顶部绝缘层内衬沟槽顶部，用第二厚度T2的底部绝缘层内衬沟槽底部，其中T2大于T1；
d)在沟槽中沉积导电材料，形成多个栅极电极；
e)在绝缘栅极电极上方制备绝缘栅极盖至少达到硬掩膜第二绝缘层的水平面处，其中绝缘栅极盖由可以被第一次刻蚀工艺刻蚀，同时抵抗第二次刻蚀工艺的材料制成；
f)利用第一次刻蚀工艺，向下刻蚀硬掩膜的第一绝缘层到硬掩膜第二绝缘层的水平面处，利用第二次刻蚀工艺，除去硬掩膜的第二绝缘层，保留与沟槽对准的绝缘栅极盖突出至硬掩膜第三绝缘层的水平面上方；
g)在衬底顶部，制备一个本体层，其中本体层为与第一导电类型相反的第二导电类型；
h)在本体层顶部，制备一个第一导电类型的源极层；
i)在绝缘栅极盖和硬掩膜第三绝缘层的裸露部分上方，制备一个第一绝缘垫片层，并且各向异性地刻蚀第一绝缘垫片层，保留沿着绝缘栅极盖侧壁的那部分第一绝缘垫片层，作为第一绝缘垫片；
j)在硬掩膜第三绝缘层的裸露部分、绝缘栅极盖和第一绝缘垫片上方，制备一个第二绝缘垫片层，各向异性地刻蚀第二绝缘垫片层，保留沿着第一绝缘垫片裸露侧壁的那部分第二绝缘垫片层，作为第二绝缘垫片；并且
k)利用第一和第二绝缘垫片作为自对准掩膜，在半导体衬底中制备用于源极接触的接触开口。
上述的方法，其中，制备多个沟槽包括穿过硬掩膜中的开口刻蚀衬底，形成沟槽顶部；沿沟槽顶部的侧壁和底面生长一个牺牲绝缘层，并且沿侧壁在牺牲绝缘层上制备垫片；将所述的垫片作为掩膜，通过刻蚀沉积在沟槽顶部底面上的牺牲绝缘层，以及沟槽顶部下方的衬底，形成沟槽底部；沿沟槽底部的侧壁和底面，生长底部绝缘层；除去垫片和牺牲绝缘层；并且沿沟槽顶部的侧壁，生长顶部绝缘层。
上述的方法，其中，硬掩膜为氧化物-氮化物-氧化物硬掩膜，其中，第一和第三绝缘层由氧化物材料制成，第二绝缘层由氮化物材料制成。
上述的方法，其中，通过CVD工艺，将第一绝缘垫片层沉积在表面上方，其中第一绝缘垫片层包括由四乙基原硅酸盐（TEOS）气制成的氧化物。
上述的方法，其中，用于制备第一绝缘垫片层的材料与绝缘栅极盖的制备材料相同。
上述的方法，其中，各向异性刻蚀第一绝缘垫片层还包括通过对刻蚀掉的那部分第一绝缘垫片层下方的那部分硬掩膜第三绝缘层的刻蚀，使得半导体衬底的一部分顶面裸露出来。
上述的方法，其中，还包括：在裸露的那部分半导体衬底的顶面上方，生长一个衬垫绝缘层。
上述的方法，其中，第一绝缘垫片和第二绝缘垫片由相同的材料制成。
上述的方法，其中，第一绝缘垫片层由氧化物制成，第二绝缘垫片层由氮化物制成。
上述的方法，其中，通过CVD工艺，在表面上方沉积第二绝缘垫片层。
上述的方法，其中，第二绝缘垫片层的厚度约为300Å。
上述的方法，其中，在衬底中制备多个沟槽还包括制备一个或多个栅极拾取沟槽，其中在沟槽中沉积导电材料还包括在栅极拾取沟槽中沉积导电材料，以制备栅极拾取电极。
上述的方法，其中，还包括：在氮化层上方沉积一层导电材料，并且利用ESD掩膜和ESD刻蚀工艺，除去硬掩膜之前，在硬掩膜第二绝缘层的上方，制备一个静电放电（ESD）保护电极。
上述的方法，其中，还包括除去硬掩膜的第二绝缘层之前，氧化ESD保护电极的表面。
上述的方法，其中，还包括： 除去硬掩膜的第二绝缘层之后，制备一个或多个本体钳位（BCL）结构，其中BCL结构是通过两次或多次掺杂物注入工艺制成的。
上述的方法，还包括，制备带有BCL结构的肖特基接触金属。
本发明还提供了一种MOSFET器件，其中，包括：
一个第一导电类型的半导体衬底，其中衬底包括一个轻掺杂漂流区，位于衬底顶部；
一个第二导电类型的本体区，形成在半导体衬底顶部，其中第二导电类型与第一导电类型相反；
由半导体衬底和本体区构成的多个有源器件结构，其中每个有源器件结构都包括一个用栅极氧化物绝缘的栅极电极，其中栅极氧化物的顶部厚度为T1，栅极氧化物底部的厚度为T2，其中T2大于T1；一个或多个第一导电类型的源极区，形成在栅极电极附近的本体区顶部；形成在每个栅极电极上方的绝缘栅极盖，其中第一绝缘垫片形成在绝缘栅极盖的侧壁上，第二绝缘垫片形成在第一绝缘垫片的裸露侧壁上；一个在本体区顶面上方的绝缘层；一个形成在绝缘层上方的导电源极电极层；将源极电极层连接到一个或多个源极区上的一个或多个电连接结构，其中通过第一和第二绝缘垫片，将一个或多个电连接结构与绝缘栅极盖分隔开。
上述的MOSFET器件，其中，第一绝缘垫片和第二绝缘垫片都是由氮化物材料制成的。
上述的MOSFET器件，其中，第二绝缘垫片可以抵抗第一次刻蚀工艺，第一次刻蚀工艺用于选择性刻蚀制备第一绝缘垫片的材料，其中第一绝缘垫片可以抵抗第二次刻蚀工艺，第二次刻蚀工艺用于选择性刻蚀制备第二绝缘垫片的材料。
上述的MOSFET器件，其中，第一绝缘垫片为氧化物材料，第二绝缘垫片为氮化物材料。
上述的MOSFET器件，其中，还包括：
一个或多个静电放电（ESD）保护ESD结构，形成在绝缘层上方。
上述的MOSFET器件，其中，还包括一个或多个栅极拾取结构，形成在半导体衬底中。
上述的MOSFET器件，其中，还包括一个本体钳位（BCL）结构。
附图说明
图1A表示依据本发明的一个方面，器件有源区的剖面图。
图1B表示依据本发明的一个方面，栅极拾取区和肖特基区的剖面图。
图1C表示基于图1A的实施例，但源极连接结构不是直接穿过ONO中最下方的一层绝缘层而是穿过衬底上方一个重新生长的氧化绝缘层。
图2表示依据本发明的一个方面，器件布局的俯视图。
图3A-3O表示依据本发明的一个方面，制备有源区、栅极拾取区和肖特基区的工艺流程的剖面图。
图4A-4C表示原有技术的基于沟槽的功率MOSFET的剖面图。
图5A-5C表示依据本发明的各个方面，用于解释MOSFET器件电学性能的图表及图形。
具体实施方式
尽管为了解释说明，以下详细说明包含了许多具体细节，但是本领域的技术人员应明确以下细节的各种变化和修正都属于本发明的范围。因此，提出以下本发明的典型实施例，并没有使所声明的方面损失任何普遍性，也没有提出任何局限。在下文中，N型器件用于解释说明。利用相同的工艺，相反的导电类型，就可以制备P型器件。
依据本发明的各个方面，可以通过自对准的源极和本体接触，制备基于高密度沟槽的功率MOSFET。源极/本体接触与第一绝缘垫片、第二绝缘垫片自对准。作为示例，第一垫片可以抵抗刻蚀工艺，刻蚀工艺将选择性地除去制备第二垫片的材料，或还可选择制备第一垫片的材料与第二垫片的材料相同。作为示例，可以用氮化物材料制备垫片。另外，有源器件具有二阶栅极氧化物，其中栅极氧化物的底部厚度为T2，栅极氧化物的顶部厚度为T1，T2大于T1。二阶栅极氧化物与自对准源极/本体接触相结合，用于制备尺寸可大幅度缩减的器件，有源器件间距在深亚微米级别（例如0.5-0.6微米）。
二阶栅极氧化物使得栅极氧化物118的底部承载绝大部分的电压，从而减少外延层107必须承载的电压。图5A表示有源器件的剖面图，显示出电场强度，其中阴影越暗表示电场强度越大。如图中沿沟槽底部的深色阴影所示，栅极氧化物118的底部承载了电场的绝大部分。图5B表示器件100闭锁的电压与衬底中深度的关系图。器件100在0.5微米左右的深度上开始闭锁电压。该深度与栅极氧化物118的底部开始厚度为T2处的深度是一致的。在沟槽底部和氧化物118附近（约1.0微米），器件总共闭锁了18V左右，大幅减少了外延层107的电压闭锁负担。因此，可以增大外延漂流层107的掺杂浓度，以降低器件的RdsA。外延层107掺杂浓度的增大，以及较小的晶胞间距导致较低的通道电阻，使得当该器件承载与图4A所示相同的电压时，与原有技术基于沟槽的MOSFET相比，RdsA下降约90%或更多，当该器件承载与图4B所示相同的电压时，与原有技术的分裂栅极MOSFET相比，RdsA下降约37%或更多。
器件的RdsA会因积累区191的位置进一步降低。如图5C所示，当栅极接通时，一个很窄的积累区191形成在沟槽侧壁附近的外延层107顶部。作为示例，积累区191的宽度约为300-400Å。沿积累区的电荷载流子浓度降低了外延层107顶部的电阻。此外，由于积累区191很薄，只要晶胞间距大于积累区191的宽度，那么减小晶胞间距就不会影响电阻。参见图4B，上述分裂栅极MOSFET器件并不具备这种特性。在分裂栅极MOSFET器件中，沟槽底部的导体保持在源极电势，防止沿侧壁附近的狭窄路径形成积累区。因此，将分裂栅极MOSFET的间距缩减至深亚微米级别并不现实。
图1A表示依据本发明的各个方面，器件结构100的有源区剖面图。器件结构100位于半导体衬底101上。形成在衬底101上的多个器件结构构成MOSFET器件，器件结构100就是这多个器件结构中的一个。此外，如同半导体制备中常见的那样，多个这样的器件可以形成在同一个衬底上。衬底101可以适当掺杂为N-型或P-型衬底。作为示例，但不作为局限，半导体衬底101可以是N-型硅衬底。半导体衬底具有一个重掺杂的N+漏极区102。作为示例，漏极区102的掺杂浓度约为1019cm-3或更大。漏极区102电连接到漏极电极102’，漏极电极102’形成在半导体衬底的底面上。漏极区102上面可以是一个轻掺杂的N-漂流区107或称漂移区。作为示例，漂流区107的掺杂浓度约在1015cm-3和1017cm-3之间。在第一导电类型的半导体衬底101顶部，制备一个第二导电类型的适当掺杂的本体层103，第二导电类型与半导体衬底101的第一导电类型相反。第一导电类型的源极区104形成在本体层103的顶部。作为示例，以及本发明中其余部分所使用的那样，半导体衬底101可以是一个N-型半导体，本体区103可以是P-型，源极区104可以是N-型。
依据本发明的各个方面，器件结构100的有源区包括多个基于沟槽的MOSFET。本发明的某些方面还可选择包括一个或多个静电放电（ESD）保护可选件的ESD结构195。通过制备穿过P-本体区103延伸到半导体衬底101中的沟槽，制备基于沟槽的功率MOSFET。每个沟槽都有一个顶部171和底部172。电介质材料118内衬沟槽壁。电介质材料118在沟槽底部172的厚度为T2，电介质材料118在沟槽顶部171的厚度为T1。依据本发明的各个方面，厚度T1小于厚度T2。作为示例，电介质材料118可以是氧化物。用适当的材料填充沟槽的剩余部分，构成一个栅极电极109。作为示例，栅极电极109可以用多晶硅制备。通过设置在沟槽上方的绝缘栅极盖108，栅极电极109与源极金属117电绝缘。绝缘层157还可以形成在源极区104上方。第一绝缘垫片111可以沿绝缘栅极盖108的每个垂直边缘设置。作为示例，但不作为局限，第一绝缘垫片111的材料与绝缘栅极盖108相同。作为示例，但不作为局限，绝缘栅极盖108、绝缘层157以及第一绝缘垫片111可以是氧化物。
虽然图1A没有表示出来，栅极电极109可以连接到栅极垫，并且保持在栅极电势。源极区104电连接到源极金属117。虽然图1A没有表示出来，作为示例，但不作为局限，利用穿过绝缘层105延伸的垂直连接结构177形成源极连接结构，如图1C所示。作为示例，但不作为局限，使用钨等导电材料制备垂直连接结构177。本发明的另外一些方面还包括内衬于设置有该垂直连接结构177的沟槽或接触孔的侧壁或底部的势垒金属165。势垒材料有利于防止不必要的扩散。作为示例，但不作为局限，势垒金属165的材料可以是钛或氮化钛。
图1C与图1A的区别在于，在图1A中源极区104上方的绝缘层157被保留而未被刻蚀，连接结构177穿过绝缘层157并延伸至源极区104下方的本体区103中，但在图1C中，绝缘层157除了位于ESD结构195下方和位于每个第一绝缘垫片111下方的部分被保留之外，其他的部分都在后续的步骤（例如图3J）中被刻蚀掉，并且因绝缘层157被刻蚀掉而裸露的衬底表面区域又重新生长了另一绝缘层105，则以自对准方式所制备的连接结构177不再穿过原先的绝缘层157，而是穿过有源区栅极沟槽附近的另一绝缘层105来接触本体区103和源极区104。
另外，第二绝缘垫片110可以将垂直连接结构177与第一绝缘垫片111隔开。作为示例，但不作为局限，第一绝缘垫片111可以由抵抗蚀刻剂的材料制成，蚀刻剂选择性地除去制成第二绝缘垫片110的材料。作为示例，第一绝缘垫片111可以是氧化物，第二绝缘垫片110可以是氮化物。氧化物能够抵抗热磷酸，而氮化物将通过热磷酸刻蚀选择性地除去。另外，第一和第二绝缘垫片110、111可以由相同的绝缘材料（例如氮化物）制成。第一和第二绝缘垫片111、110使得垂直连接结构177自对准。使用器件100上的现有结构，代替接触掩膜，以制备源极接触的垂直连接结构177，使得失准可能造成的误差降至最低。
ESD保护可选件ESD结构195可以形成在绝缘层157上方。氮化层156沉积在绝缘层157的顶面上。在氮化层156上方，制备ESD电极123。作为示例，但不作为局限，可以用多晶硅制备ESD电极123。ESD电极123除了底面之外，其他的表面都由ESD绝缘盖114覆盖屏蔽。作为示例，ESD绝缘盖114可以是氧化物。第一绝缘垫片111还可以沿ESD绝缘盖114的边缘以及氮化层156的边缘构成。第二氮化层106形成在第一绝缘垫片111周围和ESD绝缘盖114的顶面上方。外部绝缘物116形成在第二氮化层106附近例如其上方。作为示例，但不作为局限，外部绝缘物116可以是含有硼酸的硅玻璃（BPSG）。ESD电极123电连接到ESD金属128。作为示例，但不作为局限，利用穿过外部绝缘物116、第二氮化层106以及ESD绝缘盖114延伸的垂直连接结构112，制备ESD连接结构。作为示例，但不作为局限，可以用钨等导电材料制备垂直连接结构112。依据本发明的一些方面，可以用钛或氮化钛等势垒金属165内衬设置有该垂直连接结构112的沟槽或接触孔的侧壁和底部。
依据本发明的一些方面，有源区可以选择与相伴随的非有源区一起制备。图1B表示伴随器件结构100的非有源区剖面图。虚线左侧的区域是栅极拾取区126，虚线右侧的区域是肖特基区127。栅极拾取区126和肖特基区127都形成在半导体衬底101上。然而，图1B的半导体衬底101缺少本体区103和源极区104，它们位于有源区中。
利用穿过半导体衬底101顶部延伸的沟槽，制备栅极拾取结构。电介质材料118内衬沟槽壁。电介质材料118在沟槽顶部的厚度为T1，在沟槽底部的厚度为T2。厚度T1和T2与有源器件沟槽基本类似。用适当的材料填充沟槽的剩余部分，制成栅极拾取电极122。作为示例，但不作为局限，用多晶硅制备栅极拾取电极122。绝缘栅极盖108设置在沟槽上方。绝缘层157也可以设置在半导体衬底101的顶面上方。第一绝缘垫片111沿绝缘栅极盖108的每个垂直边缘形成。作为示例，但不作为局限，第一绝缘垫片111的材料与绝缘栅极盖108相同。作为示例，但不作为局限，绝缘栅极盖108、绝缘层157和第一绝缘垫片111都可以是氧化物。氮化层106形成在绝缘栅极盖108顶面上方，沿第一绝缘垫片111的顶面，以及沿第一垫片111的裸露侧面。外部绝缘物116形成在氮化层106附近例如覆盖在其上。作为示例，但不作为局限，外部绝缘物116可以是BPSG。
栅极拾取电极122电连接到栅极金属124。作为示例，但不作为局限，利用穿过外部绝缘物116、氮化层106和绝缘盖108的垂直栅极接触结构120，制备栅极连接结构。作为示例，但不作为局限，可以用钨等导电材料制备垂直的栅极接触结构120。依据本发明的一些方面，可以用钛或氮化钛等势垒金属165内衬设置有该垂直栅极接触结构120的沟槽或接触孔的侧壁和/或底部。
肖特基区127包括一个或多个本体箝位（Body clamp，简称BCL）区121，用于防止有源器件在高于它们击穿电压的情况下运行。因此，必须设计BCL区121的深度，使该区域的肖特基击穿电压高于有源器件击穿电压。在N-型半导体衬底101中，P-型掺杂物注入到衬底101中，形成BCL区121。作为示例，但不作为局限，利用离子注入系统，通过一次或多次注入工艺引入掺杂物。在10keV至500keV之间的能量范围内，注入掺杂物。本发明的一些方面包括金属接触区129，金属接触区129是制备栅极接触结构120和ESD连接结构112的原有工艺步骤的残留物。作为示例，但不作为局限，金属接触区可以是钨。肖特基接触金属125沉积在金属接触区129上方以及半导体衬底101上方。依据本发明的一些方面，肖特基接触金属125和半导体衬底之间可以内衬钛或氮化钛等势垒材料如势垒金属165。另外，栅极金属124和肖特基接触金属125相互电绝缘。
图2表示器件结构100的布局图。布局表示栅极电极109与器件区中的源极连接结构177相互相邻交替分布。源极连接结构177垂直于图平面延伸，与源极金属117电接触。栅极滑道119电连接到栅极电极109，连接到栅极拾取电极122。栅极电极、栅极滑道和栅极拾取电极可以由同种材料（例如多晶硅）制成，在一个共同的过程中这种材料形成在相应的沟槽中。栅极接触结构120垂直于图平面延伸，以便与栅极金属124电接触（图中没有表示出）。栅极金属124最初作为与源极金属117部分相同的金属层形成。例如通过常用的掩膜、刻蚀、电介质填充等工艺，栅极金属124与源极金属117电绝缘。
BCL区121位于有源器件区外部，这可以从图2所示肖特基接触金属125的位置看出。另外，ESD结构195可以形成在有源器件区外部。ESD结构195形成在绝缘层105等绝缘物上方。
图3A-3O表示在制备过程的不同阶段中，器件结构300的剖面图。垂直虚线用于区分有源区、栅极拾取区326以及肖特基区327。图3A-3O从左至右表示这三个区域，但是要注意的是，多个可能的方向中只有一个可能的方向。另外，虽然表示出了全部三个区域，但是要注意的是依据本发明的各个方面，这三个区域并不一定全部需要。
图3A表示半导体衬底301。衬底301可以适当掺杂成N-型或P-型衬底。作为示例，但不作为局限，半导体衬底可以是N-型硅衬底。半导体衬底301包括一个轻掺杂漂流区307，形成在衬底301的顶部，以及一个重掺杂漏极接触区302，形成在半导体衬底301的底部。氧化物-氮化物-氧化物（ONO）硬掩膜层形成在半导体衬底301的顶面上。作为示例，但不作为局限，底部氧化层357约为200Å，氮化层356约为3500Å，上方的顶部氧化层355约为1400Å。图3B表示多个初始工艺步骤之后的器件结构300。首先，利用沟槽掩膜刻蚀衬底301中的沟槽348和349。沟槽348形成在器件结构300的有源区中，沟槽349形成在器件结构300的栅极拾取区326中。第一次刻蚀工艺包括利用蚀刻剂除去ONO硬掩膜层357、356、355，以便使衬底301的顶面裸露出来，再通过第二次刻蚀工艺，制备沟槽348和349的顶部371。作为示例，但不作为局限，沟槽348和349的顶部371约为0.5μm深。一旦形成沟槽之后，要在每个沟槽348、349中热生长大约100Å的衬垫氧化物318a。生长衬垫氧化物318a之后，可以在衬垫氧化物318上方沉积一个氮化层346。作为示例，但不作为局限，氮化层346的厚度约为500Å。
图3C表示沟槽底部372的形成过程。首先，通过一次或多个刻蚀工艺，除去沟槽底面上的氮化层346和氧化层318a。此后，可以刻蚀沟槽371顶部下方的衬底301，以增加沟槽348、349的深度。作为示例，但不作为局限，沟槽348、349的顶部和底部的总深度约为1μm。此后，在沟槽底部372的裸露硅中热生长衬里氧化物318b。作为示例，沟槽底部中衬里氧化物318b的厚度T2可以生长至600Å左右。沿沟槽顶部侧壁的氮化层346作为一个掩膜，减小了沟槽底部372的宽度。然后，通过湿法刻蚀，除去沟槽顶部371侧壁上的氮化物346和衬垫氧化物318a。在沟槽顶部侧壁处的裸露硅上生长一个栅极氧化物318c，生长至所需厚度T1。作为示例，但不作为局限，对于12V的器件来说，栅极氧化物318c的厚度T1约为265Å。因此，沟槽372底部的栅极氧化物318的厚度T2大于沟槽371顶部的厚度T1。在图3D中，用导电材料填充沟槽348、349，以便形成栅极电极309和栅极拾取电极322。作为示例，但不作为局限，导电材料可以是N+-掺杂多晶硅，通过化学气相沉积（CVD）沉积多晶硅。利用化学机械抛光（CMP）除去多余的多晶硅，并且使栅极电极309和栅极拾取电极322与硬掩膜的表面相平。然后，如图3E所示，将栅极电极309、栅极拾取电极322回刻至半导体衬底301的表面。通过干刻蚀工艺，回刻栅极电极309、栅极拾取电极322。
在图3F中，利用ONO硬掩膜作为自对准掩膜，在每个栅极电极309、栅极拾取电极322上方形成绝缘盖308。当有源器件间距降至深亚微米级别时，为绝缘盖308使用自对准掩膜，可以降低失准的可能性。作为示例，但不作为局限，绝缘盖308可以是氧化物。一旦形成绝缘盖308之后，可以通过CMP除去ONO硬掩膜的顶部氧化层355。通过CMP还可以使绝缘盖308与氮化层356相平。依据本发明的某些方面，可以选择将静电放电（ESD）保护可选件引入到器件的有源区中。为了制备ESD保护可选件ESD结构395，可以在氮化层356的表面上形成一个多晶硅层。然后，利用ESD掩膜，选择性地刻蚀多晶硅层并留下部分多晶硅形成ESD电极323。在图3G中，氧化ESD电极323，形成ESD绝缘盖314，以便在后续的工艺步骤中，保护表面。作为示例，但不作为局限，绝缘盖314的厚度约为300Å。形成ESD绝缘盖314之后，除去氮化层356。作为示例，通过热磷酸湿法腐蚀，除去氮化层356。ESD电极323和绝缘盖314下方的那部分氮化层356被保护起来，不被湿法刻蚀除去。
在图3H中，制备本体区303。作为示例，但不作为局限，利用本体掩膜和全面注入，或者通过离子注入系统选择性地注入离子，制备本体区303。图3H还表示制备源极区304。作为示例，但不作为局限，利用源极掩膜和全面注入，或者通过离子注入系统选择性地注入离子，制备源极区304。屏蔽栅极拾取区326和肖特基区327，不接受本体注入和源极注入。此外，图3H还表示出了本体钳位（BCL）区321的注入。利用BCL掩膜，通过一次或多次注入工艺，注入BCL区321。作为示例，但不作为局限，第一次注入是在大约40keV下注入BF2形成的浅P+注入。同时，第二次注入工艺，是在大约100keV下利用硼注入，改变了BCL区321注入的深度和成分。在大约300keV下，利用硼注入，深注入可以改变BCL区321注入的深度和成分。
图3I表示沉积一个很厚的牺牲绝缘层311’。作为示例，牺牲绝缘层的厚度可以是1,100Å。而且，作为示例，绝缘层311’可以是通过带有四乙基原硅酸盐（TEOS）等气源气体的化学气相沉积法CVD所沉积的氧化物。还可选择，绝缘层311’可以是通过使用SiH4和NH3气体混合物的CVD工艺所沉积的氮化物材料。然后，在图3J中，利用各向异性刻蚀（例如干刻蚀工艺），刻蚀厚绝缘层311’，从而在每个绝缘盖308的一侧以及沿ESD结构395侧边，形成第一绝缘垫片311。作为示例，第一绝缘垫片311的厚度可以是1000Å。当绝缘层311’是氧化物时，刻蚀工艺可以在硅衬底的表面终止，从而除去ONO硬掩膜上不在第一绝缘垫片311下方的那部分底部氧化层357。然后，在衬底301的表面上方，生长衬垫氧化物305。作为示例，但不作为局限，衬垫氧化物305的厚度可以是100Å。
图3J’表示当绝缘层311’为氮化物材料时，制备可以用在器件中的第一绝缘垫片311的可选工艺。可以通过各向异性刻蚀工艺，选择性地刻蚀掉氮化物材料，在适当的位置保留ONO硬掩膜的底部氧化层357。因此，无需生长衬垫氧化物305。一旦形成第一绝缘垫片311之后，具有由氮化物材料制成的第一绝缘垫片311的器件工艺，可以继续用上述由氧化物制成的第一绝缘垫片311的制备工艺相同的方式进行。
制成第一绝缘垫片311之后，如图3K所示，可以在表面上方沉积一个牺牲氮化层306。作为示例，氮化层306的厚度可以是300Å。可以利用SiH4和NH3气体混合物的CVD工艺，沉积氮化层306。如图3L所示，通过CVD工艺，在氮化层306上方，沉积一个厚的含有硼酸的硅玻璃（BPSG）层316。
在图3M中，利用接触掩膜，提供到ESD电极323、栅极拾取电极322和BCL区321（或称BCL结构）的垂直接触的接口。刻蚀工艺可以利用三个单独的刻蚀步骤。首先，利用刻蚀除去BPSG层316，但并不除去BPSG下方的氮化层306。由于作为刻蚀终止层的氮化物层306的存在，不可能发生过度刻蚀，因此对BPSG层316可以使用快速刻蚀。第二次刻蚀是通过对氮化层306进行选择性刻蚀。然后，利用对氧化物具有高选择性的第三次刻蚀，为栅极拾取电极322穿透绝缘盖308，为ESD电极穿透ESD绝缘盖314，为肖特基区327穿透氧化层305。
在图3N中，沉积一个光致抗蚀剂层361，利用第二接触掩膜使有源晶胞区即晶体管单元区裸露出来。此后，进行第一次刻蚀工艺，选择性地除去有源区上方的BPSG层316。第二次各向异性刻蚀工艺，例如干刻蚀工艺，可以选择性地除去牺牲氮化层306。由于各向异性刻蚀的方向选择性，刻蚀后仍然留下一部分牺牲氮化层306。剩余的牺牲氮化层306成为第二绝缘垫片材料310。第二绝缘垫片材料310自对准接触沟槽347。如上所述，由于自对准的源极接触减少了失准的几率，从而增强了可扩展性。接下来的刻蚀工艺除去扩孔氧化层305，最后刻蚀半导体衬底301，例如大约035Å的深度，以便通过自对准接触沟槽347，连接到源极和本体区。
图3O表示器件结构300最终的工艺步骤。首先，在整个表面上方沉积一个势垒金属365，它可以防止扩散到源极区304中。作为示例，但不作为局限，势垒金属可以是通过物理气相沉积（PVD）所沉积的钛，或者通过CVD或PVD沉积的TiN等合金。沉积势垒金属365之后，可以沉积导电材料，以形成垂直源极连接结构377、ESD连接结构312和栅极连接结构320。作为示例，但不作为局限，通过CVD所沉积的钨制备垂直连接结构。一旦沉积一层钨之后，回刻这层钨，保留最初在垂直接触孔中的钨。另外，肖特基区中可能会残留多余的钨329。然后，在整个表面上方沉积金属，形成到垂直源极连接结构377、ESD连接结构312和栅极连接结构320以及BCL区321的适当接触。作为示例，但不作为局限，沉积的金属可以是溅射的铝。最后，利用金属掩膜，刻蚀掉一部分沉积的金属，而使ESD金属328、源极金属317、栅极金属324以及肖特基接触金属325中的接触区电绝缘。
尽管以上是本发明的较佳实施例的完整说明，但是也有可能使用各种可选、修正和等效方案。因此，本发明的范围不应局限于以上说明，而应由所附的权利要求书及其全部等效内容决定。本方法中所述步骤的顺序并不用于局限进行相关步骤的特定顺序的要求。任何可选件（无论首选与否），都可与其他任何可选件（无论首选与否）组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非在指定的权利要求中用“意思是”特别指出，否则所附的权利要求书应认为是包括意义及功能的限制。

Claims (23)

1.一种MOSFET器件的制备方法，其特征在于，包括：
a)在第一导电类型的半导体衬底顶面上方，制备一个硬掩膜，其中半导体衬底包括一个轻掺杂的漂移区，形成在衬底顶部，其中硬掩膜包括第一、第二和第三绝缘层，其中第二绝缘层夹在第一和第三绝缘层之间，其中第三绝缘层位于第二绝缘层和半导体衬底顶面之间，其中第二绝缘层可以抵抗刻蚀第一和第三绝缘层材料的刻蚀工艺，其中第一和第三绝缘层可以抵抗刻蚀第二绝缘层材料的第二次刻蚀工艺；
b)通过硬掩膜中的开口，刻蚀半导体衬底，以便在半导体衬底中形成多个沟槽，其中沟槽包括沟槽顶部和沟槽底部；
c)用第一厚度T1的顶部绝缘层内衬沟槽顶部，用第二厚度T2的底部绝缘层内衬沟槽底部，其中T2大于T1；
d)在沟槽中沉积导电材料，形成多个栅极电极；
e)在栅极电极上方制备绝缘栅极盖至少达到硬掩膜第二绝缘层的水平面处，其中绝缘栅极盖由可以被第一次刻蚀工艺刻蚀，同时抵抗第二次刻蚀工艺的材料制成；
f)利用第一次刻蚀工艺，向下刻蚀硬掩膜的第一绝缘层到硬掩膜第二绝缘层的水平面处，利用第二次刻蚀工艺，除去硬掩膜的第二绝缘层，保留与沟槽对准的绝缘栅极盖突出至硬掩膜第三绝缘层的水平面上方；
g)在衬底顶部，制备一个本体层，其中本体层为与第一导电类型相反的第二导电类型；
h)在本体层顶部，制备一个第一导电类型的源极层；
i)在绝缘栅极盖和硬掩膜第三绝缘层的裸露部分上方，制备一个第一绝缘垫片层，并且各向异性地刻蚀第一绝缘垫片层，保留沿着绝缘栅极盖侧壁的那部分第一绝缘垫片层，作为第一绝缘垫片；
j)在硬掩膜第三绝缘层的裸露部分、绝缘栅极盖和第一绝缘垫片上方，制备一个第二绝缘垫片层，各向异性地刻蚀第二绝缘垫片层，保留沿着第一绝缘垫片裸露侧壁的那部分第二绝缘垫片层，作为第二绝缘垫片；并且
k)利用第一和第二绝缘垫片作为自对准掩膜，在半导体衬底中制备用于源极接触的接触开口。
2.如权利要求1所述的方法，其特征在于，制备多个沟槽包括穿过硬掩膜中的开口刻蚀衬底，形成沟槽顶部；沿沟槽顶部的侧壁和底面生长一个牺牲绝缘层，并且沿侧壁在牺牲绝缘层上制备垫片；将所述的垫片作为掩膜，通过刻蚀沉积在沟槽顶部底面上的牺牲绝缘层，以及沟槽顶部下方的衬底，形成沟槽底部；沿沟槽底部的侧壁和底面，生长底部绝缘层；除去垫片和牺牲绝缘层；并且沿沟槽顶部的侧壁，生长顶部绝缘层。
3.如权利要求1所述的方法，其特征在于，硬掩膜为氧化物-氮化物-氧化物硬掩膜，其中，第一和第三绝缘层由氧化物材料制成，第二绝缘层由氮化物材料制成。
4.如权利要求1所述的方法，其特征在于，通过CVD工艺，将第一绝缘垫片层沉积在表面上方，其中第一绝缘垫片层包括由四乙基原硅酸盐(TEOS)气制成的氧化物。
5.如权利要求1所述的方法，其特征在于，用于制备第一绝缘垫片层的材料与绝缘栅极盖的制备材料相同。
6.如权利要求5所述的方法，其特征在于，各向异性刻蚀第一绝缘垫片层还包括通过对刻蚀掉的那部分第一绝缘垫片层下方的那部分硬掩膜第三绝缘层的刻蚀，使得半导体衬底的一部分顶面裸露出来。
7.如权利要求6所述的方法，其特征在于，还包括：在裸露的那部分半导体衬底的顶面上方，生长一个衬垫绝缘层。
8.如权利要求1所述的方法，其特征在于，第一绝缘垫片和第二绝缘垫片由相同的材料制成。
9.如权利要求1所述的方法，其特征在于，第一绝缘垫片层由氧化物制成，第二绝缘垫片层由氮化物制成。
10.如权利要求9所述的方法，其特征在于，通过CVD工艺，在表面上方沉积第二绝缘垫片层。
11.如权利要求10所述的方法，其特征在于，第二绝缘垫片层的厚度约为
12.如权利要求1所述的方法，其特征在于，在衬底中制备多个沟槽还包括制备一个或多个栅极拾取沟槽，其中在沟槽中沉积导电材料还包括在栅极拾取沟槽中沉积导电材料，以制备栅极拾取电极。
13.如权利要求1所述的方法，其特征在于，还包括：在第二绝缘层上方沉积一层导电材料，并且利用静电放电掩膜和静电放电刻蚀工艺，除去硬掩膜之前，在硬掩膜第二绝缘层的上方，制备一个静电放电保护电极。
14.如权利要求13所述的方法，其特征在于，还包括除去硬掩膜的第二绝缘层之前，氧化静电放电保护电极的表面。
15.如权利要求1所述的方法，其特征在于，还包括：除去硬掩膜的第二绝缘层之后，制备一个或多个本体钳位结构，其中本体钳位结构是通过两次或多次掺杂物注入工艺制成的。
16.如权利要求15所述的方法，还包括，制备带有本体钳位结构的肖特基接触金属。
17.一种MOSFET器件，其特征在于，包括：
一个第一导电类型的半导体衬底，其中衬底包括一个轻掺杂漂移区，位于衬底顶部；
一个第二导电类型的本体区，形成在半导体衬底顶部，其中第二导电类型与第一导电类型相反；
由半导体衬底和本体区构成的多个有源器件结构，其中每个有源器件结构都包括一个用栅极氧化物绝缘的栅极电极，其中栅极氧化物的顶部厚度为T1，栅极氧化物底部的厚度为T2，其中T2大于T1；一个或多个第一导电类型的源极区，形成在栅极电极附近的本体区顶部；形成在每个栅极电极上方的绝缘栅极盖，其中第一绝缘垫片形成在绝缘栅极盖的侧壁上，第二绝缘垫片形成在第一绝缘垫片的裸露侧壁上；一个在本体区顶面上方的绝缘层；一个形成在绝缘层上方的导电源极电极层；将源极电极层连接到一个或多个源极区上的一个或多个电连接结构，其中通过第一和第二绝缘垫片，将一个或多个电连接结构与绝缘栅极盖分隔开。
18.如权利要求17所述的MOSFET器件，其特征在于，第一绝缘垫片和第二绝缘垫片都是由氮化物材料制成的。
19.如权利要求17所述的MOSFET器件，其特征在于，第二绝缘垫片可以抵抗第一次刻蚀工艺，第一次刻蚀工艺用于选择性刻蚀制备第一绝缘垫片的材料，其中第一绝缘垫片可以抵抗第二次刻蚀工艺，第二次刻蚀工艺用于选择性刻蚀制备第二绝缘垫片的材料。
20.如权利要求19所述的MOSFET器件，其特征在于，第一绝缘垫片为氧化物材料，第二绝缘垫片为氮化物材料。
21.如权利要求17所述的MOSFET器件，其特征在于，还包括：
一个或多个静电放电保护ESD结构，形成在绝缘层上方。
22.如权利要求17所述的MOSFET器件，其特征在于，还包括一个或多个栅极拾取结构，形成在半导体衬底中。
23.如权利要求17所述的MOSFET器件，其特征在于，还包括一个本体钳位结构。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
JP6036765B2 (ja) * 2014-08-22 2016-11-30 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
US9484452B2 (en) 2014-12-10 2016-11-01 Alpha And Omega Semiconductor Incorporated Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs
US9281368B1 (en) 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
US9691863B2 (en) 2015-04-08 2017-06-27 Alpha And Omega Semiconductor Incorporated Self-aligned contact for trench power MOSFET
US9583586B1 (en) 2015-12-22 2017-02-28 Alpha And Omega Semiconductor Incorporated Transient voltage suppressor (TVS) with reduced breakdown voltage
KR102411401B1 (ko) 2016-03-08 2022-06-22 삼성전자주식회사 반도체 소자 및 이의 제조방법
CN108701715B (zh) * 2016-03-31 2021-04-27 新电元工业株式会社 半导体装置的制造方法以及半导体装置
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10446545B2 (en) 2016-06-30 2019-10-15 Alpha And Omega Semiconductor Incorporated Bidirectional switch having back to back field effect transistors
US10056461B2 (en) 2016-09-30 2018-08-21 Alpha And Omega Semiconductor Incorporated Composite masking self-aligned trench MOSFET
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10199492B2 (en) 2016-11-30 2019-02-05 Alpha And Omega Semiconductor Incorporated Folded channel trench MOSFET
JP6643382B2 (ja) * 2017-03-20 2020-02-12 インフィニオン テクノロジーズ オーストリア アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｕｓｔｒｉａ ＡＧ パワー半導体デバイス
US10325908B2 (en) 2017-04-26 2019-06-18 Alpha And Omega Semiconductor Incorporated Compact source ballast trench MOSFET and method of manufacturing
US10211333B2 (en) 2017-04-26 2019-02-19 Alpha And Omega Semiconductor (Cayman) Ltd. Scalable SGT structure with improved FOM
US10714580B2 (en) 2018-02-07 2020-07-14 Alpha And Omega Semiconductor (Cayman) Ltd. Source ballasting for p-channel trench MOSFET
CN110557969B (zh) * 2018-04-03 2023-05-16 深圳市汇顶科技股份有限公司 阻变式存储器的制造方法和阻变式存储器
CN110729286B (zh) * 2018-07-17 2022-05-03 上海宝芯源功率半导体有限公司 一种包含静电保护结构的半导体开关器件及其制作方法
US11189702B2 (en) * 2019-01-30 2021-11-30 Vishay SIliconix, LLC Split gate semiconductor with non-uniform trench oxide
CN111785771A (zh) * 2019-04-03 2020-10-16 杭州士兰微电子股份有限公司 双向功率器件
US11049956B2 (en) 2019-06-17 2021-06-29 Semiconductor Components Industries, Llc Method of forming a semiconductor device
EP3863066A1 (en) * 2020-02-06 2021-08-11 Infineon Technologies Austria AG Transistor device and method of fabricating a gate of a transistor device
CN112382613B (zh) * 2020-11-12 2023-10-03 重庆万国半导体科技有限公司 一种沟槽功率器件与源极电容集成及其制造方法

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US6262453B1 (en) 1998-04-24 2001-07-17 Magepower Semiconductor Corp. Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate
GB9815021D0 (en) * 1998-07-11 1998-09-09 Koninkl Philips Electronics Nv Semiconductor power device manufacture
US6545316B1 (en) * 2000-06-23 2003-04-08 Silicon Wireless Corporation MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US7345342B2 (en) 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP4932088B2 (ja) * 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
US6437401B1 (en) * 2001-04-03 2002-08-20 Infineon Technologies Ag Structure and method for improved isolation in trench storage cells
GB2381122B (en) 2001-10-16 2006-04-05 Zetex Plc Termination structure for a semiconductor device
US20080197408A1 (en) 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7973381B2 (en) 2003-09-08 2011-07-05 International Rectifier Corporation Thick field oxide termination for trench schottky device
US6977208B2 (en) 2004-01-27 2005-12-20 International Rectifier Corporation Schottky with thick trench bottom and termination oxide and process for manufacture
US7045857B2 (en) 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
US7183610B2 (en) 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
US7109552B2 (en) * 2004-11-01 2006-09-19 Silicon-Based Technology, Corp. Self-aligned trench DMOS transistor structure and its manufacturing methods
TWI401749B (zh) 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
US7659570B2 (en) 2005-05-09 2010-02-09 Alpha & Omega Semiconductor Ltd. Power MOSFET device structure for high frequency applications
AT504289A2 (de) 2005-05-26 2008-04-15 Fairchild Semiconductor Trench-gate-feldeffekttransistoren und verfahren zum bilden derselben
TWI400757B (zh) 2005-06-29 2013-07-01 Fairchild Semiconductor 形成遮蔽閘極場效應電晶體之方法
KR100763330B1 (ko) * 2005-12-14 2007-10-04 삼성전자주식회사 활성 핀들을 정의하는 소자분리 방법, 이를 이용하는반도체소자의 제조방법 및 이에 의해 제조된 반도체소자
KR100845103B1 (ko) 2005-12-28 2008-07-09 동부일렉트로닉스 주식회사 반도체소자의 제조방법
US7829941B2 (en) * 2006-01-24 2010-11-09 Alpha & Omega Semiconductor, Ltd. Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions
US7579650B2 (en) 2006-08-09 2009-08-25 International Rectifier Corporation Termination design for deep source electrode MOSFET
US7750398B2 (en) 2006-09-26 2010-07-06 Force-Mos Technology Corporation Trench MOSFET with trench termination and manufacture thereof
CN101536164B (zh) 2006-09-27 2012-06-20 巨能半导体股份有限公司 具有凹陷场板的功率金属氧化物半导体场效应晶体管
US7800185B2 (en) 2007-01-28 2010-09-21 Force-Mos Technology Corp. Closed trench MOSFET with floating trench rings as termination
JP4470960B2 (ja) 2007-05-21 2010-06-02 ソニー株式会社 表示装置及びその駆動方法と電子機器
US7799642B2 (en) 2007-10-02 2010-09-21 Inpower Semiconductor Co., Ltd. Trench MOSFET and method of manufacture utilizing two masks
US7585705B2 (en) * 2007-11-29 2009-09-08 Alpha & Omega Semiconductor, Inc. Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop
US8042088B2 (en) 2007-12-27 2011-10-18 Cadence Design Systems, Inc. Method and system for implementing stacked vias
JP2009212369A (ja) * 2008-03-05 2009-09-17 Elpida Memory Inc 半導体装置及び半導体装置の製造方法並びにデータ処理システム
WO2009151657A1 (en) * 2008-06-11 2009-12-17 Maxpower Semiconductor Inc. Super self-aligned trench mosfet devices, methods and systems
US7807576B2 (en) 2008-06-20 2010-10-05 Fairchild Semiconductor Corporation Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices
JP5693809B2 (ja) * 2008-07-04 2015-04-01 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
JP2010028029A (ja) * 2008-07-24 2010-02-04 Renesas Technology Corp 半導体装置および半導体装置の製造方法
US8362548B2 (en) * 2008-11-14 2013-01-29 Semiconductor Components Industries, Llc Contact structure for semiconductor device having trench shield electrode and method
US7851312B2 (en) 2009-01-23 2010-12-14 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
US8058685B2 (en) 2009-07-08 2011-11-15 Force Mos Technology Co., Ltd. Trench MOSFET structures using three masks process
KR101594031B1 (ko) * 2009-08-28 2016-02-15 삼성전자주식회사 불순물이 도핑된 폴리실리콘층 내에 불순물 확산 방지층을 갖는 반도체 소자 및 이를 이용한 디램 소자
US8252647B2 (en) 2009-08-31 2012-08-28 Alpha & Omega Semiconductor Incorporated Fabrication of trench DMOS device having thick bottom shielding oxide
US8138605B2 (en) * 2009-10-26 2012-03-20 Alpha & Omega Semiconductor, Inc. Multiple layer barrier metal for device component formed in contact trench
US7989887B2 (en) 2009-11-20 2011-08-02 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates as termination
US8525255B2 (en) 2009-11-20 2013-09-03 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
US8575695B2 (en) 2009-11-30 2013-11-05 Alpha And Omega Semiconductor Incorporated Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode
US8247296B2 (en) 2009-12-09 2012-08-21 Semiconductor Components Industries, Llc Method of forming an insulated gate field effect transistor device having a shield electrode structure
US20110156682A1 (en) 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
US8399925B2 (en) 2010-02-12 2013-03-19 Alpha & Omega Semiconductor, Inc. Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method
US8779510B2 (en) * 2010-06-01 2014-07-15 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US8580667B2 (en) * 2010-12-14 2013-11-12 Alpha And Omega Semiconductor Incorporated Self aligned trench MOSFET with integrated diode
US8829640B2 (en) 2011-03-29 2014-09-09 Alpha And Omega Semiconductor Incorporated Configuration and method to generate saddle junction electric field in edge termination
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8816476B2 (en) * 2011-04-27 2014-08-26 Alpha & Omega Semiconductor Corporation Through silicon via processing techniques for lateral double-diffused MOSFETS
US8466513B2 (en) 2011-06-13 2013-06-18 Semiconductor Components Industries, Llc Semiconductor device with enhanced mobility and method
US8803251B2 (en) 2011-07-19 2014-08-12 Alpha And Omega Semiconductor Incorporated Termination of high voltage (HV) devices with new configurations and methods
US8569765B2 (en) 2011-07-20 2013-10-29 Force Mos Technology Co., Ltd. MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures
JP5562917B2 (ja) * 2011-09-16 2014-07-30 株式会社東芝 半導体装置及びその製造方法
US8772901B2 (en) 2011-11-11 2014-07-08 Alpha And Omega Semiconductor Incorporated Termination structure for gallium nitride schottky diode
US8614482B2 (en) 2011-12-30 2013-12-24 Force Mos Technology Co., Ltd. Semiconductor power device having improved termination structure for mask saving
US8653587B2 (en) 2012-02-13 2014-02-18 Force Mos Technology Co., Ltd. Trench MOSFET having a top side drain
JP2013197551A (ja) * 2012-03-22 2013-09-30 Toshiba Corp 半導体装置及びその製造方法
US9029215B2 (en) 2012-05-14 2015-05-12 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure
US20140097491A1 (en) 2012-10-05 2014-04-10 Texas Instruments Incorporated Dielectrically Terminated Superjunction FET
TW201423869A (zh) * 2012-12-13 2014-06-16 Anpec Electronics Corp 溝渠式電晶體的製作方法
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8753935B1 (en) * 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
US8710585B1 (en) 2013-02-25 2014-04-29 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
US9018700B2 (en) 2013-03-14 2015-04-28 Fairchild Semiconductor Corporation Direct-drain trench FET with source and drain isolation
JP6219140B2 (ja) 2013-11-22 2017-10-25 ルネサスエレクトロニクス株式会社 半導体装置
US9705405B2 (en) 2015-06-26 2017-07-11 Astec International Limited Power converters and methods for reducing voltage changes at an output of a power converter

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US20150145037A1 (en) 2015-05-28
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