CN103887174B - 用于负载开关和直流-直流器件的高密度mosfet的器件结构及其制备方法 - Google Patents

用于负载开关和直流-直流器件的高密度mosfet的器件结构及其制备方法 Download PDF

Info

Publication number
CN103887174B
CN103887174B CN201310675735.XA CN201310675735A CN103887174B CN 103887174 B CN103887174 B CN 103887174B CN 201310675735 A CN201310675735 A CN 201310675735A CN 103887174 B CN103887174 B CN 103887174B
Authority
CN
China
Prior art keywords
groove
insulating barrier
layer
hard mask
conduction type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310675735.XA
Other languages
English (en)
Other versions
CN103887174A (zh
Inventor
哈姆扎·耶尔马兹
马督儿·博德
常虹
李亦衡
丹尼尔·卡拉夫特
金钟五
雷燮光
陈军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Publication of CN103887174A publication Critical patent/CN103887174A/zh
Application granted granted Critical
Publication of CN103887174B publication Critical patent/CN103887174B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

本发明的各个方面提出了一种带有自对准源极接触的基于高密度沟槽的功率MOSFET，以及这类器件的制备方法。源极接触与垫片自对准，垫片沿栅极盖的侧壁形成。另外，有源器件具有二阶栅极氧化物。其中栅极氧化物底部的厚度大于顶部的厚度。二阶栅极氧化物与自对准的源极接触相结合，从而制备的器件间距可以在深亚微米级别。

Description

用于负载开关和直流-直流器件的高密度MOSFET的器件结构及其制备方法
发明领域
本发明涉及金属氧化物半导体场效应晶体管（MOSFET），更确切地说是基于高密度沟槽的功率MOSFET。
技术背景
低压功率MOSFET通常用于负载开关器件。在负载开关器件中，要求降低器件的导通电阻（Rds）。确切地说，应该是器件的RdsA必须最小，其中RdsA就是器件的导通电阻与器件的有源区面积的乘积。另外，低压功率MOSFET常用于高频直流-直流器件。在这些应用中，通常要求器件的开关速度达到最大。优化开关速度最关键的三个因素为：1）Rds×Qg；2）Rds×Qoss；以及3）Qgd/Qgs之比。首先，Rds和栅极电荷（Qg）的乘积可测试器件传导和开关的共同损耗。Qg为栅漏电荷（Qgd）和栅源电荷（Qgs）之和。在第二个参数中，输出电荷Qoss用于测量当器件接通或断开时，需要充电和放电的电容。最后，使Qgd/Qgs的比值最小，当器件断开时，可以减少由很大的dV/dt导致器件接通的可能性。
如图1A所示，设计基于沟槽的MOSFET的目的之一是降低器件的RdsA。基于沟槽的MOSFET可以除去平面型MOSFET中原有的JFET结构。通过除去JFET，可以降低晶胞间距。然而，基本的基于沟槽的MOSFET在本体区中不具备任何电荷平衡，从而增大了RdsA。而且，栅极氧化物比较薄，在沟槽下方产生很高的电场，致使击穿电压较低。为了承载电压，漂流区中的掺杂浓度必须很低，从而对于带有较薄栅极氧化物的结构来说，增大了RdsA。另外，由于很难进一步减小栅极氧化物的厚度，所以随着晶胞间距持续减小，基于沟槽的MOSFET并非是一个理想的选择。
人们一直试图利用各种方法，解决上述问题。图1B表示Baliga在美国专利号5,998,833中提出的第一种示例——屏蔽栅MOSFET。利用一个连接到源极电势的基于沟槽的屏蔽电极，代替较大的栅极电极，降低了MOSFET的栅漏电容（Cgd），在高频操作时，通过减少栅极放电和充电的电量，提高了开关速度。然而，由于源极电势通过屏蔽电极电容耦合到漏极，因此Baliga提出的MOSFET器件具有很高的输出电容。而且，为了承载闭锁电压，需要很厚的氧化物。最后，为了在同一个沟槽中，制备两个电气性分隔的多晶硅电极，需要进行复杂的工艺。当器件的间距缩至很深的亚微米级别时，制备的复杂性将进一步增大。
最后，Temple在美国专利申请号4,941,026中提出的图1C所示的MOSFET设计图，具有有利于优化器件开关特性的某些特点。Temple提出的器件利用二阶栅极氧化物，在栅极顶部附近具有薄氧化层，在栅极底部具有厚氧化层，以便制成低通道电阻和低漂流电阻的器件。栅极顶部的薄氧化物可以在栅极和本体区之间提供良好的耦合，在薄氧化物附近的沟槽中，产生很强的反转以及低导通电阻。栅极底部较厚的栅极氧化物产生电荷平衡效果，使得漂流区的掺杂浓度增高。漂流区中较高的掺杂浓度降低了它的电阻。
然而，由于图1C所示器件对本体接触区的失准误差高度敏感，并不能轻松地减小它的尺寸。例如，如果器件的间距尺寸降至深亚微米级别（例如0.5-0.6μm），那么接触掩膜的失准就相当于栅极的失准，可能会对器件的性能造成很大的影响。为了形成到本体区良好的欧姆接触，在使用接触掩膜之后，重掺杂注入欧姆接触区，其中欧姆接触区用导电类型与本体区相同的掺杂物重掺杂。如果接触掩膜中的开口对准得太靠近栅极，也就是说不是准确地位于硅台面结构的中心，那么使用掺杂层注入，形成同本体产生欧姆接触的接触区之后，注入的重掺杂物终止在通道中。如果重掺杂欧姆接触区处于通道中，那么器件的阈值电压和导通电阻将受到影响。而且，如果接触掩膜对准得离栅极过远，那么双极结型晶体管（BJT）的接通将成为一个问题。因为如果接触离沟槽较远的话，本体区的长度及其电阻都会增大。随着本体区电阻的增大，施加在本体区的电压也会增大。本体区上较大的压降将更容地接通寄生BJT，对器件造成损坏。
因此，为了制备深亚微米器件，优化后作为负载开关和高频直流-直流器件，必须使用将接触自对准到栅极的器件和方法，以避免上述不良效果。
正是在这一前提下，提出了本发明的实施例。
发明内容
本发明提供了一种用于制备MOSFET器件的方法，其中，包括：
a）在第一导电类型的半导体衬底顶面上方，制备一个硬掩膜，其中硬掩膜包括第一和第二绝缘层，其中第二绝缘层抵抗刻蚀第一绝缘层的第一次刻蚀工艺，第一绝缘层可以抵抗刻蚀第二绝缘层的第二次刻蚀工艺；
b）通过硬掩膜中的开口，刻蚀半导体衬底，以便在半导体衬底中形成多个沟槽，其中沟槽包括沟槽顶部和沟槽底部；
c）用第一厚度T1的顶部绝缘层内衬沟槽顶部，用第二厚度T2的底部绝缘层内衬沟槽底部，其中T2大于T1；
d）在沟槽中沉积导电材料，形成多个栅极电极；
e）在栅极电极上方制备绝缘栅极盖至少达到硬掩膜第二绝缘层的水平处，其中绝缘栅极盖由可以被第一次刻蚀工艺刻蚀，同时抵抗第二次刻蚀工艺的材料制成；
f）利用第一次刻蚀工艺，除去硬掩膜的第一绝缘层，保留与沟槽对准的绝缘栅极盖突出至硬掩膜第二绝缘层的水平上方；
g）在衬底顶部，制备一个本体层，其中本体层为与第一导电类型相反的第二导电类型；
h）在硬掩膜的第二绝缘层和绝缘栅极盖上方，制备一个绝缘垫片层；
i）在绝缘垫片层上方，制备一个导电或半导体垫片层，并且各向异性地刻蚀导电或半导体垫片层和绝缘垫片层，保留沿着绝缘栅极盖侧壁的那部分导电或绝缘垫片层和绝缘垫片层，作为导电或半导体垫片和绝缘垫片；并且
j）利用导电或半导体垫片作为自对准掩膜，在半导体衬底中形成开口，用于源极接触。
上述的方法，其中，制备多个沟槽包括穿过硬掩膜和衬底中的开口刻蚀，形成沟槽的顶部；沿沟槽顶部的侧壁和底面生长一个顶部绝缘层，并且沿侧壁在顶部绝缘层上制备垫片；将垫片作为掩膜，刻蚀沉积在沟槽顶部底面上的绝缘层，以及沟槽顶部下方的衬底，形成沟槽的底部；沿沟槽底部的侧壁和底面，生长底部绝缘层；并且除去垫片。
上述的方法，其中，制备多个沟槽包括穿过硬掩膜和衬底中的开口刻蚀，形成沟槽的顶部和底部；沿沟槽顶部和底部的侧壁和底面生长底部绝缘层；用第一部分导电材料填充沟槽底部；从沟槽顶部除去底部绝缘层；沿沟槽顶部侧壁以及沿沟槽底部中导电材料的顶面，生长顶部绝缘层；利用第二部分导电材料在顶部绝缘层上沿侧壁形成垫片；并且从沟槽底部中导电材料的顶面上刻蚀掉顶部绝缘层。
上述的方法，其中，还包括：在本体层下面制备一个子本体层，其中子本体层为第二导电类型，其掺杂浓度小于本体层的掺杂浓度。
上述的方法，其中，形成本体层之前，通过第二导电类型的离子注入，形成子本体层。
上述的方法，其中，子本体层延伸到沟槽顶部以下。
上述的方法，其中，在衬底中制备多个沟槽还包括制备一个或多个栅极拾取沟槽，其中在沟槽中沉积导电材料还包括在栅极拾取沟槽中沉积导电材料，以形成栅极拾取电极，其中一个或多个栅极拾取沟槽形成在第二导电类型的掺杂槽中，掺杂槽形成在半导体衬底中。
上述的方法，其中，还包括：在通过硬掩膜的第一绝缘层上方沉积一层导电材料，并且利用ESD掩膜和ESD刻蚀工艺，除去硬掩膜的第一绝缘层之前，先在硬掩膜的第一绝缘层上方，制备一个静电放电（ESD）保护电极。
上述的方法，其中，还包括在除去硬掩膜的第二层之前，先氧化ESD保护电极的表面。
上述的方法，其中，还包括：配置一个或多个肖特基接触结构，以终止器件，其中制备肖特基接触结构还包括制备一个或多个本体钳位（BCL）结构。
上述的方法，其中，还包括：在半导体衬底中的开口附近，制备一个欧姆接触区，用于源极接触，其中欧姆接触区具有高浓度的第二导电类型掺杂物, 所述的MOSFET器件中有源器件的间距小于0.6微米。
本发明还提供了一种MOSFET器件，其中，包括：
一个第一导电类型的半导体衬底，其中衬底包括一个轻掺杂的外延区，在衬底顶部；
一个第二导电类型的本体区，形成在半导体衬底顶部，其中第二导电类型与第一导电类型相反；
半导体衬底和本体区构成的多个有源器件结构，其中每个有源器件结构都含有一个与栅极氧化物绝缘的栅极电极，其中栅极氧化物顶部的厚度为T1，栅极氧化物底部的厚度为T2，其中T2大于T1；一个或多个第一导电类型的源极区，形成在栅极电极附近的本体区顶部；一个绝缘栅极盖，形成在每个栅极电极上方，其中绝缘垫片形成在绝缘栅极盖的侧壁上，导电或半导体垫片形成在绝缘垫片的裸露侧壁上，绝缘层在本体区的顶面上；一个导电源极金属层形成在绝缘层上方；一个或多个电连接结构，将源极金属层与一个或多个源极区连接起来，其中绝缘垫片将一个或多个电连接结构与绝缘栅极盖分开。
上述的MOSFET器件，其中，导电或半导体垫片为多晶硅垫片。
上述的MOSFET器件，其中，用第一导电类型的掺杂物掺杂多晶硅垫片。
上述的MOSFET器件，其中，省去了半导体衬底顶部外延区的第一导电类型的源极区。
上述的MOSFET器件，其中，还包括一个子本体层，其中子本体层为第二导电类型的轻掺杂区，形成在本体区域底面以下，其中子本体层的深度延伸到沟槽顶部下方。
上述的MOSFET器件，其中，还包括一个或多个静电放电（ESD）保护结构。
上述的MOSFET器件，其中，还包括一个或多个栅极拾取沟槽。
上述的MOSFET器件，其中，还包括一个肖特基接触结构，其中肖特基接触结构为本体钳位结构。
附图说明
图1A-1C表示原有技术的MOSFET器件。
图2A-2C表示依据本发明的各个方面，用于解释MOSFET器件电学性能的图表及图形。
图3A-3E表示依据本发明的各个方面，多个MOSFET器件的剖面图。
图4表示依据本发明的各个方面，MOSFET器件的架空布局模式。
图5A-5J表示依据本发明的各个方面，MOSFET器件制备方法的剖面图。
图6A-6B表示依据本发明的各个方面，MOSFET器件的可选制备方法的剖面图。
图7A-7E表示依据本发明的各个方面，MOSFET器件的二阶栅极氧化物的可选制备方法的剖面图。
具体实施方式
尽管为了解释说明，以下详细说明包含了许多具体细节，但是本领域的技术人员应明确以下细节的各种变化和修正都属于本发明的范围。因此，提出以下本发明的典型实施例，并没有使所声明的方面损失任何普遍性，也没有提出任何局限。在下文中，N型器件用于解释说明。利用相同的工艺，相反的导电类型，就可以制备P型器件。
本发明的各个方面提出了一种带有自对准源极和本体接触的基于高密度沟槽的功率MSOFET。源极/本体接触与导电或半导体（例如掺杂多晶硅）垫片自对准。垫片沿栅极盖的侧壁形成。另外，有源器件具有二阶栅极氧化物，其中栅极氧化物的底部厚度为T2，栅极氧化物的顶部厚度为T1，T2大于T1。二阶栅极氧化物与自对准源极/本体接触相结合，用于制备可大幅缩减尺寸的器件，有源器件间距在深亚微米级别，例如0.5-0.6微米。
本发明的其他方面提出了一种类似的器件，在该器件的硅外延部分中，没有源极区。依据本发明的这一方面，半导体垫片（例如N+-掺杂多晶硅垫片）也可以作为源极区，因此在衬底中增加源极区可以省去。本发明的其他方面提出了一种类似的器件，通过将掺杂物从掺杂多晶硅垫片扩散至器件的硅外延部分中，在器件的硅外延部分中形成源极区。
本发明的其他方面提出了一种带有自对准源极接触的基于高密度沟槽的功率MOSFET，自对准源极接触适用于高开关速度。除了自对准源极接触和二阶栅极氧化物之外，快速开关MOSFET还包括一个在本体区下面的轻掺杂P-区。轻掺杂P-区削弱了器件栅极和漏极之间的耦合。
二阶栅极氧化物使得栅极氧化物374的底部可以承载绝大部分的电压，从而减少外延层307必须承载的电压。图2A表示有源器件的剖面图，显示出电场强度，其中阴影越暗表示电场强度越大。如图中沿沟槽底部的深色阴影所示，栅极氧化物374的底部承载了电场的绝大部分。图2B表示器件300闭锁的电压与衬底中深度的关系图。器件300在0.5微米左右的深度上开始闭锁电压。该深度与栅极氧化物118的底部开始厚度为T2处的深度是一致的。在沟槽底部和氧化物374附近（约1.0微米），器件总共闭锁了18V左右，大幅减少了外延层307的电压闭锁负担。因此，可以增大外延漂流层307的掺杂浓度，以降低器件的RdsA。外延层307掺杂浓度的增大，以及较小的晶胞间距导致较低的通道电阻，使得当该器件承载与图1A所示相同的电压时，与原有技术基于沟槽的MOSFET相比，RdsA下降约90%或更多，当该器件承载与图1B所示相同的电压时，与原有技术的分裂栅极MOSFET相比，RdsA下降约37%或更多。
器件的RdsA会因积累区391的位置进一步降低。如图2C所示，当栅极接通时，一个很窄的积累区391形成在沟槽侧壁附近的外延层307顶部。作为示例，积累区391的宽度约为300-400Å。沿积累区的电荷载流子浓度降低了外延层307顶部的电阻。此外，由于积累区391很薄，只要晶胞间距大于积累区391的宽度，那么减小晶胞间距就不会影响电阻。参见图1B，上述分裂栅极MOSFET器件并不具备这种特性。在分裂栅极MOSFET器件中，沟槽底部的导体保持在源极电势，防止沿侧壁附近的狭窄路径形成积累区391。因此，将分裂栅极MOSFET的间距缩减至深亚微米级别并不现实。
图3A表示依据本发明的各个方面，器件结构300的有源区剖面图。器件结构300位于半导体衬底301上。衬底301可以适当掺杂为N-型或P-型衬底。本文所用的衬底301将成为N-型衬底。半导体衬底301具有一个重掺杂的N+漏极区302和外延层307。作为示例，漏极区302的掺杂浓度约为1019cm-3或更大。外延层307可以生长在漏极区302上方，并且轻掺杂N-型掺杂物。作为示例，外延层107的掺杂浓度约在1015cm-3和1017cm-3之间。一个适当掺杂的P-本体层303或本体区形成在外延层307顶部。N+-掺杂源极区304形成在本体层303顶部。
依据本发明的各个方面，器件结构300的有源区包括多个基于沟槽的MOSFET。通过制备穿过P-本体层303延伸到外延层307中的沟槽370，制备基于沟槽的功率MOSFET。每个沟槽370都有一个顶部371和底部372。用厚度为T1的顶部绝缘层373内衬沟槽的顶部371，用厚度为T2的底部绝缘层374内衬沟槽的底部372。依据本发明的各个方面，要求厚度T1小于厚度T2。作为示例，顶部和底部绝缘层373、374可以是氧化物。用适当的材料填充沟槽的剩余部分，形成栅极电极309。作为示例，栅极电极309可以用多晶硅制备。虽然图3A没有表示出来，栅极电极309连接到栅极垫，并且保持在栅极电势。每个栅极电极309都通过绝缘栅极盖308与源极金属317电绝缘，绝缘栅极盖308设置在沟槽上方。为绝缘层的硬掩膜第二层355也形成在源极区304上方。通过沿栅极盖308的垂直边缘形成绝缘垫片341，可以降低栅极电极309到源极材料317之间发生短路的可能性。作为示例，绝缘垫片341可以是氧化物。
源极区304通过衬底中的自对准接触开口389电连接到源极材料317，自对准接触开口389穿过作为绝缘层的硬掩膜第二层355和源极区304延伸。沿绝缘垫片341的裸露侧壁形成的N+-掺杂多晶硅垫片342，使开口389自对准。这些垫片作为刻蚀工艺的掩膜层，用于制备接触开口389。N+-掺杂多晶硅垫片342增大了到源极的接触面积，降低了接触电阻，有利于形成欧姆接触。作为示例，但不作为局限，可以通过导电插头357形成电连接。作为示例，但不作为局限，导电插头357可以由钨等导电材料制成。增加一个欧姆接触区343，可以增强导电插头357和P-本体层303之间的欧姆接触。欧姆接触区343是一个重掺杂P-区，形成在自对准接触开口389的裸露表面上。作为示例，在大约1×1019cm-3的掺杂浓度下，注入硼等P-型掺杂物，可以形成欧姆接触区343。
自对准的接触开口389互相离得很近，使得MOSFET器件中有源器件的间距P小于1.0微米。更确切地说，本发明的各个方面提出了允许器件的间距P小于0.6微米。即使当器件的间距尺寸小于1.0微米时，由于接触开口389的自对准消除了对准误差，因此这个间距也是可能的。这样可以确保来自于欧姆接触区343的掺杂物仍然在通道外，从而保持了器件的阈值电压。另外，由于沟槽侧壁和导电插头之间的距离将在这个器件上基本保持恒定，因此接触开口389的自对准有利于精确控制寄生BJT的开启。恒定的间距使得本体区电阻和本体区中的电压降在整个器件上也基本保持恒定。因此，对于每个有源器件来说，使寄生BJT开启的情况有微小的差别。
依据本发明的另一个附加方面，还可以配置器件结构300’，用于直流-直流器件等快速开关器件。图3B表示结构300’，它与图3A所示的器件300类似，但是增加了一个子本体层388。子本体层388为轻掺杂P-层，形成在P-本体层303下方，并且电连接到源极金属。子本体层388的掺杂浓度应非常低，使得反转通道形成在底部绝缘层374附近。轻掺杂的子本体层388的掺杂范围从1×1014cm-3至1×1016cm-3左右。器件300’增加子本体层388，削弱了栅极电极和漏极电极之间的耦合，从而大幅提高了Qg、Qgd和Qoss的值。此外，器件的Rds-on只有些许增加。如上所述，这些变量都属于决定器件开关速度的关键品质因数。通过使Qg、Qgd和Qoss最大，而Rds-on只有些许增加，大幅提高了器件300’的开关速度。子本体层388的深度延伸到沟槽顶部371下方。随着子本体层388深度的增加，开关速度也会得到改善。然而，深度的增加也会使Rds-on增大。
图3C表示依据本发明的一个附加方面，器件300”从半导体衬底301的顶部省去了源极区304。除了去掉源极区304之外，器件300”与图3A所示的器件300基本类似。由于N+-掺杂多晶硅垫片342具有高浓度N-型掺杂物，可以作为源极区，因此可以省去源极区304。使用N+-掺杂多晶硅垫片342作为源极区，可以减少制备过程中的源极注入，显著抑制了寄生双极管的开启现象。
如图3D所示，器件300还可以含有一个静电放电（ESD）保护结构395。ESD保护结构395可以是形成在双层硬掩膜中第一层356上方的导电材料396。选择性掺杂导电材料396，使其含有N-型和P-型区。绝缘层397形成在导电材料396的顶面上方。
如图3D所示，器件300还可以含有一个或多个栅极拾取沟槽370’。 栅极拾取沟槽370’与有源器件沟槽370基本类似。然而，栅极拾取电极322代替电绝缘栅极电极309，穿过栅极盖308的电连接结构320，电连接到栅极金属324上。作为示例，但不作为局限，电连接结构320可以是钨。栅极拾取沟槽370’可以形成在深掺杂区361中，掺杂区361的掺杂物导电类型与衬底301相反。作为示例，但不作为局限，如果衬底301为N-型，那么深掺杂区361将掺杂P-型，在这种情况下，有时也称为“P-槽（P-Tub）”。还可选择，如果衬底301为P-型，那么深掺杂区361将掺杂N-型，在这种情况下，有时也称为“N-槽（N-Tub）”。图3E表示还可以选择为器件300配置一个或多个肖特基接触结构或构件，使电场终止。肖特基接触结构与P-槽361相结合，也可以作为本体钳位（Body clamp，简称BCL），用于防止有源器件在高于它们击穿电压的情况下运行。如图3E所示，金属接触结构321将肖特基金属325电连接到半导体衬底301。作为示例，金属接触结构321可以穿过具有第一层356和第二层355的硬掩膜延伸。作为示例，但不作为局限，第一层356可以是氮化层，第二层355可以是氧化层。作为示例，但不作为局限，金属接触结构321可以是钨。肖特基金属325可以沉积在金属接触结构321和硬掩膜356的第一层356上方，并且与栅极金属324绝缘。另外，栅极金属324和肖特基金属325之间相互电绝缘。
图4表示器件结构300的布局图。该布局表示栅极电极309和导电插头357交替出现在器件区中。作为源极接触结构的导电插头357垂直于图平面延伸，与源极金属317电接触。栅极滑道319电连接到栅极电极309，连接到栅极拾取电极322。栅极电极、栅极滑道和栅极拾取电极可以由同种材料（例如多晶硅）制成，在一个共同的过程中这种材料形成在相应的沟槽中。作为栅极接触结构的电连接结构320垂直于图平面延伸，以便与栅极金属324电接触（图中没有表示出）。栅极金属324最初作为与源极金属317部分相同的金属层形成。例如通过常用的掩膜、刻蚀、电介质填充等工艺，栅极金属324与源极金属317和/或肖特基金属325电绝缘。
BCL区位于有源器件区外部，这可以从图4所示肖特基金属325的位置看出。另外，ESD结构395可以形成在有源器件区外部。ESD结构395形成在绝缘层305等绝缘物上方。虽然，图中所示的ESD结构395位于有源区外，但是它们也可以位于栅极拾取区外。
本发明的各个方面提出了图3A-3E所示器件的制备方法。结合所述的制备方法，图5A-5J表示在制备过程的不同阶段中，器件结构500的剖面图。
图5A表示半导体衬底501。半导体衬底501可以适当掺杂成N-型或P-型衬底。为了解释说明，此处所用的半导体衬底501将是N-型衬底。半导体衬底501包括一个重掺杂漏极接触区502，带有一个轻掺杂外延区507生长在漏极接触区502上方。重掺杂P-槽561形成在外延层507中。利用离子注入或其他任意适当的方法，制备P-槽。作为示例，但不作为局限，P-槽掩膜可以和P-型掺杂物的掩膜注入一起使用。
硬掩膜具有一个第一绝缘层556和一个第二绝缘层555，形成在半导体衬底501的顶面上。第二绝缘层555可以抵抗刻蚀第一绝缘层556的第一次刻蚀工艺，第一绝缘层556可以抵抗刻蚀第二绝缘层555的第二次刻蚀工艺。作为示例，但不作为局限，第一绝缘层556可以是氮化层，第二绝缘层555可以是氧化物。作为示例，第一绝缘层556的厚度约为0.2μm至0.5μm，第二绝缘层555的厚度约为50Å至250Å。
在图5B中，利用沟槽掩膜，穿过硬掩膜的第一和第二绝缘层556、555刻蚀，限定沟槽570的位置。另外，栅极拾取沟槽570’也可以在同一个刻蚀工艺中限定。然后，在图5C中，利用部分沟槽刻蚀，制备沟槽570和栅极拾取沟槽570’的顶部571。沟槽的顶部571大约为沟槽570总深度的一半左右。作为示例，但不作为局限，沟槽顶部的深度D1约为0.5μm。通过宽度为WM的台面结构将每个沟槽570与其他沟槽分开。作为示例，宽度WM为0.2μm至0.5μm之间。作为示例，每个沟槽宽度WT为0.2μm至0.5μm之间。
在图5D中，薄衬垫氧化物575和绝缘垫片546内衬在沟槽的顶部571。衬垫氧化物575和绝缘垫片546防止沟槽的顶部571在沟槽底部572的处理过程中生长氧化物。绝缘垫片546还作为一个额外的掩膜层，以缩减沟槽底部572的宽度。作为示例，绝缘垫片546可以是氮化物。形成绝缘垫片546之后，可以通过刻蚀工艺，制备沟槽底部572。作为示例，但不作为局限，代表沟槽底部572的沟槽第二部分的深度D2增加0.5μm，致使沟槽570、栅极拾取沟槽570’的总深度约为1.0μm。
然后，在图5E中，形成底部绝缘层574。作为示例，但不作为局限，通过热氧化，生长氧化物，形成底部绝缘层574。厚度T2的范围通常为400Å-1500Å。在图5F中，首先除去衬垫氧化物575和绝缘垫片546。然后，生长顶部绝缘层573，也就是栅极氧化物。厚度T1的范围通常为50Å-500Å。虽然厚度T1和T2的范围稍有重叠，但是我们要求底部绝缘层574的厚度T2大于顶部绝缘层573的厚度T1。生长顶部绝缘层573之后，用导电材料填充沟槽570和栅极拾取沟槽570’，以便在有源器件中形成栅极电极509，在栅极拾取沟槽570’中形成栅极拾取电极522。为了使栅极电极509和栅极拾取电极522中形成空隙的可能性降至最低，沟槽的宽度和深度之比应不超过1:6。作为示例，但不作为局限，用于填充栅极电极509和栅极拾取电极522的导电材料可以是掺杂了N-型掺杂物的多晶硅。一旦填充沟槽570和栅极拾取沟槽570’之后，向下刻蚀导电材料，以便与半导体衬底501的顶面基本相平。
在图5G中，形成绝缘栅极盖508。绝缘栅极盖508可以用沉积的氧化物制备，例如但不局限于含有硼酸的硅玻璃（BPSG）或四乙基原硅酸盐（TEOS）。沉积绝缘栅极盖508之后，使其表面与硬掩膜的第一绝缘层556的顶面相平。作为示例，但不作为局限，可以利用化学机械平整化（CMP）进行平整。作为示例，但不作为局限，栅极盖508的厚度约为300 Å。最初刻蚀硬掩膜的第一绝缘层556和第二绝缘层555，用于制备沟槽掩膜，由于存在第一绝缘层556和第二绝缘层555，因此栅极盖508自对准。无需额外的掩膜对准工艺，就可以改善栅极盖508的对准。另外，栅极盖508的自对准为自对准的源极接触提供了基础。因此，准确地对准栅极盖508是非常关键的。
绝缘栅极盖508制成之后，通过掩膜和第一刻蚀工艺，在器件500的有源区中除去硬掩膜的第一绝缘层556。第一次刻蚀工艺选择性地除去硬掩膜的第一绝缘层556，对硬掩膜的第二绝缘层555几乎不会造成影响。作为示例，如果硬掩膜第一绝缘层556为氮化物，硬掩膜第二绝缘层555为氧化物，那么热磷酸湿法腐蚀就会优先除去氮化物，而保留氧化物。一旦除去了硬掩膜第一绝缘层556，则在半导体衬底501的顶部注入P-本体503。注入N+-源极区504也可以在除去硬掩膜第一绝缘层556之后。然后，沿栅极盖508的侧壁形成绝缘垫片541，以避免在栅极电极509和源极金属517之间发生短路。在器件的裸露表面上沉积一个绝缘层，然后通过各向异性刻蚀工艺刻蚀掉绝缘层，形成绝缘垫片541。各向异性刻蚀会留下沿栅极盖508侧壁的那部分绝缘层，作为绝缘垫片541。氧化之后，沿硬掩膜第二绝缘层555的顶面，在绝缘垫片541的裸露表面上和栅极盖508的顶面上沉积一个多晶硅层。用高浓度的N-型掺杂物掺杂多晶硅层。然后，通过绝缘垫片541，利用各向异性刻蚀除去多晶硅层，仅保留距离栅极盖508侧壁较远的多晶硅垫片542。作为示例，但不作为局限，各向异性刻蚀工艺可以是反应离子刻蚀（RIE）。穿过硬掩膜第二绝缘层555，也进行各向异性刻蚀工艺。此外，利用多晶硅垫片542，通过扩散工艺代替上述注入工艺，形成源极区504。将N-型掺杂物从多晶硅垫片542，扩散到垫片542下方的外延层507顶部，形成源极区504。
外延层507的顶部裸露出来之后，穿过外延层，再一次利用各向异性刻蚀工艺，使带有自对准接触开口547的P-本体区503裸露出来。多晶硅垫片542保护下面的源极区504，从而使源极区504在整个器件500上保持尺寸一致。为了提供更好的源极金属517欧姆接触，可以在自对准的接触开口547的表面中注入高浓度的P-型掺杂物，以便形成欧姆接触区543。作为示例，可以利用硼表面注入，形成欧姆接触区543。
依据本发明的其他方面，器件500还可以具有ESD结构595。图5H’表示在从有源区中除去第一硬掩膜层556之前，形成ESD结构595。作为示例，可以通过在器件500的顶面上方首先沉积一个未掺杂的多晶硅层，制备ESD结构。然后利用第一个ESD掩膜，将N-型掺杂物选择性地掺杂到多晶硅区域，成为ESD二极管596。可以在P-本体注入时注入ESD二极管596的P-型部分。然后，利用第二个ESD掩膜，选择性地除去多晶硅层，以便形成ESD二极管596。在ESD二极管596上方生长一个绝缘层597，在后续的处理工艺中提供保护。此后，依据图5H所示的工艺，处理器件500。
图6A表示配置器件600’的过程，用于提升开关速度。器件600’的工艺除了增加制备子本体层688的工艺之外，其他都与器件500的工艺类似。提供在本体层603的底面以下注入轻掺杂P-区，形成子本体层688。该注入过程可以在注入P-本体层603和/或源极区604之前或之后进行。此后，依据与器件500相同的工艺继续进行处理。
图6B表示器件600”的处理过程。器件600”的工艺除了没有源极区注入到半导体衬底601中之外，其他都与器件500的工艺类似。由于多晶硅垫片642中存在了N-型掺杂物，可以作为源极区，因此该器件仍然可以有效运行。此后的处理工艺可依据器件500的工艺进行。
回到器件500，按照标准的接触形成工艺继续进行。在图5I中，在器件的顶面上沉积一个光致抗蚀剂层516。利用栅极接触掩膜，穿过栅极拾取电极522上方的栅极盖，形成一个开口。另外，栅极接触掩膜所提供的开口，使得硬掩膜第一和第二绝缘层556、555在器件的非有源区可以被刻蚀穿透，形成肖特基结构的一个接触结构520。在图5J中，除去光致抗蚀剂层，制备器件500，用于金属化。源极接触结构557或称导电插头形成在自对准接触开口547中。作为示例，但不作为局限，源极接触结构557可以是钨。还可以制备接触结构520，栅极拾取电极522上方的绝缘栅极盖508中的开口内的接触结构520（或称电连接结构）将栅极拾取电极522连接到栅极金属524，并且第一和第二绝缘层556、555在器件的非有源区被刻蚀穿透的开口内的接触结构520将肖特基金属525连接到衬底501。作为示例，接触结构520可以由钨制成。最终，在器件的顶面上沉积一个金属层。然后利用金属掩膜，刻蚀金属层，形成源极金属517、栅极金属524和肖特基金属525，肖特基金属525连接到源极金属517。
本发明的各个方面还提出了一个制备二阶沟槽氧化层的额外工艺。首先，在图7A中，利用刻蚀工艺，穿过硬掩膜，在衬底701中形成沟槽770、770’，硬掩膜具有第一绝缘层756和第二绝缘层755形成在半导体衬底701的顶面上。衬底701含有一个重掺杂N+漏极区702和外延层707。沟槽770和沟槽770’基本类似。沟槽770可以用作有源MOSFET结构，位于器件700的有源区中。沟槽770’可用作栅极拾取结构，位于器件的非有源区中。如图所示，沟槽770’形成在P-槽761中。所形成的沟槽770、770’深度为DT，宽度为WT。作为示例，深度DT约为1.0微米，宽度WT约在0.2μm至0.5μm之间。沟槽通过一个台面结构相互分隔开，台面结构的宽度WM约为0.2μm-0.5μm。
形成沟槽770、770’之后，如图7B所示，沿沟槽壁和沟槽底面，形成一个绝缘层774。绝缘层774的厚度为T2。作为示例，但不作为局限，厚度T2约为400Å至1500Å。然后，用导电材料的第一部分7091填充沟槽770、770’。向下回刻导电材料7091，使它仅填充沟槽的底部772。
在图7C中，刻蚀掉沟槽顶部771的绝缘层774。导电材料的第一部分7091保护沟槽底部772的绝缘层774不受刻蚀影响。然后，在沟槽的顶部771侧壁上生长顶部绝缘层773。顶部绝缘层773的厚度为T1。作为示例，但不作为局限，厚度T1约为50Å至500Å。另外，要注意的是，虽然厚度T1和T2的范围稍有重叠，但是我们要求T2仍然应大于T1。在生长顶部绝缘层773时，还可以在导电材料的第一部分7091顶面上方，形成一个绝缘层773’。导电材料709两部分之间的绝缘层将使栅极电极的底部不处于栅极电势。然而，仅刻蚀掉不需要的绝缘层773’会对顶部绝缘层773造成损坏。
因此，在图7D中，可以用导电材料第二部分7092填充沟槽770。然后，利用各向异性刻蚀工艺，除去导电材料的第二部分7092，仅仅保留侧壁垫片，保护顶部绝缘层773不受后续刻蚀工艺的影响。然后，通过适当的刻蚀工艺，除去不需要的绝缘层773’。除去后，用导电材料的第三部分7093填充沟槽770的剩余部分，如图7E所示。此后的处理工艺按照器件500的工艺进行。
尽管以上是本发明的较佳实施例的完整说明，但是也有可能使用各种可选、修正和等效方案。因此，本发明的范围不应局限于以上说明，而应由所附的权利要求书及其全部等效内容决定。本方法中所述步骤的顺序并不用于局限进行相关步骤的特定顺序的要求。任何可选件（无论首选与否），都可与其他任何可选件（无论首选与否）组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非在指定的权利要求中用“意思是”特别指出，否则所附的权利要求书应认为是包括意义及功能的限制。

Claims (19)

1.一种用于制备MOSFET器件的方法，其特征在于，包括：
a)在第一导电类型的半导体衬底顶面上方，制备一个硬掩膜，其中硬掩膜包括第一和第二绝缘层，其中第二绝缘层抵抗刻蚀第一绝缘层的第一次刻蚀工艺，第一绝缘层可以抵抗刻蚀第二绝缘层的第二次刻蚀工艺；
b)通过硬掩膜中的开口，刻蚀半导体衬底，以便在半导体衬底中形成多个沟槽，其中沟槽包括沟槽顶部和沟槽底部；
c)用第一厚度T1的顶部绝缘层内衬沟槽顶部，用第二厚度T2的底部绝缘层内衬沟槽底部，其中T2大于T1；
d)在沟槽中沉积导电材料，形成多个栅极电极；
e)在栅极电极上方制备绝缘栅极盖至少达到硬掩膜第二绝缘层的水平处，其中绝缘栅极盖由可以被第一次刻蚀工艺刻蚀，同时抵抗第二次刻蚀工艺的材料制成；
f)利用第一次刻蚀工艺，除去硬掩膜的第一绝缘层，保留与沟槽对准的绝缘栅极盖突出至硬掩膜第二绝缘层的水平上方；
g)在衬底顶部，制备一个本体层，其中本体层为与第一导电类型相反的第二导电类型；
h)在硬掩膜的第二绝缘层和绝缘栅极盖上方，制备一个绝缘垫片层；
i)在绝缘垫片层上方，制备一个导电或半导体垫片层，并且各向异性地刻蚀导电或半导体垫片层和绝缘垫片层，保留沿着绝缘栅极盖侧壁的那部分导电或半导体垫片层和绝缘垫片层，作为导电或半导体垫片和绝缘垫片；并且
j)利用导电或半导体垫片作为自对准掩膜，在半导体衬底中形成开口，用于源极接触。
2.权利要求1所述的方法，其特征在于，制备多个沟槽包括穿过硬掩膜和衬底中的开口刻蚀，形成沟槽的顶部；沿沟槽顶部的侧壁和底面生长一个顶部绝缘层，并且沿侧壁在顶部绝缘层上制备垫片；将垫片作为掩膜，刻蚀沉积在沟槽顶部底面上的绝缘层，以及沟槽顶部下方的衬底，形成沟槽的底部；沿沟槽底部的侧壁和底面，生长底部绝缘层；并且除去垫片。
3.权利要求1所述的方法，其特征在于，制备多个沟槽包括穿过硬掩膜和衬底中的开口刻蚀，形成沟槽的顶部和底部；沿沟槽顶部和底部的侧壁和底面生长底部绝缘层；用第一部分导电材料填充沟槽底部；从沟槽顶部除去底部绝缘层；沿沟槽顶部侧壁以及沿沟槽底部中导电材料的顶面，生长顶部绝缘层；利用第二部分导电材料在顶部绝缘层上沿侧壁形成垫片；并且从沟槽底部中导电材料的顶面上刻蚀掉顶部绝缘层。
4.权利要求1所述的方法，其特征在于，还包括：在本体层下面制备一个子本体层，其中子本体层为第二导电类型，其掺杂浓度小于本体层的掺杂浓度。
5.权利要求4所述的方法，其特征在于，形成本体层之前，通过第二导电类型的离子注入，形成子本体层。
6.权利要求4所述的方法，其特征在于，子本体层延伸到沟槽顶部以下。
7.权利要求1所述的方法，其特征在于，在衬底中制备多个沟槽还包括制备一个或多个栅极拾取沟槽，其中在沟槽中沉积导电材料还包括在栅极拾取沟槽中沉积导电材料，以形成栅极拾取电极，其中一个或多个栅极拾取沟槽形成在第二导电类型的掺杂槽中，掺杂槽形成在半导体衬底中。
8.权利要求1所述的方法，其特征在于，还包括：在通过硬掩膜的第一绝缘层上方沉积一层导电材料，并且利用ESD掩膜和ESD刻蚀工艺，除去硬掩膜的第一绝缘层之前，先在硬掩膜的第一绝缘层上方，制备一个静电放电(ESD)保护电极。
9.权利要求8所述的方法，其特征在于，还包括在除去硬掩膜的第二层之前，先氧化ESD保护电极的表面。
10.权利要求1所述的方法，其特征在于，还包括：配置一个或多个肖特基接触结构，以终止器件，其中制备肖特基接触结构还包括制备一个或多个本体钳位(BCL)结构。
11.权利要求1所述的方法，其特征在于，还包括：在半导体衬底中的开口附近，制备一个欧姆接触区，用于源极接触，其中欧姆接触区具有高浓度的第二导电类型掺杂物，所述的MOSFET器件中有源器件的间距小于0.6微米。
12.一种MOSFET器件，其特征在于，包括：
一个第一导电类型的半导体衬底，其中衬底包括一个轻掺杂的外延区，在衬底顶部；
一个第二导电类型的本体区，形成在半导体衬底顶部，其中第二导电类型与第一导电类型相反；
半导体衬底和本体区构成的多个有源器件结构，其中每个有源器件结构都含有一个与栅极氧化物绝缘的栅极电极，其中栅极氧化物顶部的厚度为T1，栅极氧化物底部的厚度为T2，其中T2大于T1；一个或多个第一导电类型的源极区，形成在栅极电极附近的本体区顶部；一个绝缘栅极盖，形成在每个栅极电极上方，其中绝缘垫片形成在绝缘栅极盖的侧壁上，导电或半导体垫片形成在绝缘垫片的裸露侧壁上，绝缘层在本体区的顶面上；一个导电源极金属层形成在绝缘层上方；一个或多个电连接结构，将源极金属层与一个或多个源极区连接起来，其中绝缘垫片将一个或多个电连接结构与绝缘栅极盖分开。
13.权利要求12所述的MOSFET器件，其特征在于，导电或半导体垫片为多晶硅垫片。
14.权利要求13所述的MOSFET器件，其特征在于，用第一导电类型的掺杂物掺杂多晶硅垫片。
15.权利要求14所述的MOSFET器件，其特征在于，省去了半导体衬底顶部外延区的第一导电类型的源极区。
16.权利要求12所述的MOSFET器件，其特征在于，还包括一个子本体层，其中子本体层为第二导电类型的轻掺杂区，形成在本体区域底面以下，其中子本体层的深度延伸到沟槽顶部下方。
17.权利要求12所述的MOSFET器件，其特征在于，还包括一个或多个静电放电(ESD)保护结构。
18.权利要求12所述的MOSFET器件，其特征在于，还包括一个或多个栅极拾取沟槽。
19.权利要求12所述的MOSFET器件，其特征在于，还包括一个肖特基接触结构，其中肖特基接触结构为本体钳位结构。
CN201310675735.XA 2012-12-21 2013-12-11 用于负载开关和直流-直流器件的高密度mosfet的器件结构及其制备方法 Active CN103887174B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/724,180 2012-12-21
US13/724,180 US8809948B1 (en) 2012-12-21 2012-12-21 Device structure and methods of making high density MOSFETs for load switch and DC-DC applications

Publications (2)

Publication Number Publication Date
CN103887174A CN103887174A (zh) 2014-06-25
CN103887174B true CN103887174B (zh) 2016-09-14

Family

ID=50956011

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310675735.XA Active CN103887174B (zh) 2012-12-21 2013-12-11 用于负载开关和直流-直流器件的高密度mosfet的器件结构及其制备方法

Country Status (3)

Country Link
US (3) US8809948B1 (zh)
CN (1) CN103887174B (zh)
TW (1) TWI518803B (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
CN104103693A (zh) * 2014-07-25 2014-10-15 苏州东微半导体有限公司 一种u形沟槽的功率器件及其制造方法
JP6036765B2 (ja) * 2014-08-22 2016-11-30 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
US9281368B1 (en) 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
CN104658901A (zh) * 2015-01-23 2015-05-27 无锡同方微电子有限公司 一种分裂栅型沟槽mosfet的制备方法
US9583586B1 (en) 2015-12-22 2017-02-28 Alpha And Omega Semiconductor Incorporated Transient voltage suppressor (TVS) with reduced breakdown voltage
US9640409B1 (en) * 2016-02-02 2017-05-02 Lam Research Corporation Self-limited planarization of hardmask
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10446545B2 (en) 2016-06-30 2019-10-15 Alpha And Omega Semiconductor Incorporated Bidirectional switch having back to back field effect transistors
US10056461B2 (en) 2016-09-30 2018-08-21 Alpha And Omega Semiconductor Incorporated Composite masking self-aligned trench MOSFET
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10199492B2 (en) 2016-11-30 2019-02-05 Alpha And Omega Semiconductor Incorporated Folded channel trench MOSFET
US10211333B2 (en) 2017-04-26 2019-02-19 Alpha And Omega Semiconductor (Cayman) Ltd. Scalable SGT structure with improved FOM
US10325908B2 (en) 2017-04-26 2019-06-18 Alpha And Omega Semiconductor Incorporated Compact source ballast trench MOSFET and method of manufacturing
CN109326595B (zh) * 2017-07-31 2021-03-09 联华电子股份有限公司 半导体元件及其制作方法
CN109887989A (zh) * 2017-12-06 2019-06-14 深圳尚阳通科技有限公司 一种屏蔽栅功率器件及制造方法
US10714580B2 (en) 2018-02-07 2020-07-14 Alpha And Omega Semiconductor (Cayman) Ltd. Source ballasting for p-channel trench MOSFET
CN111430353B (zh) * 2019-01-25 2023-04-18 合肥晶合集成电路股份有限公司 一种非易失性存储器及其制造方法
DE102019212646A1 (de) * 2019-08-23 2021-02-25 Robert Bosch Gmbh Grabentransistor
CN112750897A (zh) * 2019-10-29 2021-05-04 华润微电子（重庆）有限公司 沟槽型场效应晶体管结构及其制备方法
US20220052170A1 (en) * 2020-08-11 2022-02-17 Maxpower Semiconductor, Inc. Mosfet with distributed doped p-shield zones under trenches
CN112864250A (zh) * 2021-01-11 2021-05-28 江苏东海半导体科技有限公司 改善栅漏电荷的沟槽型功率半导体器件及其制备方法
CN113594255A (zh) * 2021-08-04 2021-11-02 济南市半导体元件实验所 沟槽型mosfet器件及其制备方法
CN113644027B (zh) * 2021-08-11 2023-10-03 重庆万国半导体科技有限公司 一种集成电感的沟槽功率器件及其制造方法
CN116031294B (zh) * 2023-03-27 2023-06-27 合肥新晶集成电路有限公司 半导体器件及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4941026A (en) * 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
CN101536164A (zh) * 2006-09-27 2009-09-16 巨能半导体股份有限公司 具有凹陷场板的功率金属氧化物半导体场效应晶体管
CN101542731A (zh) * 2005-05-26 2009-09-23 飞兆半导体公司 沟槽栅场效应晶体管及其制造方法
CN101621031A (zh) * 2008-06-20 2010-01-06 飞兆半导体公司 形成用于沟槽栅器件的厚的底部电介质(tbd)的结构和方法
CN102005377A (zh) * 2009-08-31 2011-04-06 万国半导体股份有限公司 具有厚底部屏蔽氧化物的沟槽双扩散金属氧化物半导体器件的制备
CN102544100A (zh) * 2010-12-14 2012-07-04 万国半导体股份有限公司 带有集成二极管的自对准沟槽mosfet

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262453B1 (en) * 1998-04-24 2001-07-17 Magepower Semiconductor Corp. Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate
GB9815021D0 (en) 1998-07-11 1998-09-09 Koninkl Philips Electronics Nv Semiconductor power device manufacture
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP4932088B2 (ja) 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
GB2381122B (en) 2001-10-16 2006-04-05 Zetex Plc Termination structure for a semiconductor device
US20080197408A1 (en) 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7973381B2 (en) 2003-09-08 2011-07-05 International Rectifier Corporation Thick field oxide termination for trench schottky device
US6977208B2 (en) 2004-01-27 2005-12-20 International Rectifier Corporation Schottky with thick trench bottom and termination oxide and process for manufacture
US7045857B2 (en) 2004-03-26 2006-05-16 Siliconix Incorporated Termination for trench MIS device having implanted drain-drift region
US7183610B2 (en) * 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
US7109552B2 (en) 2004-11-01 2006-09-19 Silicon-Based Technology, Corp. Self-aligned trench DMOS transistor structure and its manufacturing methods
TWI401749B (zh) 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
US7659570B2 (en) * 2005-05-09 2010-02-09 Alpha & Omega Semiconductor Ltd. Power MOSFET device structure for high frequency applications
TWI400757B (zh) * 2005-06-29 2013-07-01 Fairchild Semiconductor 形成遮蔽閘極場效應電晶體之方法
KR100763330B1 (ko) 2005-12-14 2007-10-04 삼성전자주식회사 활성 핀들을 정의하는 소자분리 방법, 이를 이용하는반도체소자의 제조방법 및 이에 의해 제조된 반도체소자
KR100845103B1 (ko) * 2005-12-28 2008-07-09 동부일렉트로닉스 주식회사 반도체소자의 제조방법
US7579650B2 (en) 2006-08-09 2009-08-25 International Rectifier Corporation Termination design for deep source electrode MOSFET
US7750398B2 (en) 2006-09-26 2010-07-06 Force-Mos Technology Corporation Trench MOSFET with trench termination and manufacture thereof
US7800185B2 (en) 2007-01-28 2010-09-21 Force-Mos Technology Corp. Closed trench MOSFET with floating trench rings as termination
JP4470960B2 (ja) 2007-05-21 2010-06-02 ソニー株式会社 表示装置及びその駆動方法と電子機器
US7799642B2 (en) 2007-10-02 2010-09-21 Inpower Semiconductor Co., Ltd. Trench MOSFET and method of manufacture utilizing two masks
US8042088B2 (en) 2007-12-27 2011-10-18 Cadence Design Systems, Inc. Method and system for implementing stacked vias
US8878292B2 (en) * 2008-03-02 2014-11-04 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
US9882049B2 (en) * 2014-10-06 2018-01-30 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
JP2009212369A (ja) 2008-03-05 2009-09-17 Elpida Memory Inc 半導体装置及び半導体装置の製造方法並びにデータ処理システム
US7910439B2 (en) * 2008-06-11 2011-03-22 Maxpower Semiconductor Inc. Super self-aligned trench MOSFET devices, methods, and systems
JP5693809B2 (ja) 2008-07-04 2015-04-01 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
JP2010028029A (ja) 2008-07-24 2010-02-04 Renesas Technology Corp 半導体装置および半導体装置の製造方法
US7851312B2 (en) 2009-01-23 2010-12-14 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
US8058685B2 (en) 2009-07-08 2011-11-15 Force Mos Technology Co., Ltd. Trench MOSFET structures using three masks process
KR101594031B1 (ko) 2009-08-28 2016-02-15 삼성전자주식회사 불순물이 도핑된 폴리실리콘층 내에 불순물 확산 방지층을 갖는 반도체 소자 및 이를 이용한 디램 소자
US8525255B2 (en) 2009-11-20 2013-09-03 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates having thick trench bottom oxide as termination
US7989887B2 (en) 2009-11-20 2011-08-02 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates as termination
US8575695B2 (en) 2009-11-30 2013-11-05 Alpha And Omega Semiconductor Incorporated Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode
US8247296B2 (en) 2009-12-09 2012-08-21 Semiconductor Components Industries, Llc Method of forming an insulated gate field effect transistor device having a shield electrode structure
US20110156682A1 (en) * 2009-12-30 2011-06-30 Dev Alok Girdhar Voltage converter with integrated schottky device and systems including same
US8399925B2 (en) 2010-02-12 2013-03-19 Alpha & Omega Semiconductor, Inc. Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method
US8829640B2 (en) 2011-03-29 2014-09-09 Alpha And Omega Semiconductor Incorporated Configuration and method to generate saddle junction electric field in edge termination
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8466513B2 (en) * 2011-06-13 2013-06-18 Semiconductor Components Industries, Llc Semiconductor device with enhanced mobility and method
US8803251B2 (en) 2011-07-19 2014-08-12 Alpha And Omega Semiconductor Incorporated Termination of high voltage (HV) devices with new configurations and methods
US8569765B2 (en) 2011-07-20 2013-10-29 Force Mos Technology Co., Ltd. MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures
JP5562917B2 (ja) 2011-09-16 2014-07-30 株式会社東芝 半導体装置及びその製造方法
US8772901B2 (en) 2011-11-11 2014-07-08 Alpha And Omega Semiconductor Incorporated Termination structure for gallium nitride schottky diode
US8614482B2 (en) * 2011-12-30 2013-12-24 Force Mos Technology Co., Ltd. Semiconductor power device having improved termination structure for mask saving
US8653587B2 (en) 2012-02-13 2014-02-18 Force Mos Technology Co., Ltd. Trench MOSFET having a top side drain
JP2013197551A (ja) 2012-03-22 2013-09-30 Toshiba Corp 半導体装置及びその製造方法
US9029215B2 (en) * 2012-05-14 2015-05-12 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure
US20140097491A1 (en) 2012-10-05 2014-04-10 Texas Instruments Incorporated Dielectrically Terminated Superjunction FET
TW201423869A (zh) 2012-12-13 2014-06-16 Anpec Electronics Corp 溝渠式電晶體的製作方法
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US8710585B1 (en) 2013-02-25 2014-04-29 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
US9018700B2 (en) 2013-03-14 2015-04-28 Fairchild Semiconductor Corporation Direct-drain trench FET with source and drain isolation
JP6219140B2 (ja) * 2013-11-22 2017-10-25 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4941026A (en) * 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
CN101542731A (zh) * 2005-05-26 2009-09-23 飞兆半导体公司 沟槽栅场效应晶体管及其制造方法
CN101536164A (zh) * 2006-09-27 2009-09-16 巨能半导体股份有限公司 具有凹陷场板的功率金属氧化物半导体场效应晶体管
CN101621031A (zh) * 2008-06-20 2010-01-06 飞兆半导体公司 形成用于沟槽栅器件的厚的底部电介质(tbd)的结构和方法
CN102005377A (zh) * 2009-08-31 2011-04-06 万国半导体股份有限公司 具有厚底部屏蔽氧化物的沟槽双扩散金属氧化物半导体器件的制备
CN102544100A (zh) * 2010-12-14 2012-07-04 万国半导体股份有限公司 带有集成二极管的自对准沟槽mosfet

Also Published As

Publication number Publication date
US9136380B2 (en) 2015-09-15
US9484453B2 (en) 2016-11-01
US8809948B1 (en) 2014-08-19
TWI518803B (zh) 2016-01-21
US20150380544A1 (en) 2015-12-31
CN103887174A (zh) 2014-06-25
TW201426882A (zh) 2014-07-01
US20140339630A1 (en) 2014-11-20

Similar Documents

Publication Publication Date Title
CN103887174B (zh) 用于负载开关和直流-直流器件的高密度mosfet的器件结构及其制备方法
CN103887173B (zh) 利用耗尽p-屏蔽的低输出电容的高频开关mosfet
CN103887175B (zh) 带有自对准有源接触的基于高密度沟槽的功率mosfet及其制备方法
CN103247681B (zh) 沟槽底部氧化物屏蔽以及三维p-本体接触区的纳米mosfet
CN104221153B (zh) 半导体装置
CN104347689B (zh) 双沟槽‑栅极绝缘栅双极晶体管结构
US20090315103A1 (en) Trench mosfet with shallow trench for gate charge reduction
KR102257070B1 (ko) 스페이서와 자기 정렬된 바디 콘택을 갖는 트렌치 mosfet
CN104900647A (zh) 带有自对准接触增强型插头的高密度mosfet阵列及其制备方法
CN102856385A (zh) 一种具有沟槽源极场板的Trench MOSFET晶体管及其制备方法
CN104659088A (zh) 电荷库igbt顶端结构及制备方法
CN115528115A (zh) 一种ldmos功率器件及其制备方法
US20240055498A1 (en) Semiconductor device and method for producing same
CN113659008A (zh) 具有电场钳位层的匀场器件及其制造方法和应用
CN115579398B (zh) 一种带有深接触孔的屏蔽栅功率器件
US11444158B2 (en) Semiconductor device including an anode contact region having a varied doping concentration
CN103378177B (zh) 一种具有沟槽肖特基半导体装置及其制备方法
CN203659878U (zh) 半导体器件
CN115642088A (zh) 一种沟槽型SiC MOSFET器件结构及其制造方法
CN117497568A (zh) 具有左右栅结构的sgtmos器件及其制备方法、芯片
CN117238968A (zh) 一种沟槽栅碳化硅mosfet器件及其制备方法
CN115332353A (zh) 一种阶梯状ldmos器件及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20200430

Address after: Ontario, Canada

Patentee after: World semiconductor International Limited Partnership

Address before: 475 oakmead Avenue, Sunnyvale, California 94085, USA

Patentee before: Alpha and Omega Semiconductor Inc.

TR01 Transfer of patent right