CN103843133A - 具有热熔接封装部件的引线载体 - Google Patents

具有热熔接封装部件的引线载体 Download PDF

Info

Publication number
CN103843133A
CN103843133A CN201280039935.XA CN201280039935A CN103843133A CN 103843133 A CN103843133 A CN 103843133A CN 201280039935 A CN201280039935 A CN 201280039935A CN 103843133 A CN103843133 A CN 103843133A
Authority
CN
China
Prior art keywords
fusible
pad
lead
immobilization material
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280039935.XA
Other languages
English (en)
Other versions
CN103843133B (zh
Inventor
P·E·罗根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lianda Technology Holdings Ltd
Original Assignee
Lianda Technology Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lianda Technology Holdings Ltd filed Critical Lianda Technology Holdings Ltd
Publication of CN103843133A publication Critical patent/CN103843133A/zh
Application granted granted Critical
Publication of CN103843133B publication Critical patent/CN103843133B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/4866—Iron (Fe) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48669—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48684—Tungsten (W) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48855—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/4886—Iron (Fe) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48863—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48864—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48863—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48869—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48863—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48884—Tungsten (W) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8546—Iron (Fe) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85469—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85484—Tungsten (W) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

一种引线载体，在制造期间为半导体器件提供支撑。该引线载体包括具有多个封装位点的临时支撑部件。每一个封装位点包括被多个端子垫包围的管芯附接垫。这些垫在下部分上由可熔固定材料形成。芯片被安装在管芯附接垫上，并且，接合线从芯片延伸到端子垫。垫、芯片和接合线全部被封装在模制化合物内。临时支撑部件可以被加热到高于可熔固定材料的熔化温度，并且被剥离掉，然后，可以将各个封装位点相互隔离，以提供包括用于安装在电子系统板内的多个表面安装接头的完整的封装。

Description

具有热熔接封装部件的引线载体
技术领域
下面的发明涉及用于与集成电路芯片一起使用的引线载体封装，以便电气系统中的集成电路芯片的有效互连。更具体地，本发明涉及在与集成电路组合之前和期间被制造为共用组件内的多个封装位点（site）的阵列的引线框架和其它引线载体，在隔离成用于诸如印刷电路板的电子系统板上的各个封装之前将接合线（wire bond）附接和封装在非导电材料内。
背景技术
对于与今天的半导体中的提高了的集成水平相结合的更小且更强大的便携式电子系统的需求正在推动对于具有更大数量的输入/输出端子的更小的半导体封装的需要。同时，减少消费者电子系统的所有部件的成本存在巨大的压力。四方扁平无引线（“QFN”）半导体封装系列是所有的封装类型中的最小且最成本有效的，但是，当用常规技术和材料制造时，该半导体封装系列具有显著的局限性。例如，采用QFN技术，该技术可以支持的I/O端子的数量和电性能受限制。
QFN封装P（图5至7）常规上被组装在由铜片蚀刻的区域阵列引线框架1（图1和2）上。引线框架1可以包含几十到上千个封装位点，每一个封装位点由被一行或多行的导线接合垫4（图2和5至7）包围的管芯附接垫（die attach pad）2（图1、2和5至7）构成。这些封装P部件中的全部部件都通过铜片被附接到共用框架1，以相对于引线框架1的其它部分保持封装P部件的位置并提供到所有的部件的电连接，以促进接合和焊接表面的电镀（plating）。
这些连接结构，通常被称为联结条（tie bar）3（图1、2和5至7），将引线框架1的所有部件一起短路。因此，这些联结条3必须被设置为使得它们在从引线框架1切割各个封装P的过程中可以全部与包围每一个封装P的共用短路结构6（图1和2）断开，保留每个管芯附接垫2和导线接合垫4电隔离。通常，便于切断联结条3与引线框架1的电连接的设计涉及刚好在最终封装P覆盖区之外将联结条3连接到包围每一个封装P位点的铜短路结构6（图1和2）。在切割工艺期间锯掉（沿着图2的线X）该短路结构6，从而保持联结条3在封装P的边缘处露出。
QFN引线框架1提供便于固定半导体管芯的封装P的部分，例如，封装P内的集成电路芯片7（图5至7）和可以通过接合线8（图5和6）与集成电路7连接的端子。以导线接合垫4的形式的端子还提供通过在与接合线8表面相对的表面上的焊点5（图5至7）连接到电子系统板（例如，印刷电路板）的手段。
所有的封装P部件通过金属结构与引线框架1连接的要求严重地限制了可以在任何给定的封装P轮廓中实现的引线的数量。例如，导线接合垫4可以在包围管芯附接垫2的多个行中设置，其中，每一行在离管芯附接垫2的不同的距离处。对于在导线接合垫4的最外行内部的任何导线接合垫4，连接结构的联结条3必须在外行的垫4之间被路由，从而这样的联结条3可以被延伸到封装P隔离的共用排序结构6外板（sorting structure6outboard）（沿着线X）。这些联结条3的最小尺度是这样的，只有一个可以在两个相邻的垫4之间被路由。因此，只有两行垫4可以在标准的QFN引线框架1中被实现。由于当前的管芯尺寸和引线数之间的关系，标准QFN封装被局限于约一百个端子，其中，大部分的封装P具有不超过约六十个端子。这种限制排除了多种类型的管芯使用QFN封装，否则，这些管芯将会受益于QFN技术的较小的尺寸和较低的成本。
虽然常规的QFN技术非常成本有效，但是仍然存在进一步减少成本的机会。在集成电路芯片7通过接合线8被附接和连接到外部的引线接合垫4之后，多个封装P的组装的引线框架1完全被环氧模制化合物9（图6和7）封装，例如，在转移模制工艺中。因为引线框架1主要是从前向后敞口的，所以在组装工艺之前将高温带T层施加到引线框架1的背面，以在模制期间限定每一个封装P的背平面。因为该带T必须能承受高温接合和模制工艺，而没有来自热工艺的负面影响，所以该带相对昂贵。施加带T、去除带T和去除残余粘合剂的工艺会给处理每一个引线框架1增加显著的成本。
从引线框架1切割各个封装P的最常用的方法是锯切（沿着图2的线X）。因为除了切割环氧模制化合物9之外，锯还必须去除刚好在封装P轮廓之外的所有的短路结构6，所以该工艺基本上较慢并且刀片寿命相当短，好像只有模制化合物9被切割。因为短路结构6不被去除直到切割工艺为止，所以这意味着，管芯不能被测试直到分割后。与能够测试其中每一个封装P处于已知的位置的整个条相比，处理数千个小型封装P并确保每一个封装以正确的取向被呈示给测试者昂贵得多。
被称为冲压分割（punch singulation）的基于引线框架1的工艺在一定程度上解决了与锯分割相关联的问题，并且允许在引线框架1条中进行测试，但是，通过将引线框架1的利用率削减到小于锯分割的引线框架1的利用率的50%，实质上增加了成本。冲压分割对于每一个基本引线框架设计也施加了专用模制工具的要求。被设计用于锯分割的标准引线框架1对于同一尺寸的所有的引线框架1使用单模帽。
在锯分割和冲压分割封装P二者中，联结条3被留在完整的封装P中，并且表示不能被去除的电容和电感的寄生元件。这些现在多余的金属片显著地影响完整封装P的性能，从而排除了许多高性能集成电路芯片7和应用采用QFN封装P。此外，这可能相当有价值的多余金属的成本可能是很大的，并且被QFN封装工艺浪费
对于消除蚀刻的引线框架的限制的QFN型衬底，提出了几个概念。在这些概念中的一个是通过电镀在牺牲载体上沉积封装部件阵列的工艺。载体首先通过电镀抗蚀剂来被构图，并且，通常是不锈钢的载体被轻蚀刻，以提高附着力。然后，用金和钯对条带进行电镀，以产生粘结/阻挡层，接着，用Ni对条带进行电镀，达到约六十微米厚。用电镀Ag层对Ni凸块的顶部进行抛光，以促进引线接合。在条带被组装和模制之后，载体带被剥离掉以留下封装管芯片，其可以在片中被测试并以比常规的引线框架高的速率和产率被分割。该电镀方法消除了与封装内的连接的金属结构相关联的所有的问题，并且允许非常精细的特征。但是，与标准蚀刻的引线框架相比，该电镀工艺导致非常昂贵的条带。该方法在Fukutomi等人的美国专利No.7,187,072中被描述了。
另一种方法是蚀刻的引线框架工艺的修改，其中，前侧图案被蚀刻为引线框架的厚度的约一半，并且，引线框架条带的背侧被完整不变地留下，直到模制工艺完成之后。一旦模制完成，背侧图案被印刷，引线框架被蚀刻，以去除除了导线接合垫和管芯座（die paddle）的背侧部分以外的所有的金属。该双重蚀刻工艺消除了与封装内的连接的金属结构相关的所有的问题。该双重蚀刻引线框架的成本小于电镀版，但是仍然比标准蚀刻引线框架昂贵，并且，蚀刻和电镀工艺是环境上不希望的。
特别是当封装被经受冲击负荷时（例如，当其中合并了封装的电子器件被掉下并撞击到硬表面时），引线框架封装的集成电路的一个故障模式是引线接合垫4变成从与其耦接的接合线8断开。导线接合垫4可以在与周围的氧化模制化合物稍微分离的同时保持被安装到印刷电路板或其它的电子系统板，从而允许接合线8从导线接合垫4切断。因此，存在对于（特别是在经受冲击负荷时）更好地保持整个封装内的导线接合垫4的引线载体封装的进一步的需要。
由Redwood City,California的Eoplex,Inc.开发的本领域中已知的另一种引线载体被称为具有印刷成型封装部件的引线载体，并且是通过引用全部合并于此的美国专利申请No.13/135,210的主题。具有印刷成型封装部件的这种引线载体被设置有以多封装引线载体的形式的单独的封装位点的阵列（例如，参见用于一般地描述该引线载体的一种形式的图3和4）。通常开始是银粉的烧结材料被放置在由诸如不锈钢的耐高温材料形成的临时层上。形成临时层的不锈钢或者其它材料在其被加热到烧结温度时支撑烧结材料。
在以管芯附接垫和端子垫的形式的优选地相互电隔离（而不是通过临时层）的分离结构中，烧结材料被置于临时层上。一个或多个端子垫包围每一个管芯附接垫。每一个管芯附接垫被配置为具有被支撑在其上的集成电路或其它半导体器件。接合线可以从管芯附接垫上的集成电路被路由到包围每一个管芯附接垫的单独的端子垫（例如，参见图8）。然后，可以施加封装管芯附接垫、集成电路、端子垫和接合线的模制化合物（例如，参见图9和10）。只有在管芯附接垫和端子垫的部分下面限定的表面安装接头保持未封装（图10），因为它们与临时层相邻。
一旦引线载体的模制化合物硬化了，临时层就可以从引线载体的剩余部分剥离掉，留下具有各个管芯附接垫和相关的集成电路的多个封装位点，端子垫和接合线全部被嵌入在共用模制化合物内。然后，可以通过沿着封装位点和通过表面安装接头被安装到电子系统板或其它支撑体的表面之间的边界进行切割来将各个封装位点相互切割开。
因为引线载体的封装位点和封装位点内的各个垫均相互（而不是通过临时层）电隔离，所以这些独立垫在临时层上的同时被测试电连续性。在去除临时层之后，且在分割成单独的封装之前，可以测试各种电性能特性。此外，在利用已知的利用QFN封装的测试设备或其它的测试设备在引线载体上将这种封装与相邻的封装隔离之后，可以测试这种封装。
另外，包括管芯附接垫和端子垫的引线载体的每一个垫优选地具有在其周边周围的边缘，这些周边被配置为与模制化合物略机械接合。特别地，这些边缘可以以悬垂的方式逐渐变细，或者以悬垂的方式形成台阶（step），或者以另外的方式被配置为使得至少每一个边缘的与其底部隔开的一部分比每一个边缘的更靠近每一个边缘的底部的部分横向地延伸得更远。因此，模制化合物一旦被硬化了就将垫牢固地锁定到模制化合物中。这样，特别是当将临时层剥离掉时，这些垫抵抗从接合线脱离或者以另外的方式与模制化合物脱离，并将整个封装保持为单一整体封装。
发明内容
采用本发明，一种引线载体以多封装的引线载体的形式被设置有单独的封装位点阵列。每一个封装位点包括至少一个管芯附接垫和至少一个端子垫，但是，通常包括包围每一个管芯附接垫的多行的多个端子垫。这些垫被附着到由与半导体组装工艺的要求相兼容的诸如钢或钢合金或不锈钢的材料形成的临时支撑层。将管芯附接垫和导线接合垫固定到临时层的装置是可熔固定材料。可熔固定材料被选择为具有高于半导体组装操作常用的温度的熔点，但是将在比会对用于组装工艺中的半导体器件或者任何材料产生损坏的任何温度低的温度处熔化（或者，至少部分地开始熔化）。
可熔固定材料是将保护与其附接的表面免受氧化和腐蚀并且促进焊料在延长的时间段内与所述表面润湿（wet）的可熔固定材料。可熔固定材料可以从包括锡和锡与其它金属的合金、金合金、铅合金、以及具有150℃和400℃之间的熔融温度的其它金属和金属合金的组中被选择。可熔固定材料的另一种选择是，它是适合于保护相邻表面免受氧化和腐蚀并且通常具有类似的熔融温度的范围内的聚合物组合物或其它组合物（例如，石蜡）。
每一个管芯附接垫被配置为具有在其上被支撑的至少一个半导体（例如，集成电路芯片）。接合线可以从管芯附接垫上的半导体被路由到与该管芯附接垫邻近排列的单独的端子垫。然后，可以应用封装管芯附接垫、半导体、端子垫和导线接合垫的模制化合物。只有在管芯附接垫和端子垫的部分下面限定的表面安装接头保持未封装，因为它们与临时支撑层相邻。
一旦模制化合物被硬化了，结果就是通过可熔固定材料被附接到临时支撑层的完全被封装但还没有完全分开的半导体器件的片材形式的阵列。通过将临时层加热到可熔固定材料的熔点并且将临时层从封装的半导体器件的阵列剥离掉（或者，以另外的方式去除），将临时层与封装的半导体器件的阵列分离。可熔固定材料的涂层被保留在表面安装接头上，从而保护它们免受氧化或腐蚀，并且，促进表面安装组装工艺期间的良好的焊料润湿。
在去除临时层之后，封装的半导体器件的阵列中的单独的半导体器件保持以连续的片材相互物理附接，但是，每一个封装的半导体器件（以及每一个封装的半导体器件内的各个垫）除了通过半导体（例如，集成电路芯片）自身以外电隔离，并且，封装端子被露出。该配置允许通过使用一台指甲型探测器或分步重复型探测器在连续的阵列片材中的同时测试半导体器件中的单独的半导体器件。在封装的半导体器件的阵列中的单独的半导体器件之间通过锯进行分割产生多个完全封装且测试过的半导体器件，准备好用于表面安装组装工艺。
在可熔固定材料上方的端子垫和管芯垫的部分由与用于半导体管芯附接、金或铜的热声波引线接合和SMT焊接的常规工艺相兼容的高度导电的金属构成。一种优选的金属是铜或者铜的合金，但是，诸如镍、铁、钨、钯、铂、金、银和铝的金属和金属合金也是可以的。
另外，包括管芯附接垫和端子垫的每一个垫优选地具有在其周边周围的边缘，这些周边被配置为与模制化合物略机械接合。特别地，这些边缘可以以悬垂的方式逐渐变细，或者具有突起的鳍片（fin），或者以另外的方式被配置为使得至少每一个边缘的与其底部隔开的一部分比每一个边缘的更靠近每一个边缘的底部的部分横向地延伸得更远。因此，模制化合物一旦被硬化了就将垫牢固地锁定到模制化合物中。这样，这些垫抵抗从接合线脱离或者以另外的方式与模制化合物脱离，并且将整个封装保持为单一整体封装。
本发明还限定一种用于形成多个半导体封装位点的引线载体的方法。该方法通过在可溶解固定材料的上方供应形成管芯附接垫和端子垫的部分的材料的供体片材来开始。该片材被称为供体片材。将可去除的模子施加到该供体片材的下表面安装侧。在一个实施例中，通过首先将施加可光成像材料到供体片材的下表面来形成该模子层。然后，将光掩模放置在可光成像材料的部分上。然后，利用光蚀刻工艺在可光成像材料中形成凹部。
一旦将该模子放置在合适的位置中，就将可熔固定材料放置到模子层中的这些凹部中。放置这种可熔固定材料的一种选择是利用电镀或无电沉积。光掩模中的图案通常将对应于每一个封装位点的管芯附接垫和端子垫的期望的位置。因此，在期望限定供体片材上的每一个管芯附接垫和端子垫的下表面的地方施加可熔固定材料。
接下来，例如，使用化学蚀刻工艺来蚀刻供体片材的下表面。该蚀刻工艺将模子材料的剩余部分蚀刻掉，并且至少部分地蚀刻到供体片材中。优选地，该蚀刻深度近似为供体片材的厚度的一半，实际上稍微多于供体片材的厚度的一半，并且，可任选地，可以涉及完全蚀刻通过供体片材。蚀刻化学或其他方法可以被选择，使得形成可熔固定材料的材料基本上不被蚀刻材料或工艺蚀刻，或者，某种形式的抗蚀剂可以被印刷或以其他方式施加到可熔固定材料，以使得它在该供体片材蚀刻工艺期间抵抗去除。
然后，在其下表面上包含可熔固定材料的蚀刻的供体片材被附接到临时支撑部件。优选地，通过将供体片材可熔固定材料加热到其可熔固定材料至少开始熔化的温度来进行该附接，从而它可以牢固地附接到临时支撑部件。
然后，对供体片材的上表面执行选择性的蚀刻工艺。在一个实施例中，该蚀刻工艺可以涉及首先在供体片材的上表面上施加可光成像材料的上层。然后，可以与光蚀刻工艺一起使用上光掩模，以选择性地去除可光成像材料的部分。然后，施加某一形式的供体材料抗蚀材料，该供体材料抗蚀材料填充上可光成像材料的光蚀刻掉的部分。可以使用用于施加该抗蚀剂的其它方法，例如，将抗蚀剂直接印刷施加到供体片材的上表面。然后，进行蚀刻工艺，该蚀刻工艺将与其上表面相邻的供体片材的部分蚀刻掉。在一个实施例中，这些蚀刻区域与供体片材的下表面中的蚀刻凹部对准。这样，通过该第二蚀刻步骤，管芯附接垫和端子垫相互完全隔离。
如果抗蚀材料不是导电的或者另外与由供体片材形成的垫的上表面的期望特性不兼容，则可以从上表面去除抗蚀材料。诸如集成电路的半导体然后可以被安装在管芯附接垫上，并且，接合线可以被连接到半导体器件和端子垫的上表面。最后，接合线、半导体器件和垫被基本上不导电的材料封装，并且，例如，通过剥离，去除临时支撑层。通过施加足以稍微熔化可熔固定材料的热，可以帮助临时支撑层的该去除，从而可以容易地从临时支撑部件去除它，在临时支撑部件和引线框架的其它部分之间具有或不具有剥离动作。去除了临时支撑部件的引线载体然后准备好用于测试和切割成单独的封装，这些封装用于通常通过表面安装技术安装到其中要利用半导体封装的整个电子器件内的电子电路的其它部分。
附图说明
图1是简化类型的QFN引线框架的透视图，其示出现有技术的引线框架技术。
图2是在图1中示出的一部分的细节的透视图，带有指示切割线所遵循以从引线框架分离各个封装位点的地方的虚线。
图3是根据本发明的引线载体的透视图，在引线载体上具有多个单独的封装位点，并且，该引线载体被安装在临时支撑部件上。
图4是在图3中示出的一部分的细节的透视图，并且进一步示出在集成电路芯片的安装、接合线的附接和封装在模制化合物内之前的每一个封装位点的细节。
图5是示出放置集成电路芯片和接合线的现有技术的QFN封装的透视图，并且，以虚线示出如何相对于封装内的其它导电结构来放置封装材料。
图6是与在图5中示出的透视图类似的透视图，但是，封装模制化合物被放置在合适的位置，并且，封装模制化合物的部分被切掉，以揭露封装的内部结构。
图7是与在图6中示出的透视图类似的透视图，但是，从下面观看，以示出可用于将封装表面安装在电气系统内的电子系统板或其它界面上的焊料接头。
图8是在放置集成电路芯片和接合线之后的本发明的引线载体上的各个封装位点的透视图，并且，以虚线示出模制化合物的位置。
图9是类似于图8的透视图，但是，模制化合物被示出为放置在封装内的封装导电结构中的合适的位置，并且，模制化合物的部分被切掉，以揭露封装的内部细节。
图10是从封装的下方观看的透视图，并且，示出根据本发明的封装的表面安装接头。
图11至25是根据本发明的形成半导体支撑封装的工艺中的步骤的全剖视图，并且示出每一个封装的各种层和示例性几何结构。
图26是具有可替换的垫的可替换的引线载体的透视图，所述垫被示出具有不同的边缘轮廓，以通过包围封装模制化合物来表现出不同的接合性质，并且，以透视的方式示出根据本发明的各个垫的配置。
图27是另外的示例性的可替换的垫几何结构变型的全剖视图。
具体实施方式
参照附图，在各附图中，相似的附图标记表示相似的部分，附图标记110（图21）针指向优选实施例的成品引线载体。该引线载体110在其上包括临时支撑部件120，并且在去除临时支撑部件120之后也被实现为最终封装组件110’。
引线载体110在某些方面上类似于上文和美国专利申请No.13/135,210的主题中描述的引线载体10（图3、4和8至10），该美国专利申请通过引用全部合并在此。该相关的引线载体10（图3和4）被配置为在用于制造包括集成电路芯片60的多个封装100（图9和10）的临时支撑部件20上支撑多个封装位点12，并且提供大量的输入和输出到集成电路芯片60中。
实际上，具体地参照图3、4、8和9，针对本发明的引线载体110所相关的封装100和引线载体10描述基本细节。引线载体10包括诸如不锈钢的薄平面耐高温材料的临时支撑部件20。多个管芯附接垫30和端子垫40被在封装位点12处排列在临时支撑部件20上，其中，多个端子垫40包围每一个管芯附接垫30。
集成电路芯片60被安装在管芯附接垫30上（图8和9）。接合线50被联接在芯片60和端子垫40上的输入输出端子之间。除了限定封装100的下侧的表面安装接头90部分（图10）以外，包括管芯附接垫30、端子垫40、接合线50和芯片60的整个封装100被封装模制化合物70内。模制化合物70通常被施加到引线载体10，以包围封装位点12中的每一个。随后通过切割模制化合物70来进行每一个封装100的隔离，以由原始引线载体10提供多个封装100。
具体地参照图1和2，为了与引线载体10的细节比较和形成对照，描述“四方扁平无引线”（QFN）类型的现有技术的引线框架1的细节。在示出的实施例中，QFN引线框架1是蚀刻的导电材料的平面结构。该蚀刻的导电材料被蚀刻成不同的管芯附接垫2和导线接合垫4，管芯附接垫2和导线接合垫4中的每一个通过联结条3被联接到共用短路结构6。该整个蚀刻的QFN引线框架1被安装在模制带T上，从而环氧模制化合物9可以被施加到引线框架1并封装垫2,4（图5至7）。
在这种封装之前，芯片7的集成被安装在管芯附接垫2上。接合线8被放置在导线接合垫4和芯片7上的输入/输出端子之间。然后，模制化合物9可以全部封装垫2,4以及芯片7和接合线8。通过带T防止模制化合物封装垫2的下侧。在模制化合物9已硬化之后，可以将带T剥离掉，使得焊料接头5（图7）呈现于引线框架1的下侧上。最后，单独的QFN封装P通过切割（沿着图2的切割线X）隔离，以将每一个封装P与整个引线框架1隔离。
重要的是，应该注意，从管芯附接垫2和导线接合垫4延伸的联结条3的部分保持在封装P内。这些联结条3的一些部分实际上从封装P的边缘延伸出（图6和7）。此外，共用短路结构6（图1和2）不是任何封装P的部分。因此，共用短路结构6通常被浪费。此外，在每一个封装P内的联结条3的剩余部分并不提供任何有益目的，因此，也在封装P内被浪费。这样的联结条3残余物也可以对封装P和封装P内的芯片7的性能有负面的影响。例如，从封装P的模制化合物9的边缘延伸出的联结条3的一部分对不希望的短路或电磁干扰和“噪音”提供机会，从而某些电子应用不能被现有技术的QFN封装P很好地服务。即使当这样的现有技术的QFN封装P是合适的，与嵌入在封装P内的联结条3和共用短路结构6相关联的浪费是不希望的。此外，当利用已知的现有技术QFN引线框架1和封装P技术时，条T不能被重复使用，并且是另一种浪费的开支（特别地，考虑带T的不可回收性和潜在的危险性）。
参照图3和4，根据示例性实施例，描述引线载体10以及临时支撑部件20和垫30,40的具体细节。该示例性实施例相对于典型的优选实施例被明显地简化，其中每一个封装位点12仅仅示出包围每一个管芯附接垫30的四个端子垫40。通常，这种端子垫40将以包围每一个管芯附接垫30的几十个或潜在地甚至数百个的数量存在。还可以设想到的是，少至一个端子垫40将被设置在与每一个管芯附接垫30相邻。这种端子垫40将通常以多行的形式存在，所述多行包括与管芯附接垫30最靠近的最内行、端子垫40的最远离管芯附接垫30的最外行、以及在端子垫40的最内行和最外行之间的潜在的多个中间行。
引线载体10是平面结构，该平面结构被制造为包括多个封装位点12，并且在其制造期间支撑这些封装位点12，通过与集成电路芯片60（或者其它的半导体器件，例如二极管或晶体管）和接合线50（图8和9）的测试和集成，以便于最终制造多个封装100（图9和10）。引线载体10包括临时支撑部件20。该临时支撑体20是耐高温材料（最优选地，不锈钢）的薄平板。该部件20包括顶表面22，在顶表面22上制造引线载体10的其它部分。临时支撑部件20的边缘24限定临时支撑部件20的周边。在该示例性实施例中，该边缘24通常是矩形的。
该临时支撑部件20优选地充分薄，使得它可以稍微弯曲，并且便于在封装位点12和引线载体10处完全制造封装100（图8至10）之后从引线载体10剥离去除临时支撑部件20（或者，反之亦然）。
临时支撑部件20的顶表面22在其上支撑多个封装位点12，其中，每一个封装位点12包括至少一个管芯附接垫30和与每一个管芯附接垫30相邻的至少一个端子垫40。切割线Y通常限定每一个封装位点12的边界（图4）。
管芯附接垫30和端子垫40表现出不同的几何结构和位置，但是，优选地，由相似材料形成。特别地，这些垫30,40优选地由烧结材料形成。根据优选实施例，这些垫30,40开始为与悬浮组分混合的导电材料（优选地，银）的粉末。该悬浮组分通常用来向银粉末提供粘贴或其它可流动特性的一致性，使得银粉末可以被最佳地处理并操纵，以表现出垫30,40的期望的几何结构。
该悬浮组分和银粉末或其它导电金属粉末的混合物被加热到该金属粉末的烧结温度。悬浮组分煮沸成气体并从引线框架10排出。金属粉末被烧结成具有管芯附接垫30和端子垫40所期望的形状的整体块。
临时支撑部件20被配置为具有热特性，使得它直到形成垫30,40的导电材料的烧结温度保持其柔韧性以及期望的强度和其它性质。通常，该烧结温度接近被烧结为垫30,40的金属粉末的熔点。
具体地参照图8至10，根据一个示例性实施例，描述在各种封装位点12处的引线载体10上进一步制造之后的每一个封装100的细节。集成电路芯片60通常被安装在管芯附接垫30上，其中，集成电路芯片60的下侧与管芯附接垫30电耦接。这种电耦接可以对于芯片60的“接地”是公共的，或者，对于芯片60的一些其它的参考是公开的，或者，可以在利用封装100的整个电气系统内具有某一其它的电气状态。芯片60包括限定与管芯附接垫30的顶侧32接触的其下部分的基体62。芯片60的上表面64被设置为与基体62相对。该上表面64具有可以被端接于接合线50的一端的多个输入输出结（图8和9）。
一条接合线50优选地被端接于芯片60上的每一个输入输出结与周围的端子垫40之间。因此，每一条接合线50具有与端子端相对的芯片端。使用已知的接合线50端接技术，例如，与QFN引线框架一起使用的那些技术，这些接合线50被耦接在芯片60和端子垫40之间。
为了完成封装100形成工艺，模制化合物70在引线载体10上流动并被允许以这样的方式硬化，即完全封装管芯附接垫30、端子垫40、接合线50和集成电路芯片60中的每一个。该模制化合物70可以相对于临时支撑部件20的顶表面22模制。因此，每一个垫30,40的表面安装接头90在去除临时支撑部件20之后保持露出（图10）。模制化合物70通常是在第一温度处为流体形式但是在被调节到第二温度时会硬化的类型。
模制化合物70由基本上不导电的材料形成，使得垫30,40相互电隔离。模制化合物70在垫30,40之间流动，以提供倾向于在整个封装100内与模制化合物70一起保持垫30,40的联锁。这种联锁阻止端子垫40与接合线50脱离。这种脱离倾向性在从引线载体10去除临时支撑部件20时首先被抵抗，并且，当封装100被使用并且可能经受冲击负荷时再次有益地抵抗，否则，所述冲击负荷可能将端子垫40从封装100脱离。这些联锁可以具有与垫30,40的边缘相关联的上述的各种不同形状。
在模制化合物70的硬化之后，封装100以阵列的形式被设置在引线载体10上，其中，每一个封装100包括与底部104相对的顶部102，并且具有周边侧面106。有益地，不要求周边侧面106具有从其延伸的任何导电材料，这与必须具有从其延伸的任何导电材料的现有技术的QFN封装P（图6和7）形成对照。
具体参照图11至25，根据本发明的优选实施例，描述引线载体110和其后的各个封装半导体器件的制造方法的细节。引线载体110开始仅仅为供体片材112。供体片材112具有组装表面114，诸如集成电路芯片160（图22）的半导体器件可以被安装在该组装表面114上，并且，诸如接合线150的互连结构可以被附接到该组装表面114上（图23）。SMT安装表面116被设置在供体片材112的与组装表面114相对的一侧。该安装表面116通常被称为下表面，并且，组装表面114通常被称为上表面。
供体片材112提供形成引线载体110的管芯附接垫130和端子垫140的导电材料的至少一部分，通常提供该导电材料的大部分，最优选地提供该导电材料的基本上全部。可以形成供体片材112的材料包括铜、铜的合金，包括镍、铁、钨、钯、铂、金、银和铝的金属和金属合金。该材料被选择为高度导电的并且与用于半导体管芯附接、金或铜的热声波引线接合和SMT焊接的常规工艺相兼容。
可熔固定材料119被选择性地施加到其中管芯附接垫130和端子垫140所处的供体片材112的部分。可以提供可熔固定材料112的材料包括锡和锡与其它金属的合金、金合金、铅与其它金属的合金、以及具有150℃和400℃之间的熔融温度的其它金属和金属合金。作为另一种选择，可熔固定材料可以是保护供体片材112的相邻部分免受氧化或腐蚀且具有相似的温度范围的聚合物组合物或者其它材料（即，石蜡）。
可熔固定材料119可以以各种不同的方式被施加到供体片材112的安装表面116。例如，可熔固定材料可以作为粉末与某一形式的至少稍有挥发性的粘结剂液体一起被提供，以形成可流动材料。这种可流动材料然后可以例如，通过印刷操作，例如，丝网印刷操作或者喷雾印刷操作被施加。可替换地，某一形式的模子可以先被施加，然后，以可流动形式的可熔固定材料可以流入模子中。作为另一种可替换的方案，可以通过将可熔固定材料加热到其熔解成液体使得它可以流动的温度来使得该可熔固定材料流动。如果需要的话，可以利用要求流动性特性的某一印刷技术，使得可熔固定材料可以被施加在供体片材112的安装表面116上的期望位置处。
在该示例性实施例中，可熔固定材料119如下被施加到安装表面116。最初，一层可光成像材料118被施加到供体片材112的安装表面116（图12）。接下来，将光掩模115放置为与可光成像材料118相邻（图13）。在该实施例中，光掩模115是这样的类型，当光蚀刻辐射源被施加到可光成像材料118时，该光掩模115导致与放置光掩模115的地方相邻的可光成像材料118的去除。作为可替换的方案，光掩模115可以限定在施加光辐射源时防止材料被去除的位置，在这种情况中，与图13中示出的光掩模相比，该光掩模115将具有“负（negative）”的几何结构。在本实施例中，可光成像材料118是这样的类型，即，如果不被光掩模115覆盖的话，它被光辐射硬化。作为可替换的方案，可光成像材料118可以是这样的类型，即，在经受光辐射时，导致可光成像材料118被去除。
在本实施例中，显影的可光成像材料117在经受光辐射之后保留在供体片材112的安装表面116上。该显影的可光成像材料118被充分地硬化，使得它可以充当安装表面116上的模子，从而，可熔固定材料119可以被放置在该模子内的期望的地方。图14示出在放置可熔固定材料119之前的显影的可光成像材料117。
图15示出在可熔固定材料119被放置入显影的可光成像材料119中的开口或者其它形式结构中以将可熔固定材料119放置成与供体片材112的安装表面116相邻之后的供体片材112。更优选地，这样的放置通过将可熔固定材料119电镀在供体片材112的安装表面116上来发生。还可以使用其它形式的沉积，例如，无电沉积。可替换地，如上所述，通过使可熔固定材料119具有可流动特性，例如，通过将它加热到高于使得它是可流入模子中的液体的其熔点，可以将可熔固定材料119放置在显影的可光成像材料117中的开口，或者，可熔固定材料119可以是采用适当的溶剂的粉末的形式，使得可熔固定材料可以诸如为糊的形式流入该模子的开口中。然后，例如，通过允许可熔固定材料119冷却并返回到固态来允许可熔固定材料119硬化，或者，允许可流动载体或溶剂组分挥发或以另外的方式去除，留下与供体片材112的安装表面116相邻的作为固体的可熔固定材料119。
在形成引线载体110的工艺中的下一个步骤涉及蚀刻掉在引线载体110上的与每一个封装位点相关联的各个端子垫140和管芯附接垫130之间的供体片材112的部分。在本实施例中，通过蚀刻工艺，最优选地，通过化学蚀刻工艺，执行中间材料的这种去除。该蚀刻工艺涉及在端子垫140和管芯附接垫130之间形成下蚀刻凹部122。
为了将该下蚀刻凹部122基本上约束到这些中间空间，可以选择不会被蚀刻到可熔固定材料119中的蚀刻材料，使得可熔固定材料119自身充当抗蚀材料。作为可替换的方案，可以在所述蚀刻步骤之前在可熔固定材料119的最下表面上将某一其它形式的抗蚀材料施加到可熔固定材料119。选择能够蚀刻入形成供体片材112的材料中的蚀刻材料。因此，下蚀刻凹部122延伸到供体片材112中，最优选地，延伸超过供体片材112的厚度的一半（图16）。通过避免完全蚀刻通过供体片材112，对于引线载体110的全部封装位点，供体片材112保持作为连续的片材。可以设想到，下蚀刻凹部122可以完全延伸通过供体片材112，并且，支撑片材可以临时地接合到供体片材112的组装表面114。
在相邻的垫130,140之间形成下蚀刻凹部122之后，包括可熔固定材料119的供体片材112被安装在临时支撑部件120上（图17）。在优选实施例中，该安装工艺通过如下来实现：将可熔固定材料119至少加热到可熔固定材料119的熔化温度，从而允许可熔固定材料119粘附到临时支撑部件120。该熔化温度可以是可熔固定材料119可烧结的温度，例如，各个材料颗粒的表面正好开始熔解使得可以促进粘结到相邻的结构的温度。作为可替换的方案，可熔固定材料119的全部或部分熔解可以实现，其后，可熔固定材料119被冷却硬化并粘结到临时支撑部件120。
一旦供体片材112和相关的可熔固定材料119已被牢固地附接到临时支撑部件120，就可以发生管芯附接垫130和端子垫140的进一步的形成。特别地，如图18至20所示，可以遵循与上面参照图13至16描述的工艺相似的工艺，以蚀刻掉管芯附接垫130和端子垫140之间的供体片材112的剩余部分。在至少一个方面中，形成上蚀刻凹部126的该工艺不同于上述的工艺。特别地，对于组装表面114，通常不需要可熔固定材料119。因此，不是将可熔固定材料119放置入得自于利用光掩模125的上可光成像材料128中形成的开口中，相反，将抗蚀剂129放置入这些凹部中。
然后，每当不提供抗蚀剂129时上蚀刻凹部126可以由与蚀刻材料接触以形成上蚀刻凹部126的供体片材112的组装表面114形成。最终结果（图20）是不再电连接在一起且被安装在临时支撑部件120上的单独的端子垫140和管芯附接垫130。抗蚀剂129可以为某一形式的与蚀刻材料不发生化学反应的相对低熔点温度的聚合物化合物的形式。然后，例如，通过加热到足以将抗蚀剂129熔解或汽化掉，可以去除抗蚀剂129（图21）。如果抗蚀剂129是导电的且适用于与接合线150或集成电路芯片160形成接合，则可以设想到，抗蚀剂129可以保留而不被去除。
在形成上蚀刻凹部126之后垫130,140的一个重要属性是大致在限定下蚀刻凹部122和上蚀刻凹部126的最深部分的平面中形成侧面鳍片124。这些鳍片124通过在模制化合物170和垫130,140之间产生机械联锁接头来帮助将垫130,140牢固地保持在模制化合物170内（图24和25）。因此，不是必须具体地提供逐渐变细或者以另外的方式形成为产生侧面鳍片124或其它机械联锁特征的模制表面，自然地得自于两个蚀刻凹部122,126的鳍片124提供仅仅作为蚀刻工艺的结果的鳍片124或者蚀刻凹部的大致配置，所述蚀刻凹部在其最深部分处具有圆形的轮廓。
在这一阶段，图21示出以基本上完整的形式的引线载体110，其与诸如引线载体10（图3和4）的其它的引线载体一起准备好用来形成稍后要分离到单独的半导体封装中的半导体封装110’（图25）的组件。引线载体110具有多个封装位点，每一个封装位点具有全部被安装在临时支撑层120上的至少一个管芯附接垫130和至少一个端子垫140。可熔固定材料119被放置在形成垫130,140的供体片材112的部分和临时支撑层120之间的合适的位置。该可熔固定材料既将垫130,140保持到临时支撑层120，又保护垫130,140的下安装表面116免受氧化或腐蚀，直到它们准备好用于（在分离成单独的封装之后）表面安装到其它电子器件。可熔固定材料不仅保护垫130,140，还可以通过施加热以（至少部分地）熔解可熔固定材料119来导致容易地剥离临时支撑层120。
如图22至24所示，集成电路芯片160或其它的半导体器件被安装在管芯附接垫130上，并且，利用接合线150将集成电路芯片160连接到端子垫140。然后，提供模制化合物170，该模制化合物170具有基本上不导电的特性，以封装除了由可熔固定材料119限定的每一个垫130,140的最下部以外的垫130,140、接合线150和集成电路芯片160的所有部分。
最后，去除临时支撑部件120。这种去除可以通过如下来进行：用除了临时支撑部件120以外的最终封装组件110的比临时支撑部件120更加柔韧且诸如通过侧面鳍片124锁定在一起的部分来施加剥离力，使得当施加该剥离力时，最终封装组件110’从临时支撑部件120去除干净。这样的去除可以通过如下方式来促进：将整个组件加热到可熔固定材料119的熔解温度，以便于这种去除。当利用这种加热时，可以设想到以除了剥离动作以外的方式去除临时支撑部件120，或者，可以同时利用加热和剥离，以更有效地实现从临时支撑部件120分离掉。没有临时支撑部件120的剩余的引线载体110’包括多个封装位点，并且准备好用于测试和/或分离成单独的半导体器件封装。最终的封装组件110’包括覆盖垫130,140的可熔固定材料119，使得它们被保护以免受氧化或腐蚀，在该组装状态中，对于每一个封装位点，可以对封装组件110’基本上进行全面的测试。组件110’也可以在该状态中被保存而不用担心氧化或腐蚀，并且准备好用于进一步的处理。类似地，在将组件110’分离成各个封装之后，每一个封装的垫130,140被保护以免受氧化和腐蚀，并且可以被单独地测试和保存，直到这些封装准备好表面安装或以另外的方式附接到电子电路。
具体地参照图26，以进一步观看其几何结构的透视的方式在临时支撑部件120上示出垫130,140。图26还示出通常被称为“蘑菇”附接垫210的可替换的附接垫。采用蘑菇附接垫210，上蚀刻凹部126与下蚀刻凹部122对准，但是具有更窄的形式。这样，供体片材112的大部分保持与组装表面114相邻，而不是保持与安装表面116和内置的大的悬垂结果（built-in larger overhang result）相邻。这种布置提供与模制化合物170的更大程度的机械锁定，并且在组装表面114上提供更大的表面面积，例如，用于在其上支撑半导体器件，或者用于提供接合线150可以与其附接的表面。
具体地参照图27，描述可替换的下蚀刻凹部232和上蚀刻凹部236的定位和宽度的进一步的变型，以便提供关于侧面鳍片234的变型。在一个示出的实施例中，以悬垂附接垫（overhang attach pad）220的形式提供第二可替换的附接垫。采用悬垂附接垫220，在一侧提供悬垂件，但是，在相对的一侧提供标准侧面鳍片234。
在图27中还示出以偏移附接垫230的形式的第三可替换的附接垫。采用该第三可替换的偏移附接垫230，组装表面相对于安装表面被偏移到一侧。图27还以全剖视图示出蘑菇附接垫210。
最后，图27示出第四可替换的锥附接垫240，该锥附接垫240通过使上蚀刻凹部236比下蚀刻凹部232宽来具有比其安装表面小的组装表面，并且，其特征仍然是其上的侧面鳍片234。可以提供不同的附接垫210,220,230,240的各种组合以及其它的变型，以为诸如在引线载体110上制造的半导体封装内的垫130,140的垫提供期望的特定几何结构。例如，可能期望在组装表面114和在安装表面116上具有较大的管芯附接垫130，以容纳较大的集成电路芯片160的尺寸，同时最少化安装表面上所需的空间，例如，节约其它的电子器件平台上的空间，其中在安装表面上半导体封装器件要被表面安装到其它的电子器件。偏移附接垫在如下情况中可能是有益的：重要的是，端子垫140的上部分被定位在一个特定的位置中，但是，与端子垫140相关联的安装表面处于稍微不同的位置中。采用这样的偏移附接垫230，这种精确的定位可以得到满足。
提供本公开以揭示本发明的优选实施例和用于实施本发明的最佳方式。在这样描述了本发明之后，应该清楚的是，在不脱离本发明公开内容的范围和精神的情况下，可以对优选实施例进行各种不同的修改。当结构被识别为执行功能的装置时，该识别应当包括可以执行指定的功能的所有的结构。当本发明的结构被识别为耦接在一起时，这样的语言应该被广义地解释，以包括这些结构直接被耦接在一起，或者这些结构通过中间结构被耦接在一起。这种耦接可以是永久性的或者临时的，可以为刚性的方式或者以在仍然提供某一形式的附接的同时允许枢转、滑动或其它相对运动的方式，除非有特别的限制。
工业实用性
本发明表现出了工业实用性，因为它提供了一种用于制造半导体封装的电互连部件的系统，其允许实施简化的QFN工艺来更加容易地制造QFN封装半导体管芯。
本发明的另一个目的在于提供一种降低投入实践的成本的QFN制造工艺。
本发明的另一个目的在于提供一种用于形成在牺牲载体上排列的半导体封装的电互连部件的系统和方法，产生具有垫的多个半导体封装的连续条带，便于在各种不同的制造阶段的测试和避免材料浪费，其中，牺牲载体可以在模制之后被剥离掉或以另外的方式被分离，在任何两个垫之间没有电连接。
本发明的另一个目的在于以这样的方式提供半导体封装的电互连部件：当在其中利用最少量的金属的同时，能够实现更高的电性能，以便于半导体管芯与电子系统的系统板电连接。
本发明的另一个目的在于提供半导体封装的电互连部件，所述电互连部件允许包含多于两行的输入/输出端子，即为通过基于引线框架的QFN封装实践的输入/输出端子的数量多倍。
本发明的另一个目的在于提供半导体封装的电互连部件，当与现有技术的基于引线框架的QFN封装相比时，该半导体封装允许更大的设计灵活性以合并特征，例如多个电力和接地结构和多个管芯附接垫。
本发明的另一个目的在于提供一种在其上具有多个集成电路安装封装位点的引线载体，其可以以低成本、高质量的方式来制造。
本发明的另一个目的在于提供一种用于与相邻的部件电互连的半导体封装，其对于与给它的冲击负荷相关联的损坏具有高度耐抗性。
本发明的另一个目的在于提供一种具有多个集成电路安装封装位点的引线载体，其通过最少化其中的多余的导电部分来表现出高的电性能。
本发明的另一个目的在于提供一种在其上具有封装位点的引线载体，其可以在制造工艺的多个阶段处以简单的自动的方式来被测试。
本发明的另一个目的在于提供一种半导体封装制造方法，其适合于高质量、低成本的大规模的生产制造。
通过认真阅读包含的详细描述、查看附图和查看这里包含的权利要求，本发明的显示其工业实用性的其它的进一步的目的将变得清楚。

Claims (29)

1.一种用于形成引线载体的方法，在该引线载体上具有多个集成电路封装位点，每一个封装位点包括用于集成电路的至少一个管芯附接垫和与管芯垫分离的至少一个端子垫，该方法包括下述步骤：
选择导电材料的供体片材；
将可熔固定材料按照可熔固定材料图案耦接到供体片材的第一表面，该可熔固定材料图案包括所述至少一个管芯附接垫的部分和所述至少一个端子垫的部分；
将管芯附接垫的可熔固定材料部分与所述至少一个端子垫的可熔固定材料部分分隔开；
从所述第一表面蚀刻掉所述供体片材，至少部分地蚀刻到不被所述可熔固定材料覆盖的所述供体片材的第一表面的部分上的供体表面；以及
将可熔固定材料附接到与所述供体片材相对的所述可熔固定材料的一侧上的临时支撑部件。
2.根据权利要求1所述的方法，包括从所述引线载体的其它部分分离临时支撑部件的进一步的步骤。
3.根据权利要求2所述的方法，其中，所述分离步骤包括从所述引线载体的其它部分剥离临时支撑部件的步骤。
4.根据权利要求2所述的方法，包括下述的进一步的步骤：
将集成电路安装在与所述可熔固定材料相对的管芯附接垫的分离表面上；
用导线将所述集成电路接合到所述至少一个端子垫；
用基本上不导电的模制化合物至少部分地封装集成电路、接合线以及所述至少一个端子垫和所述至少一个管芯附接垫之间的空间；以及
将引线载体切割成单独的封装，每一个封装包括至少一个端子垫和至少一个管芯附接垫。
5.根据权利要求2所述的方法，包括通过所述引线载体的可熔固定材料部分对所述引线载体进行电测试的进一步的步骤。
6.根据权利要求1所述的方法，其中，所述耦接步骤包括下述步骤：
对所述供体片材的第一表面施加可光成像材料；
选择性地光蚀刻掉所述可光成像材料的部分，从而限定期望的可熔固定材料图案；以及
用可熔固定材料填充所述可光成像材料的蚀刻掉的部分。
7.根据权利要求6所述的方法，其中，所述填充步骤包括：将可熔固定材料颗粒流入所述可光成像材料的蚀刻掉的部分中，并且，将可熔固定材料颗粒一起熔接成基本上刚性的固体块。
8.根据权利要求7所述的方法，其中，所述熔接步骤包括：对可熔固定材料充分地加热，以将可熔固定材料烧结成用于可熔固定材料图案的每一个连续部分的固体整体块。
9.根据权利要求1所述的方法，其中，所述耦接步骤包括：通过从包括电镀和无电沉积的沉积工艺组中采取的工艺，将所述可熔固定材料沉积在所述供体片材的第一表面上。
10.根据权利要求1所述的方法，其中，所述附接步骤包括将所述可熔固定材料加热到熔化温度，其中所述临时支撑部件由具有比所述可熔固定材料的熔化温度高的熔点的材料形成。
11.根据权利要求1所述的方法，包括从所述供体片材的与第一表面相对的第二表面进一步蚀刻掉所述供体片材从而至少部分地蚀刻到所述供体片材的第二表面中的进一步的步骤。
12.根据权利要求11所述的方法，其中，所述进一步蚀刻步骤包括下述步骤：
对所述供体片材的第一表面施加可光成像材料层；
选择性地光蚀刻掉所述可光成像材料的部分，从而限定期望的抗蚀图案；以及
用抗蚀材料填充所述可光成像材料层的蚀刻掉的部分。
13.根据权利要求12所述的方法，其中，所述进一步蚀刻步骤遵循与所述可熔固定材料图案的图案类似的图案，使得在所述进一步蚀刻步骤之后基本上电隔离的端子垫和管芯附接垫保留。
14.根据权利要求1所述的方法，其中，所述蚀刻步骤和所述进一步蚀刻步骤提供至少部分地彼此对准的上蚀刻凹部和下蚀刻凹部，其中与所述上蚀刻凹部和下蚀刻凹部相邻的端子垫和管芯附接垫的侧表面的特征是在所述上蚀刻凹部和所述下蚀刻凹部之间的结处横向地延伸的鳍片。
15.一种引线载体，用于在电气系统内提供半导体器件的电互连，该引线载体组合地包括：
由高温抗蚀剂材料形成的临时层；
所述临时层具有顶表面；
在所述临时层的所述顶表面上的至少两个垫；
由导电材料形成的所述垫；以及
所述至少两个垫中的每一个包括由可熔固定材料形成的下部分和由与所述可熔固定材料不同的导电材料形成的上部分。
16.根据权利要求15所述的引线载体，其中，所述临时层由不锈钢形成，所述临时层足够薄以弯曲用于从所述垫和基本上不导电的封装材料剥离去除。
17.根据权利要求15所述的引线载体，其中，所述临时层具有比所述可熔固定材料的熔化温度高的熔点。
18.根据权利要求17所述的引线载体，其中，所述至少两个垫的所述上部分由具有比所述可熔固定材料的所述熔化温度高的熔点的材料形成。
19.根据权利要求18所述的引线载体，其中，所述至少两个垫的所述可熔固定材料具有得自于悬浮组分和金属粉末组分的混合物的形式，所述悬浮组分和金属粉末组分被烧结以去除所述悬浮组分，并且将所述粉末组分烧结成整体固体。
20.根据权利要求18所述的引线载体，其中，可熔固定材料是在所述至少两个垫的所述上部分上的电镀层。
21.根据权利要求15所述的引线载体，其中，所述至少两个垫包括适合于在其上支撑半导体的至少一个管芯附接垫、以及多个输入/输出端子垫，所述管芯附接垫与所述端子垫分隔开，并且，所述管芯附接垫大于所述端子垫。
22.根据权利要求15所述的引线载体，其中，所述临时层在其上包括多个封装位点，所述封装位点中的每一个包括所述至少两个垫、所述半导体器件、所述接合线和基本上不导电的封装材料。
23.根据权利要求22所述的引线载体，其中，所述至少两个垫中的至少一个在所述下表面之上的部分大于在所述下部分处的所述垫，使得所述基本上不导电的封装材料倾向于将所述至少一个垫保持在所述基本上不导电的封装材料内。
24.根据权利要求23所述的引线载体，其中，所述至少一个垫表现出相对于所述临时层的所述顶表面在所述至少一个垫的顶侧和底侧之间横向地延伸的鳍片。
25.一种引线载体，用于支撑具有多个输入和/或输出的电子器件，该引线载体组合地包括：
相互分隔开的多个导电垫；以及
所述垫由下部分和上部分形成，所述下部分包括可熔固定材料，所述上部分由具有比所述可熔固定材料的熔化温度高的熔点的导电材料形成。
26.根据权利要求25所述的引线载体，其中，所述垫位于具有比形成所述垫的所述下部分的所述可熔固定材料的所述熔化温度高的熔点的共用临时层上。
27.根据权利要求26所述的引线载体，其中，所述临时层是充分柔韧的，以允许从所述临时层剥离去除所述垫和基本上不导电的封装材料。
28.根据权利要求25所述的引线载体，其中，所述多个导电垫中的至少一个具有边缘，与限定横向垫宽度的所述下部分分隔开的所述边缘的第一部分大于与所述下部分相邻的所述边缘的第二部分，从而所述第一部分悬垂在所述第二部分之上。
29.根据权利要求25所述的引线载体，其中，半导体位于所述多个导电垫中的至少一个的顶侧上，其中接合线从所述半导体延伸到与所述半导体分隔开的导电垫，所述垫、所述接合线和所述半导体至少部分地被封装在基本上不导电的材料内。
CN201280039935.XA 2011-07-03 2012-07-03 具有热熔接封装部件的引线载体 Expired - Fee Related CN103843133B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161504225P 2011-07-03 2011-07-03
US61/504,225 2011-07-03
PCT/US2012/000316 WO2013006209A2 (en) 2011-07-03 2012-07-03 Lead carrier with thermally fused package components

Publications (2)

Publication Number Publication Date
CN103843133A true CN103843133A (zh) 2014-06-04
CN103843133B CN103843133B (zh) 2017-10-27

Family

ID=47389758

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280039935.XA Expired - Fee Related CN103843133B (zh) 2011-07-03 2012-07-03 具有热熔接封装部件的引线载体

Country Status (5)

Country Link
US (2) US20130001761A1 (zh)
EP (1) EP2727145A4 (zh)
JP (1) JP2014518455A (zh)
CN (1) CN103843133B (zh)
WO (1) WO2013006209A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110573840A (zh) * 2017-04-28 2019-12-13 盛思锐股份公司 传感器封装

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5868043B2 (ja) * 2011-07-04 2016-02-24 ルネサスエレクトロニクス株式会社 半導体装置
CN103474358A (zh) * 2013-09-29 2013-12-25 华进半导体封装先导技术研发中心有限公司 多圈qfn封装引线框架制备方法
US20160181180A1 (en) * 2014-12-23 2016-06-23 Texas Instruments Incorporated Packaged semiconductor device having attached chips overhanging the assembly pad
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US9842831B2 (en) * 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
US9818656B1 (en) * 2017-05-23 2017-11-14 Nxp Usa, Inc. Devices and methods for testing integrated circuit devices
US11866042B2 (en) 2018-08-20 2024-01-09 Indian Motorcycle International, LLC Wheeled vehicle adaptive speed control method and system
DE102019127791B4 (de) 2019-10-15 2022-09-01 Infineon Technologies Ag Package mit separaten Substratabschnitten und Verfahren zum Herstellen eines Packages
US11562947B2 (en) * 2020-07-06 2023-01-24 Panjit International Inc. Semiconductor package having a conductive pad with an anchor flange
US11569179B2 (en) * 2020-11-19 2023-01-31 Advanced Semiconductor Engineering, Inc. Package structure including an outer lead portion and an inner lead portion and method for manufacturing package structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US20030071333A1 (en) * 2001-10-15 2003-04-17 Shinko Electric Industries Co., Ltd. Leadframe, method of manufacturing the same, and method of manufacturing a semiconductor device using the same
US20090294950A1 (en) * 2002-04-01 2009-12-03 Panasonic Corporation Semiconductor device
US20100140765A1 (en) * 2008-12-05 2010-06-10 Zigmund Ramirez Camacho Leadless integrated circuit packaging system and method of manufacture thereof

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
WO1995026047A1 (en) * 1994-03-18 1995-09-28 Hitachi Chemical Company, Ltd. Semiconductor package manufacturing method and semiconductor package
JP3205235B2 (ja) * 1995-01-19 2001-09-04 シャープ株式会社 リードフレーム、樹脂封止型半導体装置、その製造方法及び該製造方法で用いる半導体装置製造用金型
JPH0945805A (ja) * 1995-07-31 1997-02-14 Fujitsu Ltd 配線基板、半導体装置及び半導体装置を配線基板から取り外す方法並びに半導体装置の製造方法
US7247526B1 (en) * 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US7226811B1 (en) * 1998-06-10 2007-06-05 Asat Ltd. Process for fabricating a leadless plastic chip carrier
US7071541B1 (en) * 1998-06-24 2006-07-04 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP3450236B2 (ja) * 1999-09-22 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6333252B1 (en) * 2000-01-05 2001-12-25 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
DE10004410A1 (de) * 2000-02-02 2001-08-16 Infineon Technologies Ag Halbleiterbauelement mit an der Unterseite befindlichen Kontakten und Verfahren zur Herstellung
KR100347706B1 (ko) * 2000-08-09 2002-08-09 주식회사 코스타트반도체 이식성 도전패턴을 포함하는 반도체 패키지 및 그 제조방법
JP2002111197A (ja) * 2000-10-02 2002-04-12 Sony Corp 部品交換方法および部品交換装置
JP4245370B2 (ja) * 2003-02-21 2009-03-25 大日本印刷株式会社 半導体装置の製造方法
US7226881B2 (en) * 2003-09-19 2007-06-05 Kabushiki Kaisha Ohara Ultra low thermal expansion transparent glass ceramics
MY140980A (en) * 2003-09-23 2010-02-12 Unisem M Berhad Semiconductor package
JP4187691B2 (ja) * 2004-06-29 2008-11-26 富士通マイクロエレクトロニクス株式会社 閾値変調型イメージセンサ
US7259576B2 (en) * 2005-03-14 2007-08-21 Agilent Technologies, Inc. Method and apparatus for a twisting fixture probe for probing test access point structures
US20080079127A1 (en) * 2006-10-03 2008-04-03 Texas Instruments Incorporated Pin Array No Lead Package and Assembly Method Thereof
DE112006004099B4 (de) * 2006-11-14 2013-08-22 Infineon Technologies Ag Elektronisches Bauelement und Verfahren zu dessen Herstellung
WO2008099321A1 (en) * 2007-02-14 2008-08-21 Nxp B.V. Dual or multiple row package
US8115285B2 (en) * 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
JP4483969B2 (ja) * 2008-03-31 2010-06-16 セイコーエプソン株式会社 基板及びその製造方法、半導体装置の製造方法
US7884488B2 (en) * 2008-05-01 2011-02-08 Qimonda Ag Semiconductor component with improved contact pad and method for forming the same
JP2009302095A (ja) * 2008-06-10 2009-12-24 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
US20090315159A1 (en) * 2008-06-20 2009-12-24 Donald Charles Abbott Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same
KR101627574B1 (ko) * 2008-09-22 2016-06-21 쿄세라 코포레이션 배선 기판 및 그 제조 방법
US8334584B2 (en) * 2009-09-18 2012-12-18 Stats Chippac Ltd. Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
US8525305B1 (en) * 2010-06-29 2013-09-03 Eoplex Limited Lead carrier with print-formed package components
WO2012099256A1 (ja) * 2011-01-21 2012-07-26 東洋インキＳｃホールディングス株式会社 接着剤組成物および積層体
US8344494B2 (en) * 2011-04-11 2013-01-01 Headway Technologies, Inc. Layered chip package and method of manufacturing same
US8586420B2 (en) * 2011-09-29 2013-11-19 Infineon Technologies Ag Power semiconductor arrangement and method for producing a power semiconductor arrangement
KR20130124858A (ko) * 2012-05-07 2013-11-15 삼성전자주식회사 반도체 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US20030071333A1 (en) * 2001-10-15 2003-04-17 Shinko Electric Industries Co., Ltd. Leadframe, method of manufacturing the same, and method of manufacturing a semiconductor device using the same
US20090294950A1 (en) * 2002-04-01 2009-12-03 Panasonic Corporation Semiconductor device
US20100140765A1 (en) * 2008-12-05 2010-06-10 Zigmund Ramirez Camacho Leadless integrated circuit packaging system and method of manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110573840A (zh) * 2017-04-28 2019-12-13 盛思锐股份公司 传感器封装
CN110573840B (zh) * 2017-04-28 2021-08-20 盛思锐股份公司 传感器封装

Also Published As

Publication number Publication date
EP2727145A2 (en) 2014-05-07
US20150194322A1 (en) 2015-07-09
EP2727145A4 (en) 2015-07-29
JP2014518455A (ja) 2014-07-28
WO2013006209A3 (en) 2013-04-11
US20130001761A1 (en) 2013-01-03
CN103843133B (zh) 2017-10-27
WO2013006209A2 (en) 2013-01-10

Similar Documents

Publication Publication Date Title
CN103843133A (zh) 具有热熔接封装部件的引线载体
US8749035B2 (en) Lead carrier with multi-material print formed package components
CN100479135C (zh) 半导体器件及其制造方法
KR102126009B1 (ko) 인쇄 형태의 단자 패드를 갖는 리드 캐리어
US8865524B2 (en) Lead carrier with print-formed package components
CN101151727A (zh) 集成电路芯片封装和方法
JPS58182853A (ja) 半導体素子のカプセル封じ法およびこの方法により得られる素子
CN104167395A (zh) 薄轮廓引线半导体封装
CN102386106A (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
CN101601133A (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US20180047588A1 (en) Lead carrier structure and packages formed therefrom without die attach pads
CN104319269A (zh) 多级引线框架
JP2018518827A (ja) プリント形成パッケージ部品と導電パス再配線構造体のリードキャリア
CN103972199A (zh) 线键合方法和结构
CN100463152C (zh) 制造一种直接芯片连接装置及结构的方法
CN103594388A (zh) 具有侧壁间隔物的接触垫及其制作方法
CN203787410U (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构
KR101134706B1 (ko) 리드 프레임 및 이의 제조 방법
CN108155170A (zh) 引线框
CN100456442C (zh) 具有支撑部的半导体封装结构及其制法
JP2006093556A (ja) 半導体装置及びその製造方法
KR20120115032A (ko) 리드 프레임 및 이의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171027

Termination date: 20200703

CF01 Termination of patent right due to non-payment of annual fee