CN103715178A - 双相介金属互连结构及其制作方法 - Google Patents

双相介金属互连结构及其制作方法 Download PDF

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CN103715178A
CN103715178A CN201210459988.9A CN201210459988A CN103715178A CN 103715178 A CN103715178 A CN 103715178A CN 201210459988 A CN201210459988 A CN 201210459988A CN 103715178 A CN103715178 A CN 103715178A
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metal
jie
phase
interconnect structure
weld
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CN103715178B (zh
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张景尧
张道智
庄东汉
李俊彦
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Abstract

一种双相介金属互连结构及其制作方法。所述双相介金属互连结构介于芯片与载板之间，包括第一介金属相、第二介金属相、第一焊接金属层以及第二焊接金属层。第二介金属相包覆第一介金属相，且第一介金属相与第二介金属相含有不同的高熔点金属。第一焊接金属层与第二焊接金属层分别配置于第二介金属相的相对两侧，其中第一介金属相是用以填补第二介金属相形成时产生的微孔洞缺陷。

Description

双相介金属互连结构及其制作方法
技术领域
本发明是有关于一种互连结构（interconnection），且特别是有关于一种双相介金属互连结构。
背景技术
碳化硅元件能提升功率组件（power module）的能量转换效率，然而，其封装工艺却面临迥然不同的技术问题。首先，现行硅基功率组件在运作的过程中，芯片的结温（junction temperature,Tj）约为150°C，尚在常用的无铅焊锡材料（Sn3.0Ag0.5Cu）可接受的温度范围内；但是在碳化硅元件导入应用后，即使是中小瓦数的电源管理组件或是太阳能微逆变器（solar micro inverter），其Tj也高于175°C，而Sn3.0Ag0.5Cu的起始熔化温度仅217°C，因此，在此温度环境下，将会发生剧烈的潜变（creep）效应，不利于互连机械强度的维持，无法满足长期可靠度的要求，更遑论应用于Tj高达250°C的车用电力组件等产品。因此，对碳化硅功率组件的制造而言，高温无铅焊料将是决定产品品质与寿命的关键因素之一。
目前，主要的高温无铅焊接技术包括锌基高温无铅焊料、奈米金属粉末烧结，以及固液扩散接合（solid-liquid inter-diffusion,SLID）。
与一般的回焊（reflow）或热压合（thermocompressive bonding）不同，固液扩散接合的原理是让低熔点的焊锡材料在短暂液化过程中与固态的高熔点金属完全反应成稳定的高熔点介金属化合物（intermetallic compound），这类高熔点介金属相之熔点高于300°C以上，因此，令互连在高温环境下仍保有良好的机械强度，以提升组件的长期可靠度。
然而，应用固液扩散接合，将会面临工艺与材料扩散行为等数种技术困难，于工艺困难需面临接合界面温度较高（260°C以上），工艺时间较长（10分钟以上）等问题，但仍可透过焊接材料与厚度选择、表面处理、组装参数控制等手法加以克服。而材料扩散行为可分为工艺引起与原生性行为，前者起因于基板与芯片的组装温度差异，导致芯片与基板端的焊料扩散速率不均；后者则是焊料转变为介金属化合物的过程中发生体积收缩效应。由于材料扩散行为属于不可逆的化学反应变化，所引发的孔洞（void）缺陷对功率组件长期的可靠度有负面的影响。此外，应指出，无论是整面互连或微互连结构接点（micro joint）都无法避免前述孔洞形成的现象。发明内容
本发明提出一种双相介金属互连结构（a dual-phase intermetallicinterconnection structure），介于芯片与载板之间，包括第一介金属相、第二介金属相、第一焊接金属层与第二焊接金属层。第二介金属相包覆第一介金属相，且第一介金属相与第二介金属相含有不同的高熔点金属。第一焊接金属层与第二焊接金属层分别配置于第二介金属相的相对两侧，其中第一介金属相是用以填补第二介金属相形成时所产生的微孔洞缺陷。
其中该第一介金属相为连续结构或不连续结构。该第一介金属相的成份包括Ni3Sn4、Cu6Sn5、Cu11In9、Ag3Sn、Ni28In72、AuSn4、AuSn2、AuSn或Au5Sn。该第二介金属相的成份包括Ni3Sn2、Cu3Sn、Ag4Sn、Ag3Sn或Ag2In。该高熔点金属的熔点例如高于300°C。
本发明提出一种双相介金属互连结构的制作方法，用以在芯片与载板之间形成互连，所述制作方法包括以下步骤。首先，在芯片与载板间形成金属堆叠；所述金属堆叠包括与芯片相邻配置的第一焊接金属层、与载板相邻配置的第二焊接金属层以及位于第一焊接金属层与第二焊接金属层之间的三明治金属结构层。三明治金属结构层是由一对外部金属层和外部金属层所夹的内部金属层所构成。接着，加热金属堆叠，使外部金属层溶化，并使外部金属层中的金属与内部金属层中的金属形成第一介金属相，外部金属层中的金属与第一焊接金属层与第二焊接金属层中的金属形成第二介金属相，其中第二介金属相包覆第一介金属相。
其中该内部金属层的厚度例如小于该对外部金属层的厚度之和。在加热该金属堆栈的步骤期间，还包括对该金属堆栈施加压力。该第一焊接金属层、该第二焊接金属层以及该内部金属层例如由高熔点金属组成，该对外部金属层例如由低熔点金属组成。
该第一焊接金属层与该第二焊接金属层由相同的高熔点金属组成，而该内部金属层与该第一焊接金属层由不同的的高熔点金属组成。该对外部金属层的材料是由锡与铟所组成的族群中选择的一种金属材料。
该第一焊接金属层与该第二焊接金属层的材料是由银、镍与铜所组成的族群中选择的一种金属材料。该内部金属层的材料是由金、银、镍与铜所组成的族群中选择的一种金属材料。
本发明提出一种电子构装结构，包括芯片、载板以及前述的双相介金属互连结构，其中芯片与载板通过双相介金属互连结构接合。
本发明提出一种电子构装结构，包括第一芯片、第二芯片以及前述的双相介金属互连结构，其中第一芯片与第二芯片通过双相介金属互连结构接合。
本发明提出一种电子构装结构，包括至少一个整面互连或至少一个凸块接点，其中所述整面互连或凸块接点为前述的双相介金属互连结构。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1A与图1B是本发明的第一实施例的一种双相介金属互连结构的剖面示意图；
图2A至图2C是本发明的第二实施例的一种双相介金属互连结构的制作方法的剖面流程图。
附图标记说明：
100：双相介金属互连结构
102、103：第一介金属相
104：第二介金属相
106、202：第一焊接金属层
108、204：第二焊接金属层
110、210：芯片
120、220：载板
200：三明治金属结构层
206：外部金属层
208：内部金属层
230：金属堆叠
240：第二介金属相
250：第一介金属相
F：压力
具体实施方式
以下将以数个实施范例来说明本发明。在此，应先指出，说明书中所谓「高熔点金属」与「低熔点金属」，分别是指，在将温度升高至一特定值时，前者维持固态，后者熔化，且两者之间可以进行固液交互扩散而形成介金属化合物的两种金属，其具体实例如下详述。
图1A与图1B是本发明的第一实施例的一种双相介金属互连结构的剖面示意图。
参照图1A与图1B，双相介金属互连结构100配置于芯片110与载板120之间，其包括第一介金属相102、第二介金属相104、第一焊接金属层106与第二焊接金属层108。
芯片110可以是任意一种半导体芯片，例如功率组件中的金属氧化物半导体晶体管（MOSFET）或绝缘闸双极晶体管（insulated gate bipolar transistor,IGBT）芯片；或是中央处理器（central processing unit,CPU）或图形处理器（graphic processing unit,GPU）。载板120可以是适于与芯片110接合的任意基板，例如铜基板、硅中介层（interposer）、导线架（lead frame）或另一芯片。
第一介金属相102与第二介金属相104均是由高熔点金属与低熔点金属经固液交互扩散而形成的介金属化合物，且第一介金属相102与第二介金属相104含有不同的高熔点金属。譬如，第一介金属相102可以是Ag3Sn，而第二介金属相104可以是Cu6Sn5，亦即，第一介金属相102含有的高熔点金属为银，而第二介金属相104含有的高熔点金属为铜。当然，本实施范例并不以此为限，在其他实施型态中，第一介金属相102的成份可包括Ni3Sn4、Cu6Sn5、Cu11In9、Ag3Sn、Ni28In72、AuSn4、AuSn2、AuSn或Au5Sn；而第二介金属相104的成份可以包括Ni3Sn2、Cu3Sn、Ag4Sn、Ag3Sn或Ag2In，只要第一介金属相102与第二介金属相104含有不同的高熔点金属即可。此外，第二介金属相104可由成份相同但化学计量比不同的多种介金属化合物组成。例如，第二介金属相104可包括Cu6Sn5与Cu3Sn层介金属化合物。
在一实施范例中，第一介金属相102与第二介金属相104可含有相同的低熔点金属，例如锡。
如图1A所示，第一介金属相102被包覆于第二介金属相104中，且第一介金属相102为连续结构。在本实施范例的其他实施型态中，第一介金属相也可以是不连续的结构，也就是说，第一介金属相可以是多个被第二介金属相104隔离的聚集体（aggregate），如图1B所示的第一介金属相103。应注意，即使是如图1B所示的不连续结构，第一介金属相103仍被第二介金属相104完整地包覆。此外，第一介金属相可能具有不规则的形状，并不限于图1B绘示的球状聚集体，也不一定具有图1A绘示的平滑表面。
第一焊接金属层106与第二焊接金属层108分别配置于第二介金属相104的相对两侧。第一焊接金属层106与第二焊接金属层108可以是相同的高熔点金属，例如镍、铜或银。在一实施范例中，第一焊接金属层106、第二焊接金属层108与第二介金属相104所含的高熔点金属是同一金属。
在本实施范例中，第一介金属相102可以填补或嵌入于第二介金属相104形成时所产生的微孔洞缺陷，使双相介金属互连结构100整体成为致密结构，而不具因工艺引起或原生性行为导致的体积收缩而产生的孔洞，从而提高了双相介金属互连结构100的机械性质。在第一介金属相102为Ag3Sn而第二介金属相104为Ni3Sn4或Cu6Sn5的实施范例中，第一介金属相102还具有提高双相介金属互连结构100的延展性、形成应力缓冲层（吸收因热膨胀系数不匹配而引起的疲劳应力）以及增益热传导性能等特性，因此，互连的寿命得以延长。
图2A至图2C是本发明的第二实施例的一种双相介金属互连结构的制作方法的剖面流程图。
本发明的第二实施范例提供一种双相介金属互连结构的制作方法，用以在芯片210与载板220之间形成互连。芯片210与载板220的实例可以和第一实施范例中所述者相同。
根据第二实施范例，双相介金属互连结构的制作方法包括以下步骤。
首先，如图2A所示，在芯片210与载板220间形成金属堆叠230。金属堆叠230包括与芯片210相邻配置的第一焊接金属层202，与载板220相邻配置的第二焊接金属层204以及位于第一焊接金属层202与第二焊接金属层204之间的三明治金属结构层200。第一焊接金属层202与第二焊接金属层204的材料可为高熔点金属，且可以和第一实施范例中所述的第一焊接金属层106与第二焊接金属层108的材料相同。在本实施范例中，只要第一焊接金属层202与第二焊接金属层204不会从芯片210或载板220上劈裂（peeling），其厚度通常愈厚愈好。考量工艺时间与良率，通常会将厚度设定为3μm至10μm，但本发明不限于此。
三明治金属结构层200是由一对外部金属层206和由外部金属层206所夹的内部金属层208所构成。外部金属层206的材料可以是低熔点金属，例如由锡与铟所组成的族群中选择的一种金属材料。外部金属层206在接合时作为焊料使用，其厚度通常愈薄愈好，但考量焊接品质、产能与良率，通常会将厚度设定为1μm至5μm，但本发明不限于此。至于内部金属层208，其材料可为高熔点金属，例如由金、银、镍与铜所组成的族群中选择的一种金属材料；其厚度可小于两个外部金属层206的厚度之和，在一实施范例中可为1μm至3μm，但本发明不限于此。在之后的加热工艺期间，外部金属层206的低熔点金属会分别和第一与第二焊接金属层202、204的高熔点金属以及内部金属层208的高熔点金属形成介金属化合物，因此，厚度须视材料形成介金属化合物时的反应速率、介金属比例及收缩比而再最佳化。
金属堆叠230的形成方法可包括电镀薄膜、印刷锡膏或其组合。此外，三明治金属结构层200可与第一焊接金属层202或第二焊接金属层204一同形成于芯片210或载板220上；或者，可在芯片210上依序形成第一焊接金属层202、外部金属层206与内部金属层208；在载板220上形成第一焊接金属层204与外部金属层206；再叠合前述两者，以形成三明治金属结构层200。当然，本发明不限于前述两种情形，只要在对金属堆叠230加热以前形成如图2A所示的结构即可。
接着，如图2B所示，加热金属堆叠230，使外部金属层206溶化。加热可在真空环境、还原气氛或大气环境下进行烧结接合。加热的温度视外部金属层206所含金属的熔点而定，通常比外部金属层206所含金属的熔点高约20°C至40°C，但本发明不限于此。温度愈高，愈有助于加快介金属化合物的形成，但必须避免过高的温度造成芯片或载板损坏。此外，在加热期间，还可对金属堆叠230施加压力F。压力F的施加有助于消除各金属层与介金属层界面的孔洞，也有助于填补介金属化合物形成时形成的孔洞，关于此点，下文将有更详细的解释。
在图2B所示的步骤中，外部金属层206分别和第一焊接金属层202与第二焊接金属层204反应，形成第二介金属相240，此处，是以第一焊接金属层202与第二焊接金属层204含同一种高熔点金属为范例来说明。同时，外部金属层206与内部金属层208反应，形成第一介金属相250。在一实施例中，内部金属层208的厚度小于一对外部金属层206的厚度之和，因此在图2B所示的时间点，内部金属层208已反应殆尽，而由内部金属层208反应得来的第一介金属相250散乱地分布在处于熔融态的外部金属层206内。应理解，虽然在图2B中将各金属层和介金属层之间的界面绘示为平滑界面，但微观上这些界面可能因原子交互扩散的作用而产生凹凸不平的界面特征。
如图2C所示，持温一段时间以后，介金属化的反应完成，亦即，外部金属层206的金属完全与第一焊接金属层202与第二焊接金属层204反应，形成包覆第一介金属相250的第二介金属相240。
第二介金属相240可包括一种或一种以上的介金属化合物。举例来说，当第一焊接金属层202与第二焊接金属层204所含的金属为铜，而外部金属层206所含的金属为锡时，铜与锡反应，会同时生成Cu6Sn5及Cu3Sn两种介金属化合物，Cu6Sn5较厚且优先形成，Cu3Sn较薄且随后形成，两者在时间顺序上几乎同时。随持温时间越长，Cu6Sn5会逐渐消耗变薄而转变成Cu3Sn，但要完全转化成Cu3Sn需要相当长的时间。Ni与Sn、Cu与In、Ni与In都有类似现象，差别在于，某些优先形成的介金属化合物不会完全转换成随后形成的介金属化合物。
第二介金属相240形成期间，孔洞（未绘示）可能由于工艺引起或原生性行为导致的体积收缩的缘故而产生。压力F的作用在于，芯片端与载板端的第二介金属相240形成时（如图2B中分别位于外部金属层206两侧的第二介金属相240），外部金属层206会快速消耗，造成体积收缩，形成断面或大孔洞。透过压力F往内挤压将有助缩小此缺陷或延缓此缺陷的形成。在持温持压的状态下继续固液交互扩散，当外部金属层206耗尽，此时的第二介金属相240互相接触，第一介金属相250得以崁入不规则结构或孔洞而填补这些缺陷。最终，第一介金属相250可能形成分离且各自被第二介金属相240包覆的多个聚集体结构，如图2C或图1B所示，也可能形成如图1A所示的连续结构。以上，是一种以第一介金属相250填补固液扩散接合期间形成的孔洞的可能机制，但本发明并不排除其他机制的可能性。
为证实本发明的实质效果，进行如下实验。
比较例1～3
在一对硅基板之间形成5μm镍层/3μm锡层/5μm镍层的金属堆叠，并在加热接合后以推力机对接合结构施以剪力，直到破坏接合结构为止。比较例中，仅形成一种介金属化合物（即Ni3Sn4），且此介金属化合物中具有孔洞。根据实验结果，比较例1～3的接合结构可承受的平均应力约为13MPa。
实验例1～3
在芯片与载板之间形成5μm镍层/1.5μm锡层/2μm银层/1.5μm锡层/5μm镍层的金属堆叠，并在加热接合后以推力机对接合结构施以剪力，直到接合结构破坏为止。实验例中，除了Ni3Sn4以外也形成了Ag3Sn。Ag3Sn不但可以填补Ni3Sn4形成时造成的孔洞，且其热传导系数为44.5W/mK，也大于Ni3Sn4的热传导系数（19.6W/mK），因此有利于降低热的累积。此实验例的接合结构可承受的平均应力上升至大于20MPa。
比较例4～6
在一对硅基板之间形成5μm镍层/3μm铟层/5μm镍层的金属堆叠，并在加热接合后以推力机对接合结构施以剪力，直到破坏接合结构为止。比较例4～6中，仅形成一种介金属化合物（即镍铟化合物），且此介金属化合物中具有孔洞。根据实验结果，比较例的接合结构可承受的平均应力约为6MPa。
实验例4～6
在一对硅基底之间形成5μm镍层/3μm铟层/1μm银层/3μm铟层/5μm镍层的金属堆叠，此金属堆叠经加热接合以后，在镍铟化合物中形成了Ag2In，同样具有提升机械强度以及促进热传导的效果，其可承受的平均应力上升至大于10MPa。
表1详细呈现比较例与实验例的实验结果。
表1
Figure BDA00002410157400081
Figure BDA00002410157400091
本发明的第三实施例提供了一种电子构装结构，其是利用第一实施例所述的双相介金属互连结构，将芯片接合至载板。芯片例如可与前文针对芯片110所述者相同；载板例如可与前文针对载板120所述者相同。
本发明的第四实施例提供了一种电子构装结构，在此电子构装结构中至少包括一个整面互连或至少一个凸块接点（bump contact），且此整面互连或凸块接点为第一实施范例所述的双相介金属互连结构。
综上所述，本发明提供一种双相介金属互连结构、其制作方法，以及使用此双相介金属互连结构的电子构装结构。在双相介金属互连结构中，第一介金属相可以填补或嵌入于第二介金属相形成时所产生的微孔洞缺陷，使双相介金属互连结构不再具有因体积收缩而产生的孔洞，从而提高了双相介金属互连结构的机械性质。若材料选择适当，则第一介金属相还具有提高双相介金属互连结构的延展性、形成应力缓冲层（吸收因热膨胀系数不匹配而引起的疲劳应力）以及增益热传导性能等特性，互连的寿命因此得以延长。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明权利要求的保护范围。

Claims (17)

1.一种双相介金属互连结构，介于一芯片与一载板之间，其特征在于所述结构包括：
第一介金属相；
第二介金属相，包覆该第一介金属相，且该第一介金属相与该第二介金属相分别含有不同的高熔点金属；以及
第一焊接金属层与第二焊接金属层，分别配置于该第二介金属相的相对两侧；
其中该第一介金属相是用以填补该第二介金属相形成时因体积收缩而产生的微孔洞缺陷。
2.如权利要求1所述的双相介金属互连结构，其特征在于，所述第一介金属相为连续结构。
3.如权利要求1所述的双相介金属互连结构，其特征在于，所述第一介金属相为不连续结构。
4.如权利要求1所述的双相介金属互连结构，其特征在于，所述第一介金属相的成份包括Ni3Sn4、Cu6Sn5、Cu11In9、Ag3Sn、Ni28In72、AuSn4、AuSn2、AuSn或Au5Sn。
5.如权利要求1所述的双相介金属互连结构，其特征在于，所述第二介金属相的成份包括Ni3Sn2、Cu3Sn、Ag4Sn、Ag3Sn或Ag2In。
6.如权利要求1所述的双相介金属互连结构，其特征在于，所述高熔点金属的熔点高于300°C。
7.一种双相介金属互连结构的制作方法，用以在一芯片与一载板之间形成互连，其特征在于所述制作方法包括：
在该芯片与该载板间形成一金属堆叠，该金属堆叠包括：与该芯片相邻配置的第一焊接金属层、与该载板相邻配置的第二焊接金属层、以及位于该第一焊接金属层与该第二焊接金属层之间的三明治金属结构层，该三明治金属结构层是由一对外部金属层和该对外部金属层所夹的内部金属层所构成；以及
加热该金属堆叠，使该对外部金属层溶化，使该对外部金属层中的金属与该内部金属层中的金属形成第一介金属相，并使该对外部金属层中的金属与该第一焊接金属层与该第二焊接金属层中的金属形成第二介金属相，其中该第二介金属相包覆该第一介金属相。
8.如权利要求7所述的双相介金属互连结构的制作方法，其特征在于，所述内部金属层的厚度小于该对外部金属层的厚度之和。
9.如权利要求7所述的双相介金属互连结构的制作方法，其特征在于，在加热该金属堆叠的步骤期间，还包括对该金属堆叠施加压力。
10.如权利要求7所述的双相介金属互连结构的制作方法，其特征在于，该第一焊接金属层、该第二焊接金属层以及该内部金属层由高熔点金属组成，该对外部金属层由低熔点金属组成。
11.如权利要求10所述的双相介金属互连结构的制作方法，其特征在于，该第一焊接金属层与该第二焊接金属层由相同的高熔点金属组成，而该内部金属层与该第一焊接金属层由不同的的高熔点金属组成。
12.如权利要求10所述的双相介金属互连结构的制作方法，其特征在于，所述对外部金属层的材料是由锡与铟所组成的族群中选择的一种金属材料。
13.如权利要求11所述的双相介金属互连结构的制作方法，其特征在于，该第一焊接金属层与该第二焊接金属层的材料是由银、镍与铜所组成的族群中选择的一种金属材料。
14.如权利要求11所述的双相介金属互连结构的制作方法，其特征在于，所述内部金属层的材料是由金、银、镍与铜所组成的族群中选择的一种金属材料。
15.一种电子构装结构，包括芯片、载板、以及如权利要求1至权利要求6中任一项所述的双相介金属互连结构，其中该芯片与该载板通过该双相介金属互连结构接合。
16.一种电子构装结构，包括第一芯片、第二芯片、以及如权利要求1至权利要求6中任一项所述的双相介金属互连结构，其中该第一芯片与该第二芯片通过该双相介金属互连结构接合。
17.一种电子构装结构，包括至少一个整面互连或至少一个凸块接点，该整面互连或该凸块接点为如权利要求1至权利要求6中任一项所述的双相介金属互连结构。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049564A1 (en) 2014-08-13 2016-02-18 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN109314063A (zh) * 2016-06-14 2019-02-05 三菱电机株式会社 电力用半导体装置
CN113169093A (zh) * 2018-12-20 2021-07-23 奥托马特里克斯责任有限公司 用于在基板上烧结电子器件的烧结压机

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008054415A1 (de) * 2008-12-09 2010-06-10 Robert Bosch Gmbh Anordnung zweier Substrate mit einer SLID-Bondverbindung und Verfahren zur Herstellung einer solchen Anordnung
JP2015122445A (ja) * 2013-12-24 2015-07-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10043731B2 (en) 2015-09-01 2018-08-07 Toyota Motor Engineering & Manufacturing North America, Inc. Multi-step processes for high temperature bonding and bonded substrates formed therefrom
JP6451866B2 (ja) * 2015-11-16 2019-01-16 株式会社豊田中央研究所 接合構造体およびその製造方法
DE102015120773A1 (de) * 2015-11-30 2017-06-01 Osram Opto Semiconductors Gmbh Bauelement und Verfahren zur Herstellung eines Bauelements
US9741682B2 (en) 2015-12-18 2017-08-22 International Business Machines Corporation Structures to enable a full intermetallic interconnect
DE102017108422A1 (de) 2017-04-20 2018-10-25 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement
CN110164782A (zh) * 2018-02-13 2019-08-23 财团法人工业技术研究院 封装结构及组件连接的方法
KR102065765B1 (ko) * 2018-07-02 2020-01-14 제엠제코(주) 솔더범프를 이용한 반도체칩의 단자 접합방법
EP3806146A1 (en) * 2019-10-11 2021-04-14 Infineon Technologies Austria AG Semiconductor device with a diffusion soldered joint with precipitates of a further intermetallic compound and a corresponding manufacturing method
DE102020130638A1 (de) * 2019-12-11 2021-06-17 Infineon Technologies Ag Lotmaterial, schichtstruktur, chipgehäuse, verfahren zum bilden einer schichtstruktur, verfahren zum bilden eines chipgehäuses, chipanordnung und verfahren zum bilden einer chipanordnung
EP3852140A1 (en) * 2020-01-20 2021-07-21 Infineon Technologies Austria AG Silicon carbide power semiconductor device with a diffusion soldered joint comprising ni3sn4 and a corresponding fabrication method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070089811A1 (en) * 2005-10-26 2007-04-26 Osamu Ikeda Semiconductor device and method for manufacturing thereof
CN102157456A (zh) * 2011-03-23 2011-08-17 南通富士通微电子股份有限公司 三维系统级封装方法
CN102403304A (zh) * 2011-12-06 2012-04-04 上海集成电路研发中心有限公司 一种互连结构及其制作方法
WO2012053178A1 (ja) * 2010-10-22 2012-04-26 パナソニック株式会社 半導体接合構造体および半導体接合構造体の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7276801B2 (en) 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
US7390735B2 (en) 2005-01-07 2008-06-24 Teledyne Licensing, Llc High temperature, stable SiC device interconnects and packages having low thermal resistance
DE102006008632B4 (de) 2006-02-21 2007-11-15 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
US7598603B2 (en) 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
DE102006031405B4 (de) 2006-07-05 2019-10-17 Infineon Technologies Ag Halbleitermodul mit Schaltfunktionen und Verfahren zur Herstellung desselben
US8157158B2 (en) 2007-01-30 2012-04-17 International Business Machines Corporation Modification of solder alloy compositions to suppress interfacial void formation in solder joints
TW200840079A (en) * 2007-03-21 2008-10-01 High Power Lighting Corp Eutectic bonding material of LED and packaging method
TWI347643B (en) 2007-06-13 2011-08-21 Advanced Semiconductor Eng Under bump metallurgy structure and die structure using the same and method of manufacturing die structure
US7629246B2 (en) 2007-08-30 2009-12-08 National Semiconductor Corporation High strength solder joint formation method for wafer level packages and flip applications
TWI360452B (en) 2009-03-20 2012-03-21 Lung Chuan Tsao Composite lead-free solder composition having nano
TWI401825B (zh) * 2009-11-27 2013-07-11 Ind Tech Res Inst 發光二極體晶片的固晶方法及固晶完成之發光二極體
JP5552958B2 (ja) * 2010-08-17 2014-07-16 Ｔｄｋ株式会社 端子構造、プリント配線板、モジュール基板及び電子デバイス
JP5719167B2 (ja) * 2010-12-28 2015-05-13 ルネサスエレクトロニクス株式会社 半導体装置
FR2971081B1 (fr) * 2011-02-02 2013-01-25 Commissariat Energie Atomique Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue
US9490193B2 (en) * 2011-12-01 2016-11-08 Infineon Technologies Ag Electronic device with multi-layer contact

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070089811A1 (en) * 2005-10-26 2007-04-26 Osamu Ikeda Semiconductor device and method for manufacturing thereof
WO2012053178A1 (ja) * 2010-10-22 2012-04-26 パナソニック株式会社 半導体接合構造体および半導体接合構造体の製造方法
CN102157456A (zh) * 2011-03-23 2011-08-17 南通富士通微电子股份有限公司 三维系统级封装方法
CN102403304A (zh) * 2011-12-06 2012-04-04 上海集成电路研发中心有限公司 一种互连结构及其制作方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049564A1 (en) 2014-08-13 2016-02-18 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN105374776A (zh) * 2014-08-13 2016-03-02 三星电子株式会社 半导体芯片、半导体器件及其制造方法
US10249604B2 (en) 2014-08-13 2019-04-02 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN112071764A (zh) * 2014-08-13 2020-12-11 三星电子株式会社 半导体芯片、半导体器件及其制造方法
CN109314063A (zh) * 2016-06-14 2019-02-05 三菱电机株式会社 电力用半导体装置
CN113169093A (zh) * 2018-12-20 2021-07-23 奥托马特里克斯责任有限公司 用于在基板上烧结电子器件的烧结压机

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