CN103579093A - 集成电路装置及用以使用于该集成电路装置中的方法 - Google Patents
集成电路装置及用以使用于该集成电路装置中的方法 Download PDFInfo
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- 239000011229 interlayer Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 185
- 238000005530 etching Methods 0.000 claims description 99
- 239000000463 material Substances 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
本发明公开了一种集成电路装置及用以形成层间连接件于三维叠层集成电路装置中的方法。该集成电路装置,包括一由多个介电/导电层形成的叠层,以形成多个层间连接件;层间连接件自装置的一表面延伸至导电层;多个接触开口建立而贯穿一介电层至一第一导电层;N个刻蚀掩模具有分隔的多个开放刻蚀区及位于他处的多个掩模区,2N-1小于W且2N大于或等于W;层所形成的叠层是以仅贯穿W-1个接触开口而建立多个延伸接触开口,延伸接触开口延伸至W-1个导电层;利用各刻蚀掩模来透过至少半数的接触开口而刻蚀2n-1个导电层,n=1、2...N;接触开口是以刻蚀掩模的不同组合的开放刻蚀区来进行刻蚀;层间连接件形成于接触开口内。
Description
技术领域
本发明是有关于一种高密度集成电路装置,且特别是有关于一种集成电路装置及用以形成层间连接件于三维叠层集成电路装置中的方法。
背景技术
在制造高密度存储装置中,集成电路上的每个单位面积的数据总量可为一个关键要素。因此,当存储装置的关键尺寸接近光刻技术的限制时,为了让每个位达到较大的储存密度与较低的成本,用于叠层存储单元的多个层的技术被提出。
举例来说,在赖(Lai)等人于公元2006年12月11-13日的IEEE的国际电子元件会议(Int’l Electron Devices Meeting)中发表的「A Multi-LayerStackable Thin-Film Transistor(TFT)NAND-Type Flash Memory」中与在钟(Jung)等人于公元2006年12月11-13日的IEEE的国际电子元件会议中发表的「Three Dimensionally Stacked NAND Flash Memory Technology UsingStacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond30nm Node」中,薄膜晶体管技术被应用于电荷捕捉存储器。
另外,在强森(Johnson)等人于公元2003年11月的IEEE固态电路期刊第38卷第11号发表的「512-Mb PROM With a Three-Dimensional Array ofDiode/Anti-fuse Memory Cells」中,交叉点阵列技术被应用于反熔丝存储器。亦可见克里夫斯(Cleeves)的美国专利第7,081,377号,标题为「Three-Dimensional Memory」。
另一提供垂直NAND晶胞于电荷捕捉存储器技术中的结构被说明于金(Kim)等人在公元2008年6月17-19日在2008VLSI科技会议的技术论文(Symposium on VLSI Technology Digest of Technical Papers)第122-123页所发表的「Novel3-D Structure for Ultra-High Density Flash Memory withVRAT and PIPE」。
于三维叠层存储装置中,导电互连件用以耦接下层的存储单元于贯穿上层的译码电路与类似的元件。完成互连关系的花费是随着所需的光刻步骤的数目增加。一个减少光刻步骤的方法被说明于田中(Tanaka)等人在公元2007年6月12-14日在2007VLSI科技会议的技术论文第14-15页所发表的「Bit Cost Scalable Technology with Punch and Plug Process for UltraHigh Density Flash Memory」。
然而,传统三维叠层存储装置的其中一个缺点为一个分离的掩模一般被用于各个接触层。因此,如果例如有20个接触层,则通常需要20个不同的掩模,且各接触层需要为其建立掩模及刻蚀步骤。
发明内容
根据本发明的一些例子,仅需要N个掩模来提供通道至2N个导电层。根据部分的例子,2n-1个导电层是就各掩模顺序数字n进行刻蚀。于部分例子中,刻蚀掩模具有分开的开放刻蚀区且遮盖介电层的其他部分,开放刻蚀区仅位于选择的接触开口上。
一方法的一第一例子是形成多个层间连接件,这些层间连接件自装置的一表面延伸至导电层,此方法用以使用于一集成电路装置,包括一由多个介电/导电层形成的叠层。此方法是以下述方式执行。分隔的多个接触开口建立于集成电路装置的一接触区域内,而贯穿一介电层并以一介电层材料分隔各接触开口,接触开口位于一导电层上,用于W个导电层的每一个。建立这些接触开口亦包括向下建立一第一接触开口至一第一导电层。利用一组N个刻蚀掩模,2N-1小于W(全部导电层的数目)且2N大于或等于W,刻蚀掩模具有分隔的多个开放刻蚀区与多个位于其余地方的掩模区,这些开放刻蚀区对应于选择的接触开口。利用N个刻蚀掩模来刻蚀由介电/导电层形成的叠层,以仅贯穿W-1个接触开口而建立多个延伸接触开口,这些延伸接触开口延伸至W-1个导电层。在刻蚀步骤中,利用各刻蚀掩模来透过至少半数的接触开口而刻蚀2n-1个导电层,n=1、2...N。刻蚀步骤是执行,使得接触开口是以刻蚀掩模的不同组合的开放刻蚀区来进行刻蚀。形成层间连接件于第一接触开口内及延伸接触开口内,以电性连接于各导申层。
此方法的例子可能包括一或多个下述的内容。N个刻蚀掩模可配置,使得围绕在接触开口周围的介电材料实质上不会在刻蚀步骤中受影响。接触开口可被刻蚀,使得至少部分的层间连接件终结于多个导电层,这些导电层位在至少与相邻层间连接件所终结的导电层距离至少两个阶层的位置。层间连接件可具有由多个尺寸所形成的范围,从较大深度至平均深度至较浅深度,具有较大深度的第一层间连接件相邻于具有较浅深度的第二层间连接件,且具有平均深度的第三及第四层间连接件彼此相邻。
集成电路装置的一例子包括由交替的多个介电层与多个导电层的叠层,这些导电层包括一上导电层与一下导电层。一上层位于上导电层上,上层具有一上表面。多个层间连接件至上层的上表面延伸至导电层的每一个,以电性接触。层间连接件彼此分隔一平均的间隔。层间连接件具有由多个深度所形成的一范围,这些深度从多个较大深度至多个平均深度至多个较浅深度。具有较大深度的一第一层间连接件相邻于具有较浅深度的一第二层间连接件。具有概括的平均深度的第三层间连接件与第四层间连接件彼此相邻。
此集成电路装置的例子可能包括一或多个下述的内容。在这些层间连接件中,第一层间连接件具有最大深度,且第二层间连接件具有最浅深度。位于相邻的层间连接件之间的间隔为一实质固定间隔。
为了对本发明的上述及其他方面有更佳的了解,下文特举较佳实施例,并配合所附图式,作详细说明如下:
附图说明
图1绘示根据本发明的集成电路装置的一例子的简易剖面图,集成电路装置包括将被处理的垂直接触区。
图2绘示利用接触开口掩模在垂直接触区中建立接触开口的示意图。
图2A绘示一组接触开口形成在硬掩模的上表面。
图3绘示利用第一掩模来透过第一组的接触开口而刻蚀贯穿四层导电层的示意图。
图4绘示利用第二掩模来透过第二组的接触开口而刻蚀贯穿两层导电层的示意图。
图5绘示利用第三掩模来透过第三组的接触开口而刻蚀贯穿一层导电层的示意图。图5亦绘示接触开口掩模与第一及第二掩模,使得各者的开放刻蚀区的关系可轻易地看见。
图5A绘示一截面图,显示接触开口被延伸,穿过不同的导电层,并接触到最下面的导电层。
图6绘示在层间连接件已从介电层间下至导电层而形成在接触开口中以后的图5的结构的示意图。
图7类似于图5,但绘示出利用具有不同组合的开放刻蚀区的尺寸及数目的第一、第二及第三掩模来建立延伸接触开口的示意图。
【主要元件符号说明】
0-7:位置
10:装置、集成电路装置
12:存储单元区
14、14.1:垂直接触区
16:阵列/周边边界区
18:周边CMOS装置区
20:导电层与介电层叠层
22、22.0-22.7:介电层
24、24.0-24.7:导电层
26:介电衬底
28:层、刻蚀停止层
30:介电层间、硬掩模
30.1:硬掩模
32、32.0-32.7:接触开口
34、34.1-34.7:延伸接触开口
36:接触开口掩模、掩模
38:开放区、开放刻蚀区
40:封闭掩模区、掩模区
41:图像
42:第一掩模、掩模、刻蚀掩模、掩模、第一掩模、第一刻蚀掩模
44:第二掩模、掩模、刻蚀掩模、掩模、第二掩模、第二刻蚀掩模
46:第三掩模、掩模、刻蚀掩模、掩模、第三掩模、第三刻蚀掩模
48:表面、上表面
50、50.0、50.1、50.2、50.3、50.7:层间连接件
52:第一掩模
54:第二掩模
56:第三掩模
58、58.0-58.7:接触连接地区
62:介电绝缘套筒
具体实施方式
图1绘示集成电路装置10的一例子的简易剖面图,集成电路装置10包括存储单元区12、垂直接触区14、阵列/周边边界区16及周边CMOS装置区18。本发明将着重于垂直接触区14。装置10绘示具有可使用本发明的集成电路装置的一种形式的例子;其他装置亦可行。
请亦参照图2,垂直接触区14包括位于介电衬底26上的交替配置的多个介电层22及多个导电层24。于此例子中,有8对的介电层22及导电层24,以介电层22.0至22.7标注,且以导电层24.0至24.7标注。介电层22可为氧化物、氮化物、氮氧化合物、硅酸盐(silicate)或其他成分。具有介电常数小于二氧化硅的介电常数的低介电常数材料较佳的,例如是SiCHOX。具有介电常数大于二氧化硅的介电常数的高介电常数(high-k)材料亦可包括,例如是HfOx、HfON、AlOx、RuOx、TiOx。导电层24可为导电半导体,包括重掺杂多晶硅(利用掺杂物例如是As、P、B)、硅化物、氧化物半导体、及半导体与硅化物的组合,硅化物包括TiSi、CoSi、氧化物半导体包括InZnO与InGaZnO。导电层24亦可为金属、导电复合物、或包括Al、Cu、W、Ti、Co、Ni、TiN、TaN、TaAlN与其他物质的材料组合。
刻蚀停止层28位于导电层与介电层叠层20上,介电层间30位于层28上。介电层间30可以SiO2、PSG、BPSG或其组合制成,且作为非处理(non-disposal)硬掩模,此将透过下方的讨论而更为清楚。刻蚀停止层28是因如下文所讨论的用于一同步刻蚀功能(etching-synchronizing function)的能力挑选,且当硬掩模30为SiN时,刻蚀停止层28不可为SiN。
图2至图5绘示用以于垂直接触区14建立多个接触开口32与延伸接触开口34的步骤,多个接触开口32是在图式中的位置0-7,且延伸接触开口34见于图3至图7。图2中所示的垂直接触区14是与图1中所示的状态相同。此外,图2绘示具有多个开放刻蚀区38与多个封闭掩模区40的接触开口掩模36。通过利用接触开口掩模36,接触开口32被刻蚀贯穿硬掩模30、刻蚀停止层28与第一介电层22.0,且停止于第一导电层24.0。于此例子中,有八个用以建立八个接触开口32的开放刻蚀区38,一个接触开口32用于八个中的各个导电层24。导电层24的数目可以W表示。利用接触开口掩模36的刻蚀有时以接触开口刻蚀(CO(contact opening)base etching)表示,利用接触开口掩模36的刻蚀可在氮化硅/多晶硅/氧化硅层上以例如是使用刻蚀化学物的反应性离子刻蚀(reactive ion etching)执行,且停止于导电层24.0的顶部上。刻蚀化学物例如是包括CF4/C5F8/CH2F2/O2/Ar。其他步骤亦可用以建立接触开口32。接触开口32的建立是提供多个开口的图案给后续的刻蚀步骤。
简单起见,于图2至图5中,开放刻蚀区38是以多个形成在掩模36中的简单开口绘示。实际上,非线性光学可能需要在掩模中形成复杂的图案,以在硬掩模30的上表面48上建立出所需的影像。因此,开放刻蚀区38的尺寸和形状可能不会对应于图像41的尺寸和形状,请参见图2A。图像41是在一组接触开口32形成在图像41的位置前导引到硬掩模30的上表面48上。于图2A的例子中,导引到上表面48的图像41基本上为正方形,且以排列成一图案,以在完成的多个接触开口32间提供较好的分隔。其他图案的图像41亦可使用。通过图2A的例子所提供的分隔的加强也对在掩模上设置开放刻蚀区38和其他特征有帮助,例如是散射条(scatteringbar)。
开放刻蚀区38及接触开口32在本发明中剩余的图式内以排列成直线的方式绘示,以易于说明。投射到上表面48的图像41一般将较后续利用第一、第二及第三掩模42、44及46所投射的图像大一些。此提供可发生于后续的投影及刻蚀步骤期间的些微的未对准,以有助于避免侵蚀接触开口周围的介电材料。图像41可为正方形以外的形状,例如是矩形、圆形或椭圆形。在刻蚀期间所建立的接触开口32的剖面形状一般将依循图像41的形状。
图3至图5绘示在使用第一、第二及第三掩模42、44及46后的垂直接触区14的示意图。如上所提及关于图2的部分,导引到导电层24的表面上的图像可小于图像41,以提供可发生于后续的投影及刻蚀步骤期间的些微未对准而有助于避免侵蚀接触开口周围的介电材料。刻蚀工艺可利用例如是时间模式刻蚀(time mode etching)而以单一刻蚀化学物执行。或者,刻蚀工艺可利用不同刻蚀化学物执行,以分别地刻蚀贯穿不同层。当接触开口掩模36包括用于W个导电层中的各层的多个开放刻蚀区38时,各掩模42、44及46包括该数目的一半的开放刻蚀区38,于此例子中即为4个。请参照图5,其绘示全部的掩模36、42、44及46,由图式可见掩模42-46的各开放区38对齐于一个适当的接触开口32。利用第一、第二及第三掩模42、44及46的刻蚀可对氧化硅/多晶硅层以例如是使用刻蚀化学物的反应性离子刻蚀执行,且停止于适当的导电层24.0-24.7的顶部上。刻蚀化学物例如是包括CF4/N2/CH2F2/HBR/He-O2/He。
如图3所示的第一掩模42是定位于硬掩模30的上表面48的上方,且具有多个开放刻蚀区38在位置1、3、5及7对齐于多个接触开口32.1、32.3、32.5及32.7。在位置1、3、5及7的多个接触开口32的底部的材料从第一掩模42的开放刻蚀区38暴露于未绘出的图像,且接着被刻蚀四个阶层而贯穿第一导电层24.0及第二介电层22.1,以建立如图3中所示的结构。接着,如图4中所示,第一掩模42被移除且第二掩模44被接着定位在图3完成的结构的上方,使得多个开放刻蚀区38在位置1、3、4及6对齐于多个接触开口32.1、32.3、32.4及32.6。在多个接触开口32.1、32.3、32.4及32.6的底部的结构从第二掩模44的开放刻蚀区38暴露于未绘出的图像,且接着被刻蚀两个阶层,以建立如图4中所示的结构。再来,第二掩模44被移除且第三掩模46被接着定位在图4完成的结构的上方,使得多个开放刻蚀区38在位置1、2、5及6对齐于多个接触开口32.1、32.2、32.5及32.6。在多个接触开口32.1、32.2、32.5及32.6的底部的结构从第三掩模46的开放刻蚀区38暴露于未绘出的图像,且接着被刻蚀一个阶层,以建立如图5中所示的结构,此结构包括接触开口32.0及七个延伸接触开口34.1-34.7。利用第一、第二、第三掩模42、44、46进行刻蚀的顺序可改变,使得例如是第三掩模46第一个使用,第二掩模44第二个使用,且第一掩模42第三个使用。
图5A绘示在位置1的接触开口的简易、放大、些微夸张的剖面图。图5A绘示位于硬掩模30的上表面48及导电层24.0之间的接触开口如何具有较导电层24.0-24.7之间的接触开口大的截面积。另外也绘示出成锥形的接触开口,从具有较大截面积的在第一、较上方的导电层24.0到具有较小的截面积的在较低的导电层24.7。
图6绘示多个导电的层间连接件50,形成于接触开口32.0及延伸接触开口34.1-34.7内,以分别提供电性连接于导电层24.0、24.7、24.1、24.6、24.2、24.5、24.3及24.4。层间连接件50可以相同于上述讨论的导电材料制成。然而,因为现有关于这些导电材料的化学机械抛光知识的原因,掺杂Si、W及Cu较佳的。多个层间连接件50是以层间连接件50.0-50.7表示,对应于位置0-7。
于一些例子中,层间连接件50可能需要与其贯穿的导电层24绝缘。此需求可例如是通过在全部或部分的延伸接触开口34.1-34.7的内部全部地或部分地以介电材料形成内衬(lining)。图6绘示一例子,其中各接触开口32及延伸接触开口34是以介电绝缘套筒62作为内衬。此举是让层间连接件50与其贯穿的导电层24绝缘。举例来说,可见公元2012年四月19日申请的美国申请专利第13/451,411号。
于应用中,分隔的多个接触开口32贯穿介电层而建立,于此例中的介电层包括硬掩模30、刻蚀停止层28及第一介电层22.0。接触开口32的建立是提供用于后续刻蚀步骤的开口的图案。接触开口32被形成,使得介电层材料分隔多个接触开口,且多个应用于W个(于此例子中为八个)导电层中的每一个的接触开口位于导电层24上。接触开口32是向下形成至第一导电层24.0。于此例子中,接触开口32利用接触开口掩模36制成;亦可利用其他工艺制成接触开口32。
一组N个刻蚀掩模被使用,其中2N-1小于W且2N大于或等于W。举例来说,在N等于3时,三个掩模可用以建立七个延伸接触开口34,一个延伸接触开口34对应于七个位于第一导电层24.0的下方的导电层24各层。各刻蚀掩模42、44及46具有分隔的多个开放刻蚀区38及多个掩模区40,开放刻蚀区38定位在选择的接触开口32上,掩模区40覆盖硬掩模30的其他位置。
使用N个刻蚀掩模的刻蚀是只在通过接触开口32处进行,以建立延伸至位于导电层24的接触连接地区58(对应于位置0-7而分别在图5中以接触连接地区58.0-58.7标注)的延伸接触开口34。因此,接触连接地区58位于接触开口32.0及延伸接触开口34.1-34.7的底端。此刻蚀是以围绕在接触开口32周围的介电材料实质上不受影响的方式执行,使得只有相对少量的围绕在接触开口32的侧壁材料会在刻蚀步骤中被移除。此情况的一例子包括形成接触开口于硬掩模30的上表面48及导电层24.7之间,以具有较导电层24.0及24.6之间的接触开口大的截面积。
在典型的操作中,半数的接触开口32是在各刻蚀步骤中被刻蚀。举例来说,当五个掩模用于刻蚀通过31个接触开口,以到达31个不同的导电层24时,各掩模将被用于刻蚀半数(16)的接触开口。然而,当可被刻蚀的导电层24的数量大于被刻蚀的导电层的数量,例如是当五个掩模用于刻蚀通过29个接触开口,以到达29个不同的导电层24时,至少部分的掩模将不会用于刻蚀半数的接触开口,而是掩模将用以刻蚀多达半数的接触开口,有时称作为有效接触开口的半数(effectively half of contactopenings)。因此,在各刻蚀步骤中,利用各刻蚀掩模来透过至少半数的接触开口而刻蚀2n-1个导电层,其中n=1、2...N。
刻蚀步骤是执行,使得各接触开口32以不同组合的刻蚀掩模的开放刻蚀区38刻蚀,于此例子中,刻蚀掩模为第一、第二及第三刻蚀掩模42、44、46。接着,层间连接件50形成于延伸接触开口34内,以电性连接于各导电层24。
于一些例子中,开放刻蚀区38的周边的形状类似于接触开口32及延伸接触开口34的周边的形状,例如一般皆为正方形。
前述提及的形状为理想形状是可理解的。其他例子可建立其他的剖面形状,包括圆形、椭圆形及矩形,以取代图2A中的一般为正方形的形状。
在图2至图5揭露的例子中,未使用刻蚀掩模42、44、46刻蚀第一接触开口32.0。全部三个刻蚀掩模42、44、46被使用来刻蚀第二接触开口32.1,以贯穿七层导电层24。刻蚀掩模46被使用来刻蚀第三接触开口32.2,以贯穿一层导电层24。刻蚀掩模42及44被使用来刻蚀第四接触开口32.3,以贯穿六层导电层24。刻蚀掩模44被使用来刻蚀第五接触开口32.4,以贯穿两层导电层24。刻蚀掩模42及46被使用来刻蚀第六接触开口32.5,以贯穿五层导电层24。刻蚀掩模44及46被使用来刻蚀第七接触开口32.6,以贯穿三层导电层24。一个刻蚀掩模42被使用来刻蚀第八接触开口32.7,以贯穿四层导电层24。
由图5及图6可了解,在某些例子中,接触开口刻蚀步骤可执行,使得至少部分的层间连接件50终结于多个导电层24,这些导电层24位在至少与相邻层间连接件50所终结的导电层24距离至少两个阶层的位置。请参见所举的例子,在位置1的层间连接件50对在位置0与2的相邻的层间连接件50。以此方式进行及提供例如是如图2A中的图像的图案,有利于前述的至少部分的层间连接件50与其导电层24之间的接触扩大,因为接触之间是存有更多的空间。此种配置方式留下更多的工艺容许度(process window)来达到最深的接触开口,而不会损失与相邻接触开口的绝缘关系。
在部分的例子中,多个接触开口在表面48的截面积较佳地可全部概略相等,然而实际上接触开口越深,接触开口在表面48的截面积越大。最浅的接触开口在表面48的截面积,通常为仅延伸到导电层24.0的接触开口,可大概与接触开口在导电层24.0的截面积。然而,对于最深的接触开口来说,在表面48的截面积可能100%大于,或于某些例子中可能甚至400%大于在导电层24.0的截面积。
一般来说,间隔(pitch)为一固定距离,间隔也就是接触开口的中心到中心的距离。然而,为了效率之故,保持间隔为最小距离是需要的。但是,如果两个相对深的接触开口彼此相邻,由于相对深的接触开口在上表面48具有相对大的截面积,分离他们的介电层间30的总量可能变得相当地少,而导致不正确的结构。然而,此问题可通过配置接触开口来减少,使得(1)最深的接触开口(因此通常在表面48具有最大截面积或具有其中一个最大截面积的最深的层间连接件50)将位在最浅的接触开口(因此通常在表面48具有最小截面积或具有其中一个最小截面积的最浅的层间连接件50)的旁边,(2)次于最深的接触开口位于次于最浅的接触开口的旁边,(3)以此类推,直到深度大致上相同的接触开口彼此相邻。一个相对简单的例子是绘示于图6中。位于位置0的最浅的层间连接件50.0位于位置1的最深的层间连接件50.1的旁边,位于位置2的次于最浅的层间连接件50.2是位在最深的层间连接件50.1与于位置3的次于最深的层间连接件50.3之间,以此类推。在仍可如上所讨论的减少刻蚀步骤的次数的同时,通过适当对齐开放刻蚀区38,上述的结果可透过本发明的多种例子达成。
本发明的某些例子的另一优点将从图5及图7的比较突显出来,其中图5及图7的相同元件是以相同编号标注。图7是类似于图5,但图7被使用具有不同组合的开放刻蚀区38的尺寸与数目的第一、第二及第三掩模52、54及56,其中图7中的垂直接触区14.1是类似于先前所述的垂直接触区14。图7的第一掩模52具有一个开放刻蚀区38来覆盖半数(于此例子中为四个)的接触开口32及其间的硬掩模30.1。第一掩模52亦具有一个封闭掩模区40来覆盖其他的接触开口及其间的硬掩模30.1。第二掩模54具有两个开放刻蚀区38及两个封闭掩模区40,各选择性地覆盖四分之一个(于此例子中为两个)接触开口32及其间的硬掩模30.1。第三掩模56具有四个开放刻蚀区38及四个封闭掩模区40,各选择性地覆盖八分之一个(于此例子中为一个)接触开口32。
利用图7的例子的工艺是建立了严重退损的硬掩模30.1,硬掩模30.1是作为一氧化硬掩模,且必须在进一步的处理前移除。移除工艺是复杂又昂贵。因此,本发明的各种例子的另一优点为可在建立延伸接触开口34后,有效地减少移除硬掩模30的需求。
上述所讨论的与图7有关的用以建立延伸接触开口34的工艺亦可视为二元工艺,基于20...2n-1且n为刻蚀步骤的次数。也就是说,第一掩模52选择地覆盖20个接触开口32且暴露出20个接触开口32;第二掩模54选择地覆盖21个接触开口32且暴露出21个接触开口32;第三掩模56选择地覆盖22个接触开口32且暴露出22个接触开口32,以此类推。通过利用此二元工艺,n个掩模可用以提供2n个接触开口32给2n个导电层24。
更进一步关于类似的用于建立接触开口32及延伸接触开口34的技术及方法的数据被揭露于公元2011年3月16号的美国申请专利号第13/049,303号中,标题为「REDUCED NUMBER OF MASK FOR ICDEVICE WITH STACKED CONTACT LEVELS」;于公元2011年5月24号的美国申请专利号第13/114,931号中,标题为「MULTILAYERCONNECTION STRUCTURE AND MAKING METHOD」;于公元2012年4月19号的美国申请专利号第13/451,411号中,标题为「METHOD FORCREATING A3D STACKED MULTICHIP MODULE」;于公元2012年4月19号的美国申请专利号第13/451,428号中,标题为「INTEGRATEDCIRCUIT CAPACITOR AND METHOD」,这些揭露的内容被并入此案以供参考。此四篇申请案及本申请是具有共有的受让人。
本发明可应用于集成电路装置的广大范围,包括例如是3-D NAND闪存,且可为集成电路的特征,包括例如是硅通孔(through silicon via,TSV)结构或微流体散热器/散热结构。
在本发明已参照上述较佳实施例及例子详细地揭露如上的同时,这些例子用于说明而非作为限制之用是可理解的。可预期的是,此技术领域中的人员将可轻易地调整与结合,且调整与结合的结果将含括在本发明的精神与随附的权利要求范围的范围内。举例来说,于部分的例子中,一个层间连接件50延伸到同一个导电层24可能是需要的。这可通过在适当的掩模42、44及46中简单地复制开放刻蚀区38,以在所需的位置建立额外的延伸接触开口34。举例来说,为了要具有延伸至导电层24.3的第二个层间连接件50,额外一组对齐的开放刻蚀区38可提供于第二及第三掩模44及46中,而无需改变上述的刻蚀顺序。
综上所述,虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当随附的权利要求范围所界定的为准。
Claims (19)
1.一种方法,用以使用于一集成电路装置,包括一由多个介电/导电层形成的叠层,以形成多个层间连接件,该多个层间连接件自该集成电路装置的一表面延伸至该多个导电层,该方法包括:
建立分隔的多个接触开口于该集成电路装置的一接触区域内,而贯穿一介电层并以一介电层材料分隔各该接触开口,该多个接触开口位于一导电层上,用于W个该多个导电层的每一个;
该多个接触开口的该建立步骤包括向下建立一第一接触开口至一第一导电层;
利用一组N个刻蚀掩模,2N-1小于W且2N大于或等于W,该多个刻蚀掩模具有多个掩模区及分隔的多个开放刻蚀区,该多个开放刻蚀区对应于选择的该多个接触开口;
利用N个该多个刻蚀掩模来刻蚀由该多个介电/导电层形成的该叠层,以仅贯穿W-1个该多个接触开口而建立多个延伸接触开口,该多个延伸接触开口延伸至W-1个该多个导电层;
该刻蚀步骤包括利用各该刻蚀掩模来透过至少半数的该多个接触开口而刻蚀2n-1个该多个导电层,n=1、2...N;
该刻蚀步骤是执行,使得该多个接触开口是以该多个刻蚀掩模的不同组合的该多个开放刻蚀区来进行刻蚀;以及
形成该多个层间连接件于该第一接触开口内及该多个延伸接触开口内,以电性连接于各该导电层。
2.根据权利要求1所述的方法,其中:
该多个接触开口的该建立步骤是建立具有多个深度所形成的一范围的该多个接触开口,从一最深接触开口至一最浅接触开口;
该最深接触开口于该介电层的一上表面的截面积较该最浅接触开口于该第一导电层的截面积大0-400%。
3.根据权利要求1所述的方法,其中:
该多个接触开口的该建立步骤是建立具有多个深度所形成的一范围的该多个接触开口,从一最深接触开口至一最浅接触开口;
该最深接触开口于该介电层的一上表面的截面积较该最浅接触开口于该第一导电层的截面积大0-100%。
4.根据权利要求1所述的方法,其中该建立步骤是执行且N个该多个刻蚀掩模被配置,使得围绕在该多个接触开口的周围的该介电层材料不受影响。
5.根据权利要求1所述的方法,其中该多个刻蚀掩模的该使用步骤及该刻蚀步骤是执行,使得该多个接触开口与该多个延伸接触开口具有相似的周边形状。
6.根据权利要求1所述的方法,其中该多个接触开口的该建立步骤包括形成该多个接触开口来贯穿该包括一介电层间及一刻蚀停止层的介电层。
7.根据权利要求1所述的方法,其中:
该第一接触开口未在该刻蚀步骤中进行刻蚀;
三个该多个刻蚀掩模被使用来刻蚀一第二接触开口,以贯穿七层该多个导电层,n=1、2及3;
一个该刻蚀掩模被使用来刻蚀一第三接触开口,以贯穿一层该导电层,n=1;
两个该多个刻蚀掩模被使用来刻蚀一第四接触开口,以贯穿六层该多个导电层,n=2及3;
一个该刻蚀掩模被使用来刻蚀一第五接触开口,以贯穿两层该多个导电层,n=2;
两个该多个刻蚀掩模被使用来刻蚀一第六接触开口,以贯穿五层该多个导电层,n=1及3;
两个该多个刻蚀掩模被使用来刻蚀一第七接触开口,以贯穿三层该多个导电层,n=1及2;以及
1个该刻蚀掩模被使用来刻蚀一第八触开口,以贯穿四层该多个导电层,n=3。
8.根据权利要求1所述的方法,其中:
W=8且N=3。
9.根据权利要求7所述的方法,其中:
该第一接触开口至该第八接触开口是以数字的顺序排列,使得该第二接触开口位于该第一接触开口与该第三接触开口之间,该第三接触开口位于该第二接触开口与该第四接触开口之间,以此类推。
10.根据权利要求1所述的方法,其中:
该多个接触开口的该刻蚀步骤是执行,使得至少部分的该多个层间连接件终结于位在至少与相邻的该多个层间连接件所终结的该多个导电层距离至少两个阶层的位置的该多个导电层。
11.根据权利要求1所述的方法,其中该刻蚀步骤是执行,使得:
该多个层间连接件具有由多个深度所形成的一范围,从多个较大深度至多个平均深度至多个较浅深度;
具有该较大深度的一第一层间连接件相邻于具有该较浅深度的一第二层间连接件;
具有该多个平均深度的一第三层间连接件与一第四层间连接件彼此相邻。
12.根据权利要求11所述的方法,其中该刻蚀步骤是执行,使得该第一层间连接件具有一最大深度,且该第二层间连接件具有一最浅深度。
13.根据权利要求11所述的方法,其中该刻蚀步骤是执行,使得:
二个具有两个最大深度的该多个层间连接件不彼此相邻;及
二个具有两个最浅深度的该多个层间连接件不彼此相邻。
14.根据权利要求11所述的方法,其中该多个接触开口的该建立步骤包括定位该多个接触开口,使得该多个层间连接件彼此分隔一固定间隔。
15.根据权利要求1所述的方法,其中该多个接触开口的该建立步骤包括定位该多个接触开口,使得该多个层间连接件彼此分隔一固定间隔。
16.一种集成电路装置,包括:
一由交替的多个介电层与多个导电层的叠层,该多个导电层包括一上导电层与一下导电层;
一上层,位于该上导电层上,该上层具有一上表面;
多个层间连接件,自该上层的该上表面延伸至该多个导电层的每一个,以电性接触,该多个层间连接件包括一第一层间连接件、一第二层间连接件、一第三层间连接件与一第四层间连接件;
该多个层间连接件彼此分隔一平均的间隔;
该多个层间连接件具有由多个深度所形成的一范围,该多个深度从多个较大深度至多个平均深度至多个较浅深度;
具有该较大深度的该第一层间连接件相邻于具有该较浅深度的该第二层间连接件;
具有概括的该多个平均深度的该第三层间连接件与该第四层间连接件彼此相邻。
17.根据权利要求16所述的集成电路装置,其中在该多个层间连接件中,该第一层间连接件具有最大深度,且该第二层间连接件具有最浅深度。
18.根据权利要求16所述的集成电路装置,其中:
二个具有两个最大深度的该多个层间连接件不彼此相邻;及
二个具有两个最浅深度的该多个层间连接件不彼此相邻。
19.根据权利要求16所述的集成电路装置,其中位于相邻的该多个层间连接件之间的该间隔为一固定间隔。
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TW201405705A (zh) | 2014-02-01 |
US8633099B1 (en) | 2014-01-21 |
TWI487066B (zh) | 2015-06-01 |
KR20140011903A (ko) | 2014-01-29 |
US20140021628A1 (en) | 2014-01-23 |
JP5801782B2 (ja) | 2015-10-28 |
CN103579093B (zh) | 2016-12-28 |
JP2014022717A (ja) | 2014-02-03 |
KR101939146B1 (ko) | 2019-04-10 |
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