CN103531536A - 部件以及使用超薄载体制造部件的方法 - Google Patents

部件以及使用超薄载体制造部件的方法 Download PDF

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CN103531536A
CN103531536A CN201310280719.0A CN201310280719A CN103531536A CN 103531536 A CN103531536 A CN 103531536A CN 201310280719 A CN201310280719 A CN 201310280719A CN 103531536 A CN103531536 A CN 103531536A
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carrier
parts
metal pattern
metal
substrate
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K.迈尔
E.纳佩施尼希
M.平措利茨
M.勒斯纳
M.斯特纳
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及部件以及使用超薄载体制造部件的方法。公开了一种用于制造封装部件的系统和方法。实施例包括:在载体上形成多个部件,所述多个部件通过所述载体的正侧上的切口区域而与彼此分离;以及在所述载体的背侧上形成金属图案,其中,所述金属图案覆盖所述载体的除与所述切口区域相对应的区域之上外的背侧。所述方法进一步包括通过分离所述载体来生成所述部件。

Description

部件以及使用超薄载体制造部件的方法
技术领域
本发明的实施例一般地涉及一种制造部件的方法,并且在特定实施例中,涉及使用超薄晶片制造部件的方法。
背景技术
加工超薄晶片是困难的,这是由于在切块期间,其比常规晶片更容易破碎。此外,分离的芯片可能在拾取工艺期间或者在被引线键合时破碎。
发明内容
根据本发明的实施例,一种用于制造部件的方法包括:在载体上形成多个部件,所述多个部件通过所述载体的正侧上的切口区域而与彼此分离;以及在所述载体的背侧上形成金属图案,其中,所述金属图案覆盖所述载体的除与所述切口区域相对应的区域之上外的背侧。所述方法进一步包括通过分离所述载体来生成所述部件。
根据本发明的实施例,一种用于制造部件的方法包括:在载体上形成多个部件;以及在所述载体的背侧上形成金属图案,所述金属图案包括通过空间而分离的独立的金属块。所述方法进一步包括:通过沿所述空间分离所述载体来形成所述部件。
根据本发明的实施例,一种用于制造晶片的方法包括:在所述晶片的第一主表面上形成切口区域和芯片;以及在所述晶片的第二主表面上形成金属图案,其中,所述金属图案覆盖所述晶片的除与所述切口区域相对应的区域之上外的第二主表面。
根据本发明的实施例,一种封装半导体器件,包括载体和在所述载体上布置的部件,所述部件包括具有约20 μm或更小的厚度的衬底和包括约20 μm或更大的厚度的金属块。所述封装半导体器件进一步包括;连接层,将所述载体和所述部件相连接;以及导线或导电夹,将所述部件的部件接触焊盘与所述载体的载体接触焊盘相连接。所述封装半导体器件最后包括密封所述部件的密封物。
附图说明
为了更全面地理解本发明及其优势,现在对结合附图作出的以下描述进行参照,在附图中:
图1示出了用于制造部件封装的方法的实施例的流程图;
图2示出了载体的背侧上的图案化的光致抗蚀剂的顶表面的实施例;
图3a示出了载体的背侧上的图案化的金属层的顶表面的实施例;
图3b示出了载体的背侧上的图案化的金属层的横截面的实施例;
图4示出了在背侧上具有金属块的切割部件的实施例;
图5a示出了在背侧上包括金属块的封装部件的实施例;
图5b示出了在背侧上包括金属块的封装部件的实施例;
图6a示出了背侧金属图案布置的实施例;以及
图6b示出了背侧金属图案布置的实施例。
具体实施方式
以下详细地讨论目前优选实施例的作出和使用。然而,应当意识到,本发明提供了可在多种多样的特定上下文中体现的许多适用的发明构思。所讨论的特定实施例仅示意了用于作出和使用本发明的特定方式,而不限制本发明的范围。
将在特定上下文(即,薄晶片加工方法和器件)中关于实施例描述本发明。然而,本发明还可以适用于其他载体加工方法和器件。
典型地,传统晶片和芯片的安全且有把握的加工针对晶片或芯片的衬底需要约60 μm或更大的硅厚度。在低于该厚度处对晶片或芯片的加工是困难的,这是由于在前端和后端工艺中存在严重的处理问题。例如,当从锯箔(拾取)移除芯片时,这些芯片可能由于其薄硅衬底而破碎或断裂。此外,当芯片被引线键合时,其可能由于对芯片施加的机械压力和超声而破碎或破裂。可能经受所加工的芯片的100%损耗。
本发明的实施例提供了超薄载体和部件的机械稳定化。本发明的实施例进一步提供了部件的背侧上的极好的电和热接触。本发明的实施例提供了针对部件的无空隙的背侧接触。部件和载体的机械稳定化的优势是具有超薄衬底的部件和载体的可靠处理。具有超薄衬底的部件的另一优势是:相对于具有常规大小的衬底的部件,改进了电和热参数。例如,由于更薄的衬底,可以减小部件的电阻。
图1示出了用于制造封装电气部件的方法的实施例的流程图100。在第一步骤110中,在支撑载体上安装载体。该载体可以是工件、衬底、晶片或印刷电路板(PCB)。
该载体可以是半导体衬底(诸如硅或锗)或化合物衬底(诸如SiGe、GaAs、InP、GaN或SiC)。可替换地,该载体包括其他材料。衬底可以是单晶硅或绝缘体上硅(SOI)。衬底可以是掺杂的或无掺杂的。
可以在载体上布置一个或多个互连镀金属层。在互连镀金属层上布置钝化层,从而形成载体的顶表面或第一主表面。该钝化层可以对载体的部件的部件接触部或部件接触焊盘进行电隔离和结构化。例如,该钝化层可以包括SiN。第一主表面位于载体的正侧上。载体包括底表面或第二主表面。第二主表面位于载体的背侧上。
在一个实施例中,第一主表面是在其中主导地布置有源区的表面,并且第二主表面是无有源区或主导地无有源区的表面。
载体包括多个部件,诸如芯片或管芯。部件可以包括分立器件(诸如单个半导体器件)或集成电路(IC)。例如,部件可以包括功率半导体器件,诸如双极晶体管、绝缘栅双极晶体管(IGBT)、功率MOSFET、晶闸管或二极管。可替换地,例如,部件可以是电阻器、保护器件、电容器、传感器或检测器。
载体包括对部件进行分离和结构化的切口、切口线或切口区域。沿切口线将载体分离、切割或切削为单个部件。载体包括沿x方向和沿y方向的切口线的网格或图案。切口线是下述区域:沿着该区域,部件与彼此分离。
载体可以被附着至支撑载体。支撑载体可以是玻璃载体。可替换地,支撑载体可以是半导体载体,诸如硅载体。在一个实施例中,载体的第一主表面被胶合至玻璃载体,使得载体的第二主表面被暴露。
在步骤115中,使载体变薄,即,减小载体的背侧的厚度。例如,使衬底变薄至约小于约40 μm的厚度或变薄至约小于约20 μm的厚度。可替换地,使衬底变薄至约10 μm到约20 μm的厚度。可以通过研磨或砂轮切削来使衬底变薄。可以不执行在将载体安装至支撑载体后移除过多胶残渣的汞清洗,这是由于清洗步骤可能在研磨期间导致部件的边缘破碎。
在步骤120中,使载体平滑并对载体进行清洗。例如,应用湿法蚀刻(诸如HNO3)来使载体平滑,并应用水清洗来清洗载体。
在步骤125中,执行可选的应力松弛。该应力松弛可以是有利的,这是由于衬底厚度(在变薄后)可以处于与载体的正侧上的互连镀金属层相同或相似的尺寸范围内并且衬底和互连镀金属层的CTE不同。可以应用冰冻工艺来执行该应力松弛。例如,可以在约-70℃的温度处执行冰冻工艺。
在步骤130中,将载体的背侧与载体的正侧对准。在一个实施例中,在载体的背侧上对正侧对准标记进行拷贝、成像、映射或再现。可替换地,将载体的背侧与正侧对准标记进行对准。例如,可以通过“看穿(seeing through)”载体的衬底来对准载体。
在步骤135中,可选地,在载体的背侧上形成下层。该下层可以是金属层。例如,该下层可以是铝(Al)或铝合金、钛(Ti)或钛合金或者其组合。可替换地,该下层可以包括铜(Cu)、镍钒(NiV)或银(Ag)。该下层可以是层堆叠。例如,该下层可以包括与载体相邻的第一层和在第一层上布置的第二层。第一层可以是粘附层,并且第二层可以是阻挡层。在一个示例中,第一层包括铝或铝合金(例如,200 nm厚),并且第二层包括钛或钛合金(例如,200 nm厚)。可以通过溅射来形成该下层。可替换地,可以使用其他沉积工艺,诸如物理气相沉积(PVD)、化学气相沉积(CVD)或蒸发。
在该下层之上形成种子层。种子层可以是金属层。例如,种子层可以是铝(Al)或铝合金、铜(Cu)或铜合金或者其组合。可以通过溅射来形成种子层。可替换地,可以使用其他沉积工艺,诸如物理气相沉积(PVD)、化学气相沉积(CVD)或蒸发。在一个实施例中,在低温处(例如,在约100℃的温度处)执行溅射。在一个实施例中,在单个工艺中形成下层和种子层,从而形成提供接触、阻挡和种子层的层堆叠。
在步骤140中,在种子层之上形成光致抗蚀剂。可以通过旋涂来形成光致抗蚀剂。光致抗蚀剂可以是实现比约20 μm更大的抗蚀剂厚度的抗蚀剂。然后,在步骤145中,对光致抗蚀剂进行图案化和显影。在一个实施例中,对光致抗蚀剂进行图案化和显影,使得光致抗蚀剂图案对载体的正侧上的切口区域或切口线进行镜像或映射。在部件的背侧之上移除光致抗蚀剂,并且光致抗蚀剂保持存在于切口区域或切口线之上。在一个实施例中,光致抗蚀剂的图案化形成光致抗蚀剂脊状物、鳍状物或条状物。脊状物、鳍状物或条状物可以包括框架或交叉状条状物的形式。脊状物、鳍状物或条状物可以包括正方形或矩形的周缘的形式。可替换地,脊状物、鳍状物或条状物可以包括其他形式。在一个实施例中,光致抗蚀剂的被移除的部分可以包括嵌板(panel)、正方形、矩形、格子或块的形式。可替换地,光致抗蚀剂的被移除的部分可以包括其他形式。图2示出了载体的背侧上的光致抗蚀剂图案的实施例的细节。光致抗蚀剂脊状物、鳍状物或条状物210保持存在,而从区域220移除光致抗蚀剂。在一个实施例中,脊状物、鳍状物或条状物210包括沿x方向和沿y方向的相同厚度d1。可以对载体进行清洗,以移除不必要的有机沉积。例如,可以利用O2等离子来对载体进行清洗。
在步骤150中,形成金属图案。在一个实施例中,通过流电电镀来形成金属图案或金属层。将载体浸没在金属浴中,并且从光致抗蚀剂脊状物、鳍状物和条状物之间的种子层以及在该种子层之上电镀金属图案(金属块)。例如,将载体浸没在铜(Cu)浴中。通过将载体留在金属浴中预定时间来调整金属厚度。例如,铜块的金属厚度可以是约20 μm至约50 μm或者约20 μm至约100 μm。金属块可以比部件的衬底更厚。在一个实施例中,当金属块不仅被配置为电接触部而且被配置为散热片时,金属比衬底更厚。
电镀工艺的优势是:可以在相比之下较短的时间段中形成厚金属图案。另一优势是:电镀工艺提供了无空隙的金属块和与部件载体的无空隙的界面。
图3a示出了载体的背侧上的金属图案或金属层(例如,铜)的实施例的顶视图的细节。金属块320通过抗蚀剂脊状物、条状物或鳍状物310而与彼此分隔开。图3b示出了载体的背侧上的金属图案的横截面视图的细节。抗蚀剂脊状物、鳍状物或条状物310被放置在衬底300之上的金属块320之间。种子层和/或下层可以被布置在衬底300与抗蚀剂条状物/金属块310、320之间。
在实施例中,通过其他快速沉积工艺来形成金属图案。例如,可以通过应用喷墨式打印机的丝网印刷工艺或者孔版印刷工艺来形成金属图案。
在步骤155中,移除其余光致抗蚀剂层。例如,移除光致抗蚀剂框架或者光致抗蚀剂脊状物、鳍状物或条状物。通过有机液体介质来移除光致抗蚀剂。
在步骤160中,将支撑载体和载体放置在切块箔上。然后,从载体移除支撑载体。在步骤165中,从载体分离、切割或切削部件。在一个实施例中,使用切块激光器来切割载体。在一个实施例中,应用将金属块用作硬掩模的等离子蚀刻来切割载体。可替换地,使用切块锯来切割载体。在图4中示出了具有背侧金属420的部件410的细节的实施例。图4示出了部件410的周缘与背侧金属块420的周缘之间的边沿或间隙430的距离d。在一个实施例中,有利的是,距离d2尽可能小,例如在约5 μm与约0 μm之间。
在步骤170中,在部件载体上翻转和组装分离的个体部件。部件载体可以是工件、衬底、晶片或印刷电路板(PCB)。在一个实施例中,部件载体是包括诸如铜(Cu)或铜合金、镍(Ni)或镍合金、银(Ag)或银合金或者其组合之类的金属的引线框。
在部件放置区处将部件附着至部件载体。例如,将部件的背侧上的金属层或金属块附着至部件载体的顶表面。在一个实施例中,使用焊接、共晶键合或环氧键合将金属层键合至部件载体的顶表面。可替换地,使用粘附带、焊膏或焊料将第二主表面键合或胶合至载体的顶表面。在一个实施例中,部件与部件载体之间的连接是电连接。可替换地,该连接是绝缘阻挡层。
在步骤175中,将部件键合至部件载体。例如,将在部件的顶表面或第一主表面上布置的部件接触部或部件接触焊盘键合至部件载体的部件载体接触部或部件载体接触焊盘。将部件的接触部引线键合、球形键合、夹键合或以其他方式键合至部件载体的接触部。引线或导电夹包括诸如铝(Al)、铜(Cu)、银(Ag)或金(Au)之类的金属。
例如,将在部件的第一主表面上布置的第一部件接触部电连接至第一部件载体接触部。该部件可以进一步在第一主表面上包括第二部件接触部和/或第三部件接触部。可替换地,该部件可以在其第一主表面上具有其他接触焊盘布置。
在步骤180处,利用模塑料(molding compound)来密封部件。在一个实施例中,密封材料可以是模塑料。模塑料可以包括热固材料或热塑材料。模塑料可以包括粗颗粒材料。在一个实施例中,可以应用模塑料来密封部件以及部件载体的至少部分。可替换地,密封材料可以是诸如预浸材料之类的层压材料。
可选地,当多个部件被放置在部件载体上时,可以将密封的部件/部件载体切块成封装电气部件,每个封装电气部件包括部件。例如,使用切块锯来切割个体封装电气部件。
图5a示出了包括具有厚度d3的部件500和具有厚度d4的金属块540的封装电气部件,其中,d3基本上与d4相同。金属块(例如,铜)540可以被焊接至部件载体(例如,引线框)590。经由引线或导电夹514将部件500的一个或多个部件接触焊盘512连接至部件载体590的一个或多个部件载体接触焊盘592。
图5b示出了包括具有厚度d5的部件500和具有厚度d6的金属块540的封装电气部件,其中,d6基本上比d5大。金属块540可以包括散热片。金属块(例如,铜)540可以被焊接至部件载体(例如,引线框)590。经由引线或导电夹514将部件500的一个或多个部件接触焊盘512连接至部件载体590的一个或多个部件载体接触焊盘592。
图6a示出了处于翻转位置的背侧金属图案布置600。晶片610被胶合或连接至玻璃载体620。晶片610在其正侧上被连接至玻璃载体620。在该实施例中,对准标记被布置在晶片610的其背侧上。种子层或者种子层与下层一起630被布置为直接与晶片610相邻。种子层(与下层一起)630可以包括金属层堆叠。种子层630可以覆盖晶片610的整个背侧。金属图案640(例如,铜)被布置在晶片610的背侧上的种子层/下层之上。晶片(例如,晶片的衬底)610包括厚度d7,并且金属图案640包括厚度d8。厚度d8比厚度d7大。金属图案640由抗蚀剂图案650进行结构化。
图6b示出了在其被放置在切块箔660之后的背侧金属图案布置600。已经移除抗蚀剂图案650和玻璃载体620。图6b示出了背侧金属图案布置600,其中,金属块640被空间或气隙670分离。空间或气隙670替换被移除的抗蚀剂图案650。如图6b所示,在空间或气隙670中且沿空间或气隙670、利用切削工具680来切削晶片610。切削工具680切削穿过晶片610和下层/种子层630,但不穿过金属图案/块640。切削工具680可以是切块激光器。
尽管已经详细地描述本发明及其优势,但是应当理解的是,在不脱离如所附权利要求限定的本发明的精神和范围的前提下,可以在本发明中进行各种改变、替代和更改。
此外,本申请的范围并不意在被限于说明书中描述的工艺、机器、制造、物质组成、装置、方法和步骤的特定实施例。如本领域技术人员将容易地从本发明的公开中意识到的那样,根据本发明,可以利用执行与本文描述的对应实施例基本上相同的功能或实现与本文描述的对应实施例基本上相同的结果的、目前存在或后续开发的工艺、机器、制造、物质组成、装置、方法或步骤。相应地,所附权利要求意图在其范围内包括这种工艺、机器、制造、物质组成、装置、方法或步骤。 

Claims (20)

1.一种用于制造部件的方法,所述方法包括:
形成在载体上布置的多个部件,所述多个部件通过所述载体的正侧上的切口区域而与彼此分离;
在所述载体的背侧上形成金属图案,其中,所述金属图案覆盖所述载体的除与所述切口区域相对应的区域之上外的背侧;以及
将所述部件与所述载体分离。
2.根据权利要求1所述的方法,其中,形成金属图案包括:形成金属种子层;形成图案化的抗蚀剂掩模;以及对所述金属图案进行电镀。
3.根据权利要求2所述的方法,进一步包括:在种子层与所述部件的衬底之间形成下层,其中,所述下层包括金属粘附层和金属阻挡层。
4.根据权利要求3所述的方法,其中,所述金属图案包括铜Cu。
5.根据权利要求1所述的方法,其中,所述部件的衬底以及所述金属图案包括大约相同的厚度。
6.根据权利要求1所述的方法,其中,所述部件的衬底包括约20 μm或更小的厚度,以及其中,所述金属图案包括约20 μm或更大的厚度。
7.根据权利要求1所述的方法,其中,将所述部件与所述载体分离包括沿所述区域对所述载体进行激光切削。
8.一种用于制造部件的方法,所述方法包括:
在载体上形成多个部件;
在所述载体的背侧上形成金属图案,所述金属图案包括被空间分离的自立的金属块;以及
沿所述空间将所述部件与所述载体分离。
9.根据权利要求8所述的方法,其中,形成金属图案包括:形成金属种子层;形成图案化的抗蚀剂掩模;以及对所述金属图案进行电镀。
10.根据权利要求9所述的方法,进一步包括:在所述金属种子层与所述部件的衬底之间形成下层,其中,所述下层包括铝和钛的金属层堆叠,以及其中,所述种子层层包括与所述金属图案相同的材料。
11.根据权利要求10所述的方法,其中,所述部件的衬底包括约20 μm或更小的厚度,以及其中,所述金属图案包括约20 μm或更大的厚度。
12.根据权利要求11所述的方法,其中,将所述部件与所述载体分离包括对所述载体进行激光切削。
13.根据权利要求11所述的方法,进一步包括:将所述部件放置在引线框上;以及对所述部件以及所述引线框的至少一部分进行密封。
14.根据权利要求13所述的方法,其中,将所述部件放置在引线框上包括:将所述部件引线键合或夹键合至所述引线框。
15.一种制造晶片的方法,所述方法包括:
在所述晶片的第一主表面上形成切口区域和芯片;以及
在所述晶片的第二主表面上形成金属图案,其中,所述金属图案覆盖所述晶片的除与所述切口区域相对应的区域之上外的第二主表面。
16.根据权利要求15所述的方法,其中,所述金属图案包括铜Cu。
17.根据权利要求15所述的方法,其中,形成金属图案包括:在所述晶片的第二主表面之上形成种子层;在所述种子层之上对光致抗蚀剂进行图案化;以及在金属浴中形成所述金属图案。
18.一种封装半导体器件,包括:
载体;
在所述载体上布置的部件,所述部件包括具有约20 μm或更小的厚度的衬底和包括约20 μm或更大的厚度的金属块;
连接层,将所述载体和所述部件相连接;
导线或导电夹,将所述部件的部件接触焊盘与所述载体的载体接触焊盘相连接;以及
密封物,密封所述部件。
19.根据权利要求18所述的封装半导体器件,其中,所述金属块是铜块。
20.根据权利要求19所述的封装半导体器件,其中,所述连接层是焊膏。
CN201310280719.0A 2012-07-05 2013-07-05 部件以及使用超薄载体制造部件的方法 Pending CN103531536A (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336718A (zh) * 2014-08-04 2016-02-17 英飞凌科技股份有限公司 源极向下半导体器件及其制造方法
CN107507767A (zh) * 2016-06-14 2017-12-22 英飞凌科技股份有限公司 碳化硅的等离子体切割
CN111489965A (zh) * 2019-01-25 2020-08-04 半导体元件工业有限责任公司 部分背面金属移除切割系统及相关方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303978B1 (en) * 2000-07-27 2001-10-16 Motorola, Inc. Optical semiconductor component and method of manufacture
CN1839470A (zh) * 2003-09-19 2006-09-27 霆激科技股份有限公司 半导体器件上导电金属层的制作
US20080003720A1 (en) * 2006-06-30 2008-01-03 Daoqiang Lu Wafer-level bonding for mechanically reinforced ultra-thin die
CN101150157A (zh) * 2006-09-22 2008-03-26 亿光电子工业股份有限公司 高导热发光二极管封装结构
US20100276706A1 (en) * 2007-06-29 2010-11-04 Osram Opto Semiconductors Gmbh Method for the Production of a Plurality of Optoelectronic Components, and Optoelectronic Component

Family Cites Families (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2666788B2 (ja) * 1995-10-19 1997-10-22 日本電気株式会社 チップサイズ半導体装置の製造方法
DE19980448D2 (de) * 1998-03-14 2004-12-09 Andreas Jakob Verfahren und Vorrichtung zum Behandeln von Wafern mit Bauelementen beim Abdünnen des Wafers und beim Vereinzeln der Bauelemente
JP2003533030A (ja) * 2000-04-26 2003-11-05 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング GaNをベースとする発光ダイオードチップおよび発光ダイオード構造素子の製造法
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US8294172B2 (en) * 2002-04-09 2012-10-23 Lg Electronics Inc. Method of fabricating vertical devices using a metal support film
US6808960B2 (en) * 2002-10-25 2004-10-26 Omni Vision International Holding Ltd Method for making and packaging image sensor die using protective coating
US7008861B2 (en) * 2003-12-11 2006-03-07 Cree, Inc. Semiconductor substrate assemblies and methods for preparing and dicing the same
US20050151268A1 (en) * 2004-01-08 2005-07-14 Boyd William D. Wafer-level assembly method for chip-size devices having flipped chips
US7154186B2 (en) * 2004-03-18 2006-12-26 Fairchild Semiconductor Corporation Multi-flip chip on lead frame on over molded IC package and method of assembly
US7202141B2 (en) * 2004-03-29 2007-04-10 J.P. Sercel Associates, Inc. Method of separating layers of material
US7830006B2 (en) * 2004-05-06 2010-11-09 United Test And Assembly Center, Ltd. Structurally-enhanced integrated circuit package and method of manufacture
US8728937B2 (en) * 2004-07-30 2014-05-20 Osram Opto Semiconductors Gmbh Method for producing semiconductor chips using thin film technology
EP1774599B1 (de) * 2004-07-30 2015-11-04 OSRAM Opto Semiconductors GmbH Verfahren zur herstellung von halbleiterchips in dünnfilmtechnik und halbleiterchip in dünnfilmtechnik
US8318519B2 (en) * 2005-01-11 2012-11-27 SemiLEDs Optoelectronics Co., Ltd. Method for handling a semiconductor wafer assembly
JP4338650B2 (ja) * 2005-01-12 2009-10-07 パナソニック株式会社 半導体チップの製造方法
EP1844495B1 (en) * 2005-01-24 2011-07-27 Panasonic Corporation Manufacturing method for semiconductor chips
JP4275096B2 (ja) * 2005-04-14 2009-06-10 パナソニック株式会社 半導体チップの製造方法
JP4288252B2 (ja) * 2005-04-19 2009-07-01 パナソニック株式会社 半導体チップの製造方法
WO2007099146A1 (de) * 2006-03-01 2007-09-07 Jakob + Richter Ip-Verwertungsgesellschaft Mbh Verfahren zum bearbeiten insbesondere dünnen der rückseite eines wafers, wafer-träger-anordnung hierfür und verfahren zur herstellung einer solchen wafer-träger-anordnung
JP5165207B2 (ja) * 2006-03-29 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
US8022552B2 (en) * 2006-06-27 2011-09-20 Megica Corporation Integrated circuit and method for fabricating the same
US8421227B2 (en) * 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
JP5023614B2 (ja) * 2006-08-24 2012-09-12 パナソニック株式会社 半導体チップの製造方法及び半導体ウエハの処理方法
JP4544231B2 (ja) * 2006-10-06 2010-09-15 パナソニック株式会社 半導体チップの製造方法
US7655527B2 (en) * 2006-11-07 2010-02-02 Infineon Technologies Austria Ag Semiconductor element and process of manufacturing semiconductor element
US7841075B2 (en) * 2007-06-19 2010-11-30 E. I. Du Pont De Nemours And Company Methods for integration of thin-film capacitors into the build-up layers of a PWB
US8859396B2 (en) * 2007-08-07 2014-10-14 Semiconductor Components Industries, Llc Semiconductor die singulation method
US8585915B2 (en) * 2007-10-29 2013-11-19 Micron Technology, Inc. Methods for fabricating sub-resolution alignment marks on semiconductor structures
JP4539773B2 (ja) * 2008-03-07 2010-09-08 株式会社デンソー 半導体装置およびその製造方法
US8375577B2 (en) * 2008-06-04 2013-02-19 National Semiconductor Corporation Method of making foil based semiconductor package
KR100993342B1 (ko) * 2008-09-03 2010-11-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
SG162633A1 (en) * 2008-12-22 2010-07-29 Helios Applied Systems Pte Ltd Integrated system for manufacture of sub-micron 3d structures using 2-d photon lithography and nanoimprinting and process thereof
US8865522B2 (en) * 2010-07-15 2014-10-21 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a glass substrate
US8202786B2 (en) * 2010-07-15 2012-06-19 Infineon Technologies Austria Ag Method for manufacturing semiconductor devices having a glass substrate
JP5675504B2 (ja) * 2010-08-06 2015-02-25 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び半導体装置の製造方法
US8389334B2 (en) * 2010-08-17 2013-03-05 National Semiconductor Corporation Foil-based method for packaging intergrated circuits
US8580100B2 (en) * 2011-02-24 2013-11-12 Massachusetts Institute Of Technology Metal deposition using seed layers
US20120288698A1 (en) * 2011-03-23 2012-11-15 Advanced Diamond Technology, Inc Method of fabrication, device structure and submount comprising diamond on metal substrate for thermal dissipation
US20120273935A1 (en) * 2011-04-29 2012-11-01 Stefan Martens Semiconductor Device and Method of Making a Semiconductor Device
JP5888995B2 (ja) * 2012-01-16 2016-03-22 三菱電機株式会社 半導体装置およびその製造方法
US8816495B2 (en) * 2012-02-16 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structures and formation methods of packages with heat sinks
US8803302B2 (en) * 2012-05-31 2014-08-12 Freescale Semiconductor, Inc. System, method and apparatus for leadless surface mounted semiconductor package
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier
US9034733B2 (en) * 2012-08-20 2015-05-19 Semiconductor Components Industries, Llc Semiconductor die singulation method
US8664089B1 (en) * 2012-08-20 2014-03-04 Semiconductor Components Industries, Llc Semiconductor die singulation method
US8987057B2 (en) * 2012-10-01 2015-03-24 Nxp B.V. Encapsulated wafer-level chip scale (WLSCP) pedestal packaging
US20140110826A1 (en) * 2012-10-23 2014-04-24 Nxp B.V. Backside protection for a wafer-level chip scale package (wlcsp)
US9245804B2 (en) * 2012-10-23 2016-01-26 Nxp B.V. Using a double-cut for mechanical protection of a wafer-level chip scale package (WLCSP)
US8946894B2 (en) * 2013-02-18 2015-02-03 Triquint Semiconductor, Inc. Package for high-power semiconductor devices
US9548247B2 (en) * 2013-07-22 2017-01-17 Infineon Technologies Austria Ag Methods for producing semiconductor devices
CN103489792B (zh) * 2013-08-06 2016-02-03 江苏长电科技股份有限公司 先封后蚀三维系统级芯片倒装封装结构及工艺方法
US9293409B2 (en) * 2013-09-11 2016-03-22 Infineon Technologies Ag Method for manufacturing a semiconductor device, and semiconductor device
US8906745B1 (en) * 2013-09-12 2014-12-09 Micro Processing Technology, Inc. Method using fluid pressure to remove back metal from semiconductor wafer scribe streets
EP2950338B1 (en) * 2014-05-28 2019-04-24 ams AG Dicing method for wafer-level packaging
US9472458B2 (en) * 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
CN105280567B (zh) * 2014-06-19 2018-12-28 株式会社吉帝伟士 半导体封装件及其制造方法
US9349670B2 (en) * 2014-08-04 2016-05-24 Micron Technology, Inc. Semiconductor die assemblies with heat sink and associated systems and methods
US9385041B2 (en) * 2014-08-26 2016-07-05 Semiconductor Components Industries, Llc Method for insulating singulated electronic die
CN109637934B (zh) * 2014-10-11 2023-12-22 意法半导体有限公司 电子器件及制造电子器件的方法
US9673096B2 (en) * 2014-11-14 2017-06-06 Infineon Technologies Ag Method for processing a semiconductor substrate and a method for processing a semiconductor wafer
US9704823B2 (en) * 2015-03-21 2017-07-11 Nxp B.V. Reduction of defects in wafer level chip scale package (WLCSP) devices
KR101843621B1 (ko) * 2015-12-04 2018-03-29 앰코테크놀로지코리아(주) 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
US10672664B2 (en) * 2016-03-01 2020-06-02 Infineon Technologies Ag Composite wafer, semiconductor device, electronic component and method of manufacturing a semiconductor device
US10373869B2 (en) * 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
DE102018101710A1 (de) * 2018-01-25 2019-07-25 Osram Opto Semiconductors Gmbh Optoelektronisches bauelement und verfahren zur herstellung eines optoelektronischen bauelements

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303978B1 (en) * 2000-07-27 2001-10-16 Motorola, Inc. Optical semiconductor component and method of manufacture
CN1839470A (zh) * 2003-09-19 2006-09-27 霆激科技股份有限公司 半导体器件上导电金属层的制作
US20080003720A1 (en) * 2006-06-30 2008-01-03 Daoqiang Lu Wafer-level bonding for mechanically reinforced ultra-thin die
CN101150157A (zh) * 2006-09-22 2008-03-26 亿光电子工业股份有限公司 高导热发光二极管封装结构
US20100276706A1 (en) * 2007-06-29 2010-11-04 Osram Opto Semiconductors Gmbh Method for the Production of a Plurality of Optoelectronic Components, and Optoelectronic Component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336718A (zh) * 2014-08-04 2016-02-17 英飞凌科技股份有限公司 源极向下半导体器件及其制造方法
US9911686B2 (en) 2014-08-04 2018-03-06 Infineon Technologies Ag Source down semiconductor devices and methods of formation thereof
CN105336718B (zh) * 2014-08-04 2018-06-15 英飞凌科技股份有限公司 源极向下半导体器件及其制造方法
CN107507767A (zh) * 2016-06-14 2017-12-22 英飞凌科技股份有限公司 碳化硅的等离子体切割
CN107507767B (zh) * 2016-06-14 2020-12-01 英飞凌科技股份有限公司 碳化硅的等离子体切割
CN111489965A (zh) * 2019-01-25 2020-08-04 半导体元件工业有限责任公司 部分背面金属移除切割系统及相关方法

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