CN108538732B - 半导体器件以及制造半导体器件的方法 - Google Patents

半导体器件以及制造半导体器件的方法 Download PDF

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CN108538732B
CN108538732B CN201810158820.1A CN201810158820A CN108538732B CN 108538732 B CN108538732 B CN 108538732B CN 201810158820 A CN201810158820 A CN 201810158820A CN 108538732 B CN108538732 B CN 108538732B
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semiconductor die
semiconductor
bumps
forming
die
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CN108538732A (zh
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戈登·M·格里芙尼亚
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

本发明涉及半导体器件以及制造半导体器件的方法。本发明公开了一种半导体衬底，所述半导体衬底包含多个半导体管芯，在半导体管芯之间具有锯道。多个凸块在半导体管芯的第一表面上形成。绝缘层在所述半导体管芯的第一表面上在凸块之间形成。将所述半导体管芯的第二表面的一部分去除，并且在剩余的第二表面上形成导电层。将所述半导体衬底设置在切割胶带上，穿过锯道切割所述半导体衬底，同时维持所述半导体管芯的位置，并且使切割胶带扩张以赋予所述半导体管芯的移动并增加所述半导体管芯之间的空间。将密封剂沉积在所述半导体管芯上并且进入所述半导体管芯之间的空间。穿过所述密封剂在所述半导体管芯之间形成沟道以分离半导体管芯。

Description

半导体器件以及制造半导体器件的方法
技术领域
本发明整体涉及半导体器件，具体地讲涉及半导体器件以及形成晶圆级芯片尺寸封装(WLCSP)的方法，并且更具体地讲，涉及半导体器件以及制造半导体器件的方法。
背景技术
半导体晶圆或衬底可用各种基极衬底材料制成，诸如硅(Si)、锗、氮化铝(AlN)、砷化镓(GaAs)、氮化镓(GaN)、氮化铝镓/氮化镓(AlGaN/GaN)、磷化铟、碳化硅(SiC)、或用于结构支撑的其他基体材料。多个半导体管芯形成在晶圆上，通过非有源的管芯间衬底区域或锯道分开。锯道提供用以将半导体晶圆切割成单独半导体管芯的切割区域。
在一些情况下，将半导体管芯从半导体晶圆切割，然后单独封装以进行电互连和包封以实现环境隔离。对于小型通用技术半导体管芯，诸如小信号二极管，管芯级半导体封装成本通常显著大于管芯的成本。
为了降低封装成本，半导体管芯可以晶圆形式进行封装，例如以晶圆级芯片尺寸封装(WLCSP)进行封装。一旦处于封装形式，半导体管芯便与晶圆分离。WLCSP提供较低的成本，减小封装尺寸，并且增强导热特性。在WLCSP中，相邻半导体管芯之间的间距必须足够大以执行封装操作，例如在对于封装管芯的切割留下足够划线宽度的同时进行包封和电互连。
在一种已知的双包封WLCSP工艺中，在半导体管芯的有源表面上以晶圆形式形成多个凸块。通过宽锯片将沟道或沟槽部分地切割成管芯之间的半导体晶圆的划线中的基体衬底。将第一密封剂沉积在半导体管芯的有源表面上方并且进入沟道。通过研磨操作去除第一密封剂的一部分以暴露凸块。在研磨操作中，从与有源表面相对的背表面去除基极衬底材料的一部分以使晶圆变薄并使第一密封剂暴露在沟道中。将第二密封剂沉积在半导体管芯的背表面以及第一密封剂上方。然后切割包封的半导体管芯，将第一密封剂留在半导体管芯的侧表面上，并且将第二密封剂留在背表面上。双包封WLCSP工艺需要能接近管芯尺寸的大的管芯间间距，以及许多处理步骤。大的管芯间间距减小了每个晶圆的管芯产量，并增加了总体制造成本。
在另一个WLCSP中，将单个密封剂沉积在半导体管芯的背表面和侧表面上。单个包封WLCSP工艺仍然需要大的管芯间间距，以便在半导体管芯的侧表面上沉积密封剂。同样，大的管芯间间距减小了每个晶圆的管芯产量，并增加了总体制造成本。
发明内容
根据一个方面，提供一种制造半导体器件的方法，包括：提供半导体衬底，所述半导体衬底包括多个半导体管芯，在所述半导体管芯之间具有锯道；在所述半导体管芯的第一表面上形成多个凸块；在所述半导体管芯的所述第一表面上在所述凸块之间形成绝缘层；穿过所述锯道切割所述半导体衬底，同时维持所述半导体管芯的位置；赋予所述半导体管芯的移动以增加所述半导体管芯之间的空间；将密封剂沉积在所述半导体管芯上并且进入所述半导体管芯之间的所述空间；以及穿过所述密封剂在所述半导体管芯之间形成沟道以分离所述半导体管芯。
在一个示例中，所述方法还包括在所述半导体管芯的所述第一表面上并且围绕所述凸块形成所述绝缘层。
在一个示例中，所述方法还包括将所述密封剂沉积在所述半导体管芯的所述第一表面的一部分上。
在一个示例中，所述方法还包括去除所述半导体管芯的与所述半导体管芯的所述第一表面相对的第二表面的一部分。
在一个示例中，所述方法还包括：将所述半导体衬底沉积在切割胶带上；以及使所述切割胶带扩张以赋予所述半导体管芯的移动以增加所述半导体管芯之间的所述空间。
在一个示例中，所述半导体衬底上的第一半导体管芯与相邻的第二半导体管芯之间的第一距离大于所述半导体衬底上的所述第一半导体管芯与相邻的第三半导体管芯之间的第二距离。
根据另一方面，提供一种制造半导体器件的方法，包括：提供半导体衬底，所述半导体衬底包括多个半导体管芯；在所述半导体管芯的第一表面上形成多个凸块；在所述半导体管芯的所述第一表面上在所述凸块之间形成绝缘层；切割所述半导体管芯之间的所述半导体衬底；扩大所述半导体管芯之间的空间；将密封剂沉积在所述半导体管芯上并且进入所述半导体管芯之间的所述空间；以及穿过所述密封剂在所述半导体管芯之间形成沟道以分离所述半导体管芯。
在一个示例中，所述方法还包括在所述半导体管芯的所述第一表面上并且围绕所述凸块形成所述绝缘层。
在一个示例中，所述方法还包括将所述密封剂沉积在所述半导体管芯的所述第一表面的一部分上。
在一个示例中，所述方法还包括在所述半导体管芯的与所述半导体管芯的所述第一表面相对的第二表面上形成导电层。
根据又一方面，提供一种半导体器件，包括：多个半导体管芯，在所述半导体管芯之间具有空间；多个凸块，所述多个凸块在所述半导体管芯的第一表面上形成；绝缘层，所述绝缘层在所述半导体管芯的所述第一表面上在所述凸块之间形成；密封剂，所述密封剂沉积在所述半导体管芯上并且进入所述半导体管芯之间的所述空间；以及沟道，所述沟道在所述半导体管芯之间穿过所述密封剂。
在一个示例中，在所述半导体管芯的所述第一表面上并且围绕所述凸块形成所述绝缘层。
在一个示例中，所述密封剂沉积在所述半导体管芯的所述第一表面的一部分上。
在一个示例中，所述半导体器件还包括在所述半导体管芯的与所述半导体管芯的所述第一表面相对的第二表面上形成的导电层。
在一个示例中，所述半导体管芯之间的所述空间为至少75微米。
根据本发明的实施方案，能够增加每个晶圆的管芯产量并降低总体制造成本。
附图说明
图1a-图1c示出具有由锯道分开的多个半导体管芯的半导体衬底；
图2a-图2k示出以晶圆级封装半导体管芯的工艺；
图3a-图3b示出切割后WLCSP；
图4a-图4b示出WLCSP的实施方案，其中密封剂覆盖半导体管芯的有源表面的一部分；
图5a-图5j示出以晶圆级用背面导电层封装半导体管芯的工艺；并且
图6a-图6b示出具有切割后背面导电层的WLCSP。
具体实施方式
下文参照附图描述了一个或多个实施方案，其中类似的数字表示相同或相似的元件。虽然按照实现某些目标的最佳模式描述了附图，但描述旨在涵盖可包括在本公开的实质和范围内的替代形式、修改形式和等同形式。如本文使用的术语“半导体管芯”兼指该词语的单数形式和复数形式，并且相应地，可同时涉及单个半导体器件和多个半导体器件。
图1a示出具有基极衬底材料102的半导体晶圆或衬底100，该基极衬底材料诸如Si、锗、AlN、GaAs、GaN、AlGaN/GaN、磷化铟、SiC、或用于结构支撑的其他基体材料。半导体衬底100的宽度或直径为100-450毫米(mm)，并且厚度为约800微米(μm)。多个半导体管芯104形成在衬底100上，通过非有源的管芯间衬底区域或锯道106分开。锯道106提供用以将半导体衬底100切割成单独半导体管芯104的切割区域。在一个实施方案中，半导体管芯104的尺寸为195μm×400μm，并且锯道106的宽度为10-20μm。
图1b示出半导体衬底100的一部分。具体地讲，半导体管芯104a与半导体管芯104b之间的锯道106b的宽度大于半导体管芯104a与半导体管芯104c之间的锯道106a的宽度，以补偿切割胶带沿x方向和y方向的非线性扩张，如在图2g中进一步描述。在一个实施方案中，锯道106b的宽度为20μm，并且锯道106a的宽度为10μm。
图1c示出半导体衬底100的一部分的剖面图。每个半导体管芯104包括背表面108以及有源表面或区域110，该有源表面或区域包含模拟或数字电路，该模拟或数字电路实现为形成在管芯内并根据管芯的电学设计和功能电互连的有源器件、无源器件、导电层和介电层。例如，电路可包括形成在有源表面或区域110内的一个或多个晶体管、二极管和其他电路元件以实现模拟电路或数字电路。在一个实施方案中，半导体管芯104实现二极管、晶体管、或其他分立半导体器件。半导体管芯104还可包含数字信号处理器(DSP)、微控制器、ASIC、标准逻辑、放大器、时钟管理、存储器、接口电路、光电子器件，以及其他信号处理电路。半导体管芯104还可包含用于RF信号处理的集成无源器件(IPD)，诸如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在有源表面110上方形成导电层112。导电层112包括铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)、钛(Ti)、钛钨(TiW)或其他合适的导电材料的一个或多个层。导电层112用作与有源表面110上的电路(例如，二极管的阳极区和阴极区)电连接的接触焊盘。
图2a-图2k示出以晶圆级封装半导体管芯的工艺。图2a示出半导体衬底100的一部分。使用蒸镀、电解电镀、化学电镀、焊球滴落或丝网印刷工艺，将导电凸块材料沉积在导电层112上方。凸块材料可为Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，且具有任选的焊剂溶体。例如，凸块材料可为共熔Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合工艺，将凸块材料接合到导电层112。在一个实施方案中，通过在高于材料熔点的温度下加热材料来使凸块材料回流，以形成宽度为120μm，且高度为20μm的球或凸块120。在一些应用中，凸块120被第二次回流以改善与导电层112的电接触。在一个实施方案中，在凸块下金属化(UBM)层上方形成凸块120。凸块120还可压缩接合或热压接合到导电层112。凸块120表示可形成于导电层112上方的一种类型的互连结构。互连结构还可以使用焊丝、导电胶、柱形凸块、微凸块或其他电互连件。
在图2b中，使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或其他工艺在凸块120之间的有源表面110上形成厚绝缘层122。绝缘层122包含绝缘材料，诸如二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、氧化铪(HfO2)、苯并环丁烯(BCB)、聚酰亚胺(PI)、聚苯并唑(PBO)、模塑料、聚合物，或具有类似结构和绝缘特性的其他介电材料的一个或多个层。绝缘层122基本上填充有源表面110上方的凸块120之间的间隙。在一个实施方案中，绝缘层122形成在整个有源表面110上方并包围凸块120，以提供对有源表面110的后来形成的密封剂可能不能达到的覆盖率，如图2b-图2k和图3中所述。作为另外一种选择，绝缘层122形成在与每个凸块的至少一个侧面接触的凸块120之间。在这种情况下，参见图4a-图4b，凸块120与半导体管芯104的侧表面之间的区域保持没有绝缘层122。可以在凸块120之前形成绝缘层122，在这种情况下，在凸块的绝缘层中形成开口。
图2c示出具有形成在半导体管芯104上方的凸块120和绝缘层122的半导体衬底100的平面图。锯道106b的宽度大于锯道106a的宽度以补偿切割胶带沿x方向和y方向的扩张的差异(如果有的话)。图2b是沿图2c中的线2b-2b截取的剖面图。
在图2d中，具有凸块120和绝缘层122的半导体衬底100被定位成凸块朝向背面研磨胶带130取向。粘合剂层132接触凸块120和绝缘层122，并将半导体衬底100以晶圆形式固定到背面研磨胶带130。通过研磨机134将基极衬底材料102的一部分从背表面108去除，对于半导体晶圆100留下平面表面136，并且厚度T1为25-200μm。
在图2e中，将具有背面研磨胶带130的半导体衬底100反转，其中表面136朝向切割胶带140取向，该切割胶带包括可扩张聚合物基极材料140a和可扩张粘合剂层140b。将半导体衬底100安装到切割胶带140的粘合剂层140b。
在图2f中，在保持半导体管芯104的相对位置的同时，去除背面研磨胶带130并且通过等离子体蚀刻穿过锯道106切割半导体衬底100。等离子蚀刻的优点在于沿着锯道106形成精密侧表面以及在相同晶圆上形成不同锯道宽度，同时保持基极衬底材料的结构和完整性。作为另外一种选择，使用锯片或激光切割工具148将半导体衬底100切割。在切割后，半导体管芯104保持附连到切割胶带140。
在图2g中，切割胶带140沿x方向、y方向以及可能z方向扩张以赋予半导体管芯104的移动以引入间隙或空间150并且以增加所有相邻半导体管芯104之间的间距。通过沿z方向移动的竖直柱塞154或沿x方向和y方向移动的扩张台，切割胶带140可沿x方向、y方向和z方向(参见箭头152、153)扩张。在一个实施方案中，参见图2h，所有相邻的半导体管芯104之间的空间150具有75μm或更大的宽度。扩张后跨过所有半导体管芯104的宽度增加约10％-30％。
参见图1b，由于切割胶带140不一定在沿x方向和y方向扩张相同，所以锯道106a-106b的宽度可在相邻的半导体管芯104之间沿x方向或y方向不同，以补偿切割胶带沿x方向和y方向的不同扩张。
在图2i中，载体或临时衬底156包含牺牲基极材料，诸如包覆模制胶带、聚合物、氧化铍、硅、玻璃或其他适合于结构支撑的低成本刚性材料。在载体156上方形成界面层或双面胶带158作为临时粘合剂接合膜、蚀刻停止层或热释放层。将载体156和界面层158设置在凸块120、绝缘层122和空间150上方以用于结构支撑。
在图2j中，在半导体管芯104之间具有空间150的半导体组件160在设置在载体156和界面层158上时被反转，并且去除切割胶带140。使用糊剂印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、膜辅助模塑、旋涂或其他合适的涂覆器将密封剂或模塑料162沉积在半导体管芯104上方并进入空间150以覆盖半导体管芯的侧表面164。密封剂162可为聚合物复合材料，诸如环氧树脂与填料、环氧丙烯酸酯与填料，或者聚合物与合适填料。密封剂162不导电，提供物理支撑，并在环境中保护半导体器件免受外部元件和污染物影响。在形成凸块120之后以及在形成空间150之后沉积密封剂162。
在图2k中，将半导体组件160再次反转，其中凸块120和绝缘层122远离切割胶带166取向，该切割胶带包括聚合物基极材料166a和粘合剂层166b。将半导体组件160安装到切割胶带166的粘合剂层166b。通过UV光、化学蚀刻、机械剥离、化学机械平面化(CMP)、机械研磨、热烘焙、激光扫描或湿法剥离来去除载体156和界面层158以暴露凸块120和绝缘层122。使用锯片或激光切割工具172将沟道170完全穿过密封剂162并且进入切割胶带166中围绕每个半导体管芯104而形成。密封剂162的一部分保留在半导体管芯104的侧表面164上。
图3a示出切割后WLCSP 176，其中凸块120从绝缘层122暴露以用于外部互连。密封剂162覆盖半导体管芯104的侧表面164和表面136。在一个实施方案中，WLCSP 176的尺寸为235μm×440μm。图2a-图2k中描述的WLCSP工艺可以完整晶圆级封装(即，半导体管芯的包封和电互连)为每个半导体衬底100提供30％-40％的更多的半导体管芯104。WLCSP 176降低了制造成本并且增加了每个晶圆的管芯产量。图3b是WLCSP 176的平面图，其中凸块120从绝缘层122暴露并且密封剂162覆盖半导体管芯104的侧表面164。
图4a示出WLCSP 180的实施方案，其中绝缘层122形成在凸块120之间。在这种情况下，凸块120与半导体管芯104的侧表面164之间的区域没有绝缘层122。参考图2j，密封剂162覆盖有源表面110的未被绝缘层122覆盖的部分，例如在凸块200与半导体管芯104的侧表面164之间。在一个实施方案中，WLCSP 180的尺寸为235μm×440μm。WLCSP工艺可以完整晶圆级封装(即，半导体管芯的包封和电互连)为每个半导体衬底100提供30％-40％的更多的半导体管芯104。WLCSP 180降低了制造成本并且增加了每个晶圆的管芯产量。图4b是WLCSP 180的平面图，其中凸块120从绝缘层122暴露，并且密封剂162覆盖半导体管芯104的侧表面164以及有源表面110的一部分。
图5a-图5g示出以晶圆级用背面导电层封装半导体管芯的工艺。继续参见图2a，使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化在凸块120之间的有源表面110上形成厚绝缘层182。绝缘层182包含绝缘材料，诸如SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物，或具有类似结构和绝缘特性其他介电材料的一个或多个层。绝缘层182基本上填充凸块120之间的间隙并与有源表面110上的每个凸块的至少一个侧面接触。凸块120与半导体管芯104的侧表面之间的区域保持没有绝缘层182。
图5b示出具有形成在半导体管芯104上方的凸块120和绝缘层182的半导体衬底100的平面图。锯道106b的宽度大于锯道106a的宽度以补偿切割胶带沿x方向和y方向的任何不同扩张。图5a是沿图5b中的线5a-5a截取的剖面图。
在图5c中，具有凸块120和绝缘层182的半导体衬底100被定位成凸块朝向背面研磨胶带184取向。粘合剂层185接触凸块120和绝缘层182，并将半导体衬底100以晶圆形式固定到背面研磨胶带184。通过研磨机187将基极衬底材料102的一部分从背表面108去除，对于半导体晶圆100留下平面表面186，并且厚度T2为25-300μm。
在图5d中，使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在表面186上方形成导电层188。导电层188包括Al、Cu、Sn、Ni、Au、Ag、Ti、TiW或其他合适的导电材料的一个或多个层。导电层188减小半导体管芯104的导通电阻和电流密度。作为另外一种选择，导电层188可被图案化以提供增加的功能性或去除锯道上方的材料。
在图5e中，将具有背面研磨胶带184的半导体衬底100反转，其中导电层188朝向切割胶带190取向，该切割胶带包括可扩张聚合物基极材料190a和可扩张粘合剂层190b。将半导体衬底100安装到切割胶带190的粘合剂层190b。
在图5f中，去除背面研磨胶带184并且通过等离子体蚀刻穿过锯道106切割半导体衬底100。等离子蚀刻的优点在于沿锯道106形成精密侧表面，同时保持基极衬底材料的结构和完整性。作为另外一种选择，使用锯片或激光切割工具196将半导体衬底100切割。穿过锯道106内的导电层188进行破裂或切割，以允许切割胶带190的扩张和半导体管芯104的移动。在切割后，半导体管芯104保持附连到切割胶带190。
在图5g中，切割胶带190沿x方向、y方向以及可能z方向扩张以赋予半导体管芯104的移动以引入间隙或空间198并且以增加所有相邻半导体管芯104之间的间距。切割胶带190可通过沿z方向移动的竖直柱塞或沿x方向和y方向移动的扩张台而扩张，类似于图2g。在一个实施方案中，参见图2h，所有相邻的半导体管芯104之间的空间198具有75μm或更大的宽度。扩张后跨过所有半导体管芯104的宽度增加约10％-30％。
参见图1b，由于切割胶带190不一定在沿x方向和y方向扩张相同，所以锯道106a-106b的宽度可在相邻的半导体管芯104之间不同，以补偿切割胶带沿x方向和y方向的不同扩张。
在图5h中，载体或临时衬底200包含牺牲基极材料，诸如包覆模制胶带、聚合物、氧化铍、硅、玻璃或其他适合于结构支撑的低成本刚性材料。在载体200上方形成界面层或双面胶带202作为临时粘合剂接合膜、蚀刻停止层或热释放层。将载体200和界面层202设置在凸块120、绝缘层182和空间198上方以用于结构支撑。
在图5i中，在半导体管芯104之间具有空间198的半导体组件210在设置在载体200和界面层202上时被反转，并且去除切割胶带190。在去除切割胶带190的情况下，可以使用诸如喷水、CO2喷射之类的工艺或其他清洁方法来去除留在开口198中的管芯之间的任何金属188。使用糊剂印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、膜辅助模塑、旋涂或其他合适的涂覆器将密封剂或模塑料212沉积在半导体管芯104上方并进入空间198以覆盖半导体管芯的侧表面214。密封剂212可为聚合物复合材料，诸如环氧树脂与填料、环氧丙烯酸酯与填料，或者聚合物与合适填料。密封剂212不导电，提供物理支撑，并在环境中保护半导体器件免受外部元件和污染物影响。在形成凸块120之后以及在形成空间198之后沉积密封剂212。
在图5j中，将半导体组件210再次反转，其中凸块120和绝缘层182远离切割胶带216取向，该切割胶带包括聚合物基极材料216a和粘合剂层216b。将半导体组件210安装到切割胶带216的粘合剂层216b。通过UV光、化学蚀刻、机械剥离、CMP、机械研磨、热烘焙、激光扫描或湿法剥离来去除载体200和界面层202以暴露凸块120和绝缘层122。使用锯片或激光切割工具222将沟道220完全穿过密封剂212并且进入切割胶带216中围绕每个半导体管芯104而形成。密封剂212的一部分保留在半导体管芯104的侧表面214上。
图6a示出切割后WLCSP 226，其中凸块120从绝缘层182暴露以用于外部互连。密封剂212覆盖半导体管芯104的侧表面214、导电层188，以及表面186。在一个实施方案中，WLCSP 226的尺寸为235μm×440μm。图5a-图5j中描述的WLCSP工艺可为每个半导体衬底100提供30％-40％的更多的半导体管芯104，并且仍提供完整的晶圆级封装，即，半导体管芯的包封和电互连。WLCSP 226降低了制造成本并且增加了每个晶圆的管芯产量。图6b是WLCSP226的平面图，其中凸块120从绝缘层182暴露，并且密封剂212覆盖半导体管芯104的侧表面214以及有源表面110的一部分。
虽然已详细示出并描述了一个或多个实施方案，但技术人员将认识到，在不脱离本公开的范围的情况下，可对这些实施方案作出修改和变更。下文中列出了多个示例性实施方案，而其他实施方案也是可能的。
在第一实施方案中，制造半导体器件的方法包括以下步骤：提供半导体衬底，该半导体衬底包括多个半导体管芯，在半导体管芯之间具有锯道；在半导体管芯的第一表面上方形成多个凸块；在半导体管芯的第一表面上方在凸块之间形成绝缘层；穿过锯道切割半导体衬底同时维持半导体管芯的位置；赋予半导体管芯的移动以增加半导体管芯之间的空间；将密封剂沉积在半导体管芯上方并且进入半导体管芯之间的空间；以及穿过密封剂在半导体管芯之间形成沟道以分离半导体管芯。
在第二实施方案中，第一实施方案的方法还包括以下步骤：在半导体管芯的第一表面上方并且围绕凸块形成绝缘层。
在第三实施方案中，第一实施方案的方法还包括以下步骤：将密封剂沉积在第二半导体管芯的第一表面的一部分上方。
在第四实施方案中，第一实施方案的方法还包括以下步骤：去除半导体管芯的与半导体管芯的第一表面相对的第二表面的一部分。
在第五实施方案中，第一实施方案的方法还包括以下步骤：在半导体管芯的与半导体管芯的第一表面相对的第二表面上方形成导电层。
在第六实施方案中，第一实施方案的方法还包括以下步骤：将半导体衬底设置在切割胶带上方，以及使切割胶带扩张以赋予半导体管芯的移动以增加半导体管芯之间的空间。
在第七实施方案中，第一实施方案中半导体衬底上的第一半导体管芯与相邻的第二半导体管芯之间的第一距离大于半导体衬底上的第一半导体管芯与相邻的第三半导体管芯之间的第二距离。
在第八实施方案中，制造半导体器件的方法包括以下步骤：提供半导体衬底，该半导体衬底包括多个半导体管芯；在半导体管芯的第一表面上方形成多个凸块；在半导体管芯的第一表面上方在凸块之间形成绝缘层；切割半导体管芯之间的半导体衬底；扩大半导体管芯之间的空间；将密封剂沉积在半导体管芯上方并且进入半导体管芯之间的空间；以及穿过密封剂在半导体管芯之间形成沟道以分离半导体管芯。
在第九实施方案中，第八实施方案的方法还包括以下步骤：在半导体管芯的第一表面上方并且围绕凸块形成绝缘层。
在第十实施方案中，第八实施方案的方法还包括以下步骤：将密封剂沉积在第二半导体管芯的第一表面的一部分上方。
在第十一实施方案中，第八实施方案的方法还包括以下步骤：去除半导体管芯的与半导体管芯的第一表面相对的第二表面的一部分。
在第十二实施方案中，第八实施方案的方法还包括以下步骤：在半导体管芯的与半导体管芯的第一表面相对的第二表面上方形成导电层。
在第十三实施方案中，第八实施方案的方法还包括以下步骤：将半导体衬底设置在切割胶带上方，以及使切割胶带扩张以扩大半导体管芯之间的空间。
在第十四实施方案中，第八实施方案中半导体衬底上的第一半导体管芯与相邻的第二半导体管芯之间的第一距离大于半导体衬底上的第一半导体管芯与相邻的第三半导体管芯之间的第二距离。
在第十五实施方案中，半导体器件包括多个半导体管芯，在半导体管芯之间具有空间。多个凸块形成在半导体管芯的第一表面上方。绝缘层形成在凸块之间的半导体管芯的第一表面上方。密封剂沉积在半导体管芯上方并且进入半导体管芯之间的空间。沟道在半导体管芯之间穿过密封剂。
在第十六实施方案中，第十五实施方案的绝缘层在半导体管芯的第一表面上方并且围绕凸块形成。
在第十七实施方案中，第十五实施方案的密封剂沉积在第二半导体管芯的第一表面上方。
在第十八实施方案中，第十五实施方案的半导体器件还包括在半导体管芯的与半导体管芯的第一表面相对的第二表面上方形成的导电层。
在第十九实施方案中，第十五实施方案的半导体管芯之间的空间为至少75微米。
在第二十实施方案中，第十五实施方案的半导体管芯包括分立半导体器件。

Claims (13)

1.一种制造半导体器件的方法，其中，所述方法包括：
提供半导体衬底，所述半导体衬底包括多个半导体管芯，在所述多个半导体管芯之间具有锯道；
在提供所述半导体衬底后，在所述半导体管芯的第一表面上形成多个凸块；
在形成多个凸块后，在所述多个半导体管芯的所述第一表面上在所述凸块之间形成绝缘层；
在形成所述绝缘层后，将所述半导体衬底设置在切割胶带上；
在将所述半导体衬底设置在所述切割胶带上后，穿过所述锯道切割所述半导体衬底，同时维持所述多个半导体管芯在所述切割胶带上的位置；
在切割所述半导体衬底后，使所述切割胶带扩张以赋予所述多个半导体管芯的移动并增加所述多个半导体管芯之间的空间，其中，设置不同宽度的所述锯道以补偿所述切割胶带的非线性扩张；
在移动所述多个半导体管芯后，将密封剂沉积在所述多个半导体管芯上并且进入所述多个半导体管芯之间的所述空间；以及
在沉积所述密封剂后，穿过所述密封剂在所述多个半导体管芯之间形成沟道以分离所述多个半导体管芯。
2.根据权利要求1所述的方法，其中，所述方法还包括在所述半导体管芯的所述第一表面上并且围绕所述凸块形成所述绝缘层。
3.根据权利要求1所述的方法，其中，所述方法还包括将所述密封剂沉积在所述半导体管芯的所述第一表面的一部分上。
4.根据权利要求1所述的方法，其中，所述方法还包括去除所述半导体管芯的与所述半导体管芯的所述第一表面相对的第二表面的一部分。
5.根据权利要求1所述的方法，其中，所述半导体衬底上的第一半导体管芯与相邻的第二半导体管芯之间的第一距离大于所述半导体衬底上的所述第一半导体管芯与相邻的第三半导体管芯之间的第二距离。
6.一种制造半导体器件的方法，其中，所述方法包括：
提供半导体衬底，所述半导体衬底包括多个半导体管芯；
在提供所述半导体衬底后，在所述半导体管芯的第一表面上形成多个凸块；
在形成多个凸块后，在所述半导体管芯的所述第一表面上在所述凸块之间形成绝缘层；
在形成所述绝缘层后，将所述半导体衬底设置在切割胶带上；
在将所述半导体衬底设置在所述切割胶带上后，切割所述半导体管芯之间的所述半导体衬底以在所述半导体管芯之间形成空间，其中设置不同宽度的所述空间以补偿所述切割胶带的非线性扩张；
在切割所述半导体衬底后，使所述切割胶带扩张以扩大所述半导体管芯之间的空间；
在扩大所述空间后，将密封剂沉积在所述半导体管芯上并且进入所述半导体管芯之间的所述空间；以及
在沉积所述密封剂后，穿过所述密封剂在所述半导体管芯之间形成沟道以分离所述半导体管芯。
7.根据权利要求6所述的方法，其中，所述方法还包括在所述半导体管芯的所述第一表面上并且围绕所述凸块形成所述绝缘层。
8.根据权利要求6所述的方法，其中，所述方法还包括将所述密封剂沉积在所述半导体管芯的所述第一表面的一部分上。
9.根据权利要求6所述的方法，其中，所述方法还包括在所述半导体管芯的与所述半导体管芯的所述第一表面相对的第二表面上形成导电层。
10.一种制造半导体器件的方法，其中，所述方法包括：
在半导体衬底的第一表面上形成多个半导体管芯；
在形成多个半导体管芯后，在所述半导体管芯的第一表面上形成多个凸块；
在形成所述多个凸块后，在所述多个凸块之间形成绝缘层；
在形成所述绝缘层后，将切割胶带施加到与所述第一表面相对的所述多个半导体管芯的第二表面上；
在施加所述切割胶带后，完全穿过所述半导体衬底在所述半导体管芯之间形成多个第一沟道，其中，设置不同宽度的所述第一沟道以补偿所述切割胶带的非线性扩张；
在形成所述多个第一沟道后，通过使所述切割胶带扩张来加宽所述多个第一沟道；
在加宽所述多个第一沟道后，使用密封剂填充所述多个第一沟道；以及
在填充所述多个第一沟道后，穿过所述密封剂形成第二沟道以分离所述多个半导体管芯。
11.一种制造半导体器件的方法，其中，所述方法包括：
在半导体衬底所包括的多个半导体管芯的第一表面上形成多个凸块；
提供第一载体；
将所述半导体衬底设置在所述第一载体上；
切割所述多个半导体管芯之间的半导体衬底以在所述多个半导体管芯之间形成空间，同时维持所述多个半导体管芯在所述第一载体上的位置，其中，设置不同宽度的所述多个半导体管芯之间的空间以补偿所述第一载体的非线性扩张；
使所述第一载体扩张以扩大在所述第一载体上的所述多个半导体管芯之间的空间；
将所述半导体管芯设置在第二载体上，同时维持在所述第一载体上的扩大的空间，所述多个凸块朝向所述第二载体取向；
移除所述第一载体；
将密封剂沉积在所述多个半导体管芯上并且进入在所述第二载体上的所述多个半导体管芯之间的空间；以及
穿过所述密封剂在所述多个半导体管芯之间形成沟道以分离所述多个半导体管芯。
12.一种制造半导体器件的方法，其中，所述方法包括：
提供多个半导体管芯，所述多个半导体管芯之间具有间隔，其中，设置不同宽度的所述多个半导体管芯之间的间隔以补偿切割胶带的非线性扩张；
在所述多个半导体管芯的第一表面上形成多个凸块；
在所述多个半导体管芯的第一表面上在所述多个凸块之间形成绝缘层；
将所述多个半导体管芯设置在所述切割胶带上；
使所述切割胶带扩张以赋予所述多个半导体管芯的移动并增加所述多个半导体管芯之间的间隔；
将密封剂沉积在所述多个半导体管芯上并且进入所述多个半导体管芯之间的空间；以及
穿过所述密封剂在所述多个半导体管芯之间形成沟道以分离所述多个半导体管芯。
13.根据权利要求12所述的方法，其中，所述方法还包括切割在所述切割胶带上的所述多个半导体管芯。
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